Mon Apr 20 04:23:24 2020 UTC ()
 Whitespace fix. No functional change.


(msaitoh)
diff -r1.183 -r1.184 src/sys/arch/x86/x86/cpu.c

cvs diff -r1.183 -r1.184 src/sys/arch/x86/x86/cpu.c (expand / switch to unified diff)

--- src/sys/arch/x86/x86/cpu.c 2020/04/10 14:35:26 1.183
+++ src/sys/arch/x86/x86/cpu.c 2020/04/20 04:23:23 1.184
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpu.c,v 1.183 2020/04/10 14:35:26 bouyer Exp $ */ 1/* $NetBSD: cpu.c,v 1.184 2020/04/20 04:23:23 msaitoh Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2000-2012 NetBSD Foundation, Inc. 4 * Copyright (c) 2000-2012 NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran. 8 * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -52,27 +52,27 @@ @@ -52,27 +52,27 @@
52 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
54 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 54 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
61 * SUCH DAMAGE. 61 * SUCH DAMAGE.
62 */ 62 */
63 63
64#include <sys/cdefs.h> 64#include <sys/cdefs.h>
65__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.183 2020/04/10 14:35:26 bouyer Exp $"); 65__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.184 2020/04/20 04:23:23 msaitoh Exp $");
66 66
67#include "opt_ddb.h" 67#include "opt_ddb.h"
68#include "opt_mpbios.h" /* for MPDEBUG */ 68#include "opt_mpbios.h" /* for MPDEBUG */
69#include "opt_mtrr.h" 69#include "opt_mtrr.h"
70#include "opt_multiprocessor.h" 70#include "opt_multiprocessor.h"
71#include "opt_svs.h" 71#include "opt_svs.h"
72 72
73#include "lapic.h" 73#include "lapic.h"
74#include "ioapic.h" 74#include "ioapic.h"
75#include "acpica.h" 75#include "acpica.h"
76 76
77#include <sys/param.h> 77#include <sys/param.h>
78#include <sys/proc.h> 78#include <sys/proc.h>
@@ -188,29 +188,29 @@ uint32_t cpu_feature[7] __read_mostly; / @@ -188,29 +188,29 @@ uint32_t cpu_feature[7] __read_mostly; /
188 * [6] structured extended features cpuid.7:%ecx 188 * [6] structured extended features cpuid.7:%ecx
189 */ 189 */
190 190
191#ifdef MULTIPROCESSOR 191#ifdef MULTIPROCESSOR
192bool x86_mp_online; 192bool x86_mp_online;
193paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 193paddr_t mp_trampoline_paddr = MP_TRAMPOLINE;
194#endif 194#endif
195#if NLAPIC > 0 195#if NLAPIC > 0
196static vaddr_t cmos_data_mapping; 196static vaddr_t cmos_data_mapping;
197#endif 197#endif
198struct cpu_info *cpu_starting; 198struct cpu_info *cpu_starting;
199 199
200#ifdef MULTIPROCESSOR 200#ifdef MULTIPROCESSOR
201void cpu_hatch(void *); 201void cpu_hatch(void *);
202static void cpu_boot_secondary(struct cpu_info *ci); 202static void cpu_boot_secondary(struct cpu_info *ci);
203static void cpu_start_secondary(struct cpu_info *ci); 203static void cpu_start_secondary(struct cpu_info *ci);
204#if NLAPIC > 0 204#if NLAPIC > 0
205static void cpu_copy_trampoline(paddr_t); 205static void cpu_copy_trampoline(paddr_t);
206#endif 206#endif
207#endif /* MULTIPROCESSOR */ 207#endif /* MULTIPROCESSOR */
208 208
209/* 209/*
210 * Runs once per boot once multiprocessor goo has been detected and 210 * Runs once per boot once multiprocessor goo has been detected and
211 * the local APIC on the boot processor has been mapped. 211 * the local APIC on the boot processor has been mapped.
212 * 212 *
213 * Called from lapic_boot_init() (from mpbios_scan()). 213 * Called from lapic_boot_init() (from mpbios_scan()).
214 */ 214 */
215#if NLAPIC > 0 215#if NLAPIC > 0
216void 216void
@@ -266,51 +266,51 @@ cpu_pcpuarea_init(struct cpu_info *ci) @@ -266,51 +266,51 @@ cpu_pcpuarea_init(struct cpu_info *ci)
266 266
267static void 267static void
268cpu_vm_init(struct cpu_info *ci) 268cpu_vm_init(struct cpu_info *ci)
269{ 269{
270 int ncolors = 2, i; 270 int ncolors = 2, i;
271 271
272 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 272 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) {
273 struct x86_cache_info *cai; 273 struct x86_cache_info *cai;
274 int tcolors; 274 int tcolors;
275 275
276 cai = &ci->ci_cinfo[i]; 276 cai = &ci->ci_cinfo[i];
277 277
278 tcolors = atop(cai->cai_totalsize); 278 tcolors = atop(cai->cai_totalsize);
279 switch(cai->cai_associativity) { 279 switch (cai->cai_associativity) {
280 case 0xff: 280 case 0xff:
281 tcolors = 1; /* fully associative */ 281 tcolors = 1; /* fully associative */
282 break; 282 break;
283 case 0: 283 case 0:
284 case 1: 284 case 1:
285 break; 285 break;
286 default: 286 default:
287 tcolors /= cai->cai_associativity; 287 tcolors /= cai->cai_associativity;
288 } 288 }
289 ncolors = uimax(ncolors, tcolors); 289 ncolors = uimax(ncolors, tcolors);
290 /* 290 /*
291 * If the desired number of colors is not a power of 291 * If the desired number of colors is not a power of
292 * two, it won't be good. Find the greatest power of 292 * two, it won't be good. Find the greatest power of
293 * two which is an even divisor of the number of colors, 293 * two which is an even divisor of the number of colors,
294 * to preserve even coloring of pages. 294 * to preserve even coloring of pages.
295 */ 295 */
296 if (ncolors & (ncolors - 1) ) { 296 if (ncolors & (ncolors - 1) ) {
297 int try, picked = 1; 297 int try, picked = 1;
298 for (try = 1; try < ncolors; try *= 2) { 298 for (try = 1; try < ncolors; try *= 2) {
299 if (ncolors % try == 0) picked = try; 299 if (ncolors % try == 0) picked = try;
300 } 300 }
301 if (picked == 1) { 301 if (picked == 1) {
302 panic("desired number of cache colors %d is " 302 panic("desired number of cache colors %d is "
303 " > 1, but not even!", ncolors); 303 " > 1, but not even!", ncolors);
304 } 304 }
305 ncolors = picked; 305 ncolors = picked;
306 } 306 }
307 } 307 }
308 308
309 /* 309 /*
310 * Knowing the size of the largest cache on this CPU, potentially 310 * Knowing the size of the largest cache on this CPU, potentially
311 * re-color our pages. 311 * re-color our pages.
312 */ 312 */
313 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 313 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors);
314 uvm_page_recolor(ncolors); 314 uvm_page_recolor(ncolors);
315 315
316 pmap_tlb_cpu_init(ci); 316 pmap_tlb_cpu_init(ci);
@@ -1008,27 +1008,27 @@ cpu_hatch(void *v) @@ -1008,27 +1008,27 @@ cpu_hatch(void *v)
1008#if defined(DDB) 1008#if defined(DDB)
1009 1009
1010#include <ddb/db_output.h> 1010#include <ddb/db_output.h>
1011#include <machine/db_machdep.h> 1011#include <machine/db_machdep.h>
1012 1012
1013/* 1013/*
1014 * Dump CPU information from ddb. 1014 * Dump CPU information from ddb.
1015 */ 1015 */
1016void 1016void
1017cpu_debug_dump(void) 1017cpu_debug_dump(void)
1018{ 1018{
1019 struct cpu_info *ci; 1019 struct cpu_info *ci;
1020 CPU_INFO_ITERATOR cii; 1020 CPU_INFO_ITERATOR cii;
1021 const char sixtyfour64space[] =  1021 const char sixtyfour64space[] =
1022#ifdef _LP64 1022#ifdef _LP64
1023 " " 1023 " "
1024#endif 1024#endif
1025 ""; 1025 "";
1026 1026
1027 db_printf("addr %sdev id flags ipis spl curlwp " 1027 db_printf("addr %sdev id flags ipis spl curlwp "
1028 "\n", sixtyfour64space); 1028 "\n", sixtyfour64space);
1029 for (CPU_INFO_FOREACH(cii, ci)) { 1029 for (CPU_INFO_FOREACH(cii, ci)) {
1030 db_printf("%p %s %ld %x %x %d %10p\n", 1030 db_printf("%p %s %ld %x %x %d %10p\n",
1031 ci, 1031 ci,
1032 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 1032 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev),
1033 (long)ci->ci_cpuid, 1033 (long)ci->ci_cpuid,
1034 ci->ci_flags, ci->ci_ipis, ci->ci_ilevel, 1034 ci->ci_flags, ci->ci_ipis, ci->ci_ilevel,