 @@ -1,14 +1,14 @@
-/* $NetBSD: sun4i_a10_ccu.c,v 1.10 2019/01/22 23:06:49 jmcneill Exp $ */
+/* $NetBSD: sun4i_a10_ccu.c,v 1.10.4.1 2020/05/07 17:05:07 martin Exp $ */
 /*-
  * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -18,27 +18,27 @@
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.10 2019/01/22 23:06:49 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.10.4.1 2020/05/07 17:05:07 martin Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/systm.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/sunxi/sunxi_ccu.h>
 #include <arm/sunxi/sun4i_a10_ccu.h>
 #include <arm/sunxi/sun7i_a20_ccu.h>
 #define	PLL1_CFG_REG		0x000
 @@ -68,26 +68,28 @@ __KERNEL_RCSID(1, "$NetBSD: sun4i_a10_cc
 #define	FE1_CFG_REG		0x110
 #define	MP_CFG_REG		0x114
 #define	LCD0CH0_CFG_REG		0x118
 #define	LCD1CH0_CFG_REG		0x11c
 #define LCD0CH1_CFG_REG		0x12c
 #define LCD1CH1_CFG_REG		0x130
 #define	CSI_CFG_REG		0x134
 #define	VE_CFG_REG		0x13c
 #define	AUDIO_CODEC_SCLK_CFG_REG 0x140
 #define	LVDS_CFG_REG 		0x14c
 #define	HDMI_CLOCK_CFG_REG	0x150
 #define	MALI_CLOCK_CFG_REG	0x154
 #define	IEP_SCLK_CFG_REG	0x160
 #define	CLK_OUTA_REG		0x1f0
 #define	CLK_OUTB_REG		0x1f4
 static int sun4i_a10_ccu_match(device_t, cfdata_t, void *);
 static void sun4i_a10_ccu_attach(device_t, device_t, void *);
 enum sun4i_a10_ccu_type {
 	CCU_A10 = 1,
 	CCU_A20,
 };
 static const struct of_compat_data compat_data[] = {
 	{ "allwinner,sun4i-a10-ccu",	CCU_A10 },
 	{ "allwinner,sun7i-a20-ccu",	CCU_A20 },
 	{ NULL }
 @@ -109,26 +111,27 @@ static struct sunxi_ccu_reset sun4i_a10_
 	SUNXI_CCU_RESET(A10_RST_TCON1, LCD1CH0_CFG_REG, 30),
 	SUNXI_CCU_RESET(A10_RST_LVDS, LVDS_CFG_REG, 0),
 };
 static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" };
 static const char *axi_parents[] = { "cpu" };
 static const char *ahb_parents[] = { "axi", "pll_periph", "pll_periph_base" };
 static const char *apb0_parents[] = { "ahb" };
 static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc" };
 static const char *mod_parents[] = { "osc24m", "pll_periph", "pll_ddr_other" };
 static const char *sata_parents[] = { "pll6_periph_sata", "external" };
 static const char *de_parents[] = { "pll_video0", "pll_video1", "pll_ddr_other" };
 static const char *lcd_parents[] = { "pll_video0", "pll_video1", "pll_video0x2", "pll_video1x2" };
 static const char *out_parents[] = { "losc" /* really OSC24MHz/750 */, "losc", "osc24m" };
 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_pll1_table[] = {
 	{ 1008000000, 21, 1, 0, 0 },
 	{  960000000, 20, 1, 0, 0 },
 	{  912000000, 19, 1, 0, 0 },
 	{  864000000, 18, 1, 0, 0 },
 	{  720000000, 30, 0, 0, 0 },
 	{  624000000, 26, 0, 0, 0 },
 	{  528000000, 22, 0, 0, 0 },
 	{  312000000, 13, 0, 0, 0 },
 	{  144000000, 12, 0, 0, 1 },
 	{          0 }
 };
 @@ -438,26 +441,43 @@ static struct sunxi_ccu_clk sun4i_a10_cc
 	    .get_rate = sunxi_ccu_div_get_rate,
 	    .set_rate = sun4i_a10_ccu_lcd1ch1_set_rate,
 	    .set_parent = sunxi_ccu_div_set_parent,
 	    .get_parent = sunxi_ccu_div_get_parent,
 	    },
 	SUNXI_CCU_DIV_GATE(A10_CLK_HDMI, "hdmi-mod", lcd_parents,
 	    HDMI_CLOCK_CFG_REG,		/* reg */
 	    __BITS(3,0),		/* div */
 	    __BITS(25,24),		/* sel */
 	    __BIT(31),			/* enable */
 				/* flags */
 	    ),
 	/* A20 specific */
 	SUNXI_CCU_NM(A20_CLK_OUT_A, "outa", out_parents,
 	    CLK_OUTA_REG,		/* reg */
 	    __BITS(21,20),		/* n */
 	    __BITS(12,8),		/* m */
 	    __BITS(25,24),		/* sel */
 	    __BIT(31),			/* enable */
 	    SUNXI_CCU_NM_POWER_OF_TWO),
 	SUNXI_CCU_NM(A20_CLK_OUT_B, "outb", out_parents,
 	    CLK_OUTB_REG,		/* reg */
 	    __BITS(21,20),		/* n */
 	    __BITS(12,8),		/* m */
 	    __BITS(25,24),		/* sel */
 	    __BIT(31),			/* enable */
 	    SUNXI_CCU_NM_POWER_OF_TWO),
 	/* AHB_GATING_REG0 */
 	SUNXI_CCU_GATE(A10_CLK_AHB_OTG, "ahb-otg", "ahb",
 	    AHB_GATING_REG0, 0),
 	SUNXI_CCU_GATE(A10_CLK_AHB_EHCI0, "ahb-ehci0", "ahb",
 	    AHB_GATING_REG0, 1),
 	SUNXI_CCU_GATE(A10_CLK_AHB_OHCI0, "ahb-ohci0", "ahb",
 	    AHB_GATING_REG0, 2),
 	SUNXI_CCU_GATE(A10_CLK_AHB_EHCI1, "ahb-ehci1", "ahb",
 	    AHB_GATING_REG0, 3),
 	SUNXI_CCU_GATE(A10_CLK_AHB_OHCI1, "ahb-ohci1", "ahb",
 	    AHB_GATING_REG0, 4),
 	SUNXI_CCU_GATE(A10_CLK_AHB_SS, "ahb-ss", "ahb",
 	    AHB_GATING_REG0, 5),