 @@ -1,14 +1,14 @@
-/*	$NetBSD: pmap.c,v 1.75 2020/05/15 05:39:15 skrll Exp $	*/
+/*	$NetBSD: pmap.c,v 1.76 2020/06/01 02:42:24 ryo Exp $	*/
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.75 2020/05/15 05:39:15 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.76 2020/06/01 02:42:24 ryo Exp $");
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
 #include "opt_multiprocessor.h"
 #include "opt_pmap.h"
 #include "opt_uvmhist.h"
 #include <sys/param.h>
 #include <sys/types.h>
 #include <sys/kmem.h>
 #include <sys/vmem.h>
 #include <sys/atomic.h>
 #include <sys/asan.h>
 @@ -161,37 +161,33 @@ PMAP_COUNTER(unwire_failure, "pmap_unwir
 			if ((asid) == 0)				\
 				aarch64_tlbi_by_va_ll((va));		\
 			else						\
 				aarch64_tlbi_by_asid_va_ll((asid), (va)); \
 		} else {						\
 			if ((asid) == 0)				\
 				aarch64_tlbi_by_va((va));		\
 			else						\
 				aarch64_tlbi_by_asid_va((asid), (va));	\
 		}							\
 	} while (0/*CONSTCOND*/)
 /*
- * aarch64 require write permission in pte to invalidate instruction cache.
+ * require access permission in pte to invalidate instruction cache.
- * changing pte to writable temporarly before cpu_icache_sync_range().
+ * change the pte to accessible temporarly before cpu_icache_sync_range().
  * this macro modifies PTE (*ptep). need to update PTE after this.
  */
 #define PTE_ICACHE_SYNC_PAGE(pte, ptep, pm, va, ll)			\
 	do {								\
-		pt_entry_t tpte;					\
+		atomic_swap_64((ptep), (pte) | LX_BLKPAG_AF);		\
 		tpte = (pte) & ~(LX_BLKPAG_AF|LX_BLKPAG_AP);		\
 		tpte |= (LX_BLKPAG_AF|LX_BLKPAG_AP_RW);			\
 		tpte |= (LX_BLKPAG_UXN|LX_BLKPAG_PXN);			\
 		atomic_swap_64((ptep), tpte);				\
 		AARCH64_TLBI_BY_ASID_VA((pm)->pm_asid, (va), (ll));	\
 		cpu_icache_sync_range((va), PAGE_SIZE);			\
 	} while (0/*CONSTCOND*/)
 #define VM_PAGE_TO_PP(pg)	(&(pg)->mdpage.mdpg_pp)
 struct pv_entry {
 	LIST_ENTRY(pv_entry) pv_link;
 	struct pmap *pv_pmap;
 	vaddr_t pv_va;
 	paddr_t pv_pa;		/* debug */
 	pt_entry_t *pv_ptep;	/* for fast pte lookup */
 };
 @@ -1318,27 +1314,27 @@ pmap_protect(struct pmap *pm, vaddr_t sv
+		}
 #ifdef UVMHIST
 		opte = pte;
 #endif
 		executable = l3pte_executable(pte, user);
 		pte = _pmap_pte_adjust_prot(pte, prot, mdattr, user);
 		if (!executable && (prot & VM_PROT_EXECUTE)) {
 			/* non-exec -> exec */
 			UVMHIST_LOG(pmaphist, "icache_sync: "
 			    "pm=%p, va=%016lx, pte: %016lx -> %016lx",
 			    pm, va, opte, pte);
-			if (!l3pte_writable(pte)) {
+			if (!l3pte_readable(pte)) {
 				PTE_ICACHE_SYNC_PAGE(pte, ptep, pm, va, true);
 				atomic_swap_64(ptep, pte);
 				AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true);
 			} else {
 				atomic_swap_64(ptep, pte);
 				AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true);
 				cpu_icache_sync_range(va, PAGE_SIZE);
+			}
 		} else {
 			atomic_swap_64(ptep, pte);
 			AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true);
+		}
+	}
 @@ -1879,27 +1875,27 @@ _pmap_enter(struct pmap *pm, vaddr_t va,
 	if (flags & PMAP_WIRED)
 		attr |= LX_BLKPAG_OS_WIRED;
 #ifdef MULTIPROCESSOR
 	attr |= LX_BLKPAG_SH_IS;
 #endif
 	pte = pa | attr;
 	if (need_sync_icache) {
 		/* non-exec -> exec */
 		UVMHIST_LOG(pmaphist,
 		    "icache_sync: pm=%p, va=%016lx, pte: %016lx -> %016lx",
 		    pm, va, opte, pte);
-		if (!l3pte_writable(pte)) {
+		if (!l3pte_readable(pte)) {
 			PTE_ICACHE_SYNC_PAGE(pte, ptep, pm, va, l3only);
 			atomic_swap_64(ptep, pte);
 			AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va ,true);
 		} else {
 			atomic_swap_64(ptep, pte);
 			AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, l3only);
 			cpu_icache_sync_range(va, PAGE_SIZE);
+		}
 	} else {
 		atomic_swap_64(ptep, pte);
 		AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, l3only);
+	}