Wed Jun 24 08:27:47 2020 UTC ()
Fix bug with incorrect range calculation when doing icache sync.
This is called by sysarch(ARM_SYNC_ICACHE) from aarch32 (compat_netbsd32) emul process.

pointed out by rin@, thanks.

XXX pullup-9


(ryo)
diff -r1.78 -r1.79 src/sys/arch/aarch64/aarch64/pmap.c
cvs diff -r1.78 -r1.79 src/sys/arch/aarch64/aarch64/pmap.c (expand / switch to unified diff)

--- src/sys/arch/aarch64/aarch64/pmap.c 2020/06/14 21:47:14 1.78
+++ src/sys/arch/aarch64/aarch64/pmap.c 2020/06/24 08:27:47 1.79
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: pmap.c,v 1.78 2020/06/14 21:47:14 ad Exp $ */ 1/* $NetBSD: pmap.c,v 1.79 2020/06/24 08:27:47 ryo Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org> 4 * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -17,27 +17,27 @@ @@ -17,27 +17,27 @@
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE. 26 * POSSIBILITY OF SUCH DAMAGE.
27 */ 27 */
28 28
29#include <sys/cdefs.h> 29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.78 2020/06/14 21:47:14 ad Exp $"); 30__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.79 2020/06/24 08:27:47 ryo Exp $");
31 31
32#include "opt_arm_debug.h" 32#include "opt_arm_debug.h"
33#include "opt_ddb.h" 33#include "opt_ddb.h"
34#include "opt_multiprocessor.h" 34#include "opt_multiprocessor.h"
35#include "opt_pmap.h" 35#include "opt_pmap.h"
36#include "opt_uvmhist.h" 36#include "opt_uvmhist.h"
37 37
38#include <sys/param.h> 38#include <sys/param.h>
39#include <sys/types.h> 39#include <sys/types.h>
40#include <sys/kmem.h> 40#include <sys/kmem.h>
41#include <sys/vmem.h> 41#include <sys/vmem.h>
42#include <sys/atomic.h> 42#include <sys/atomic.h>
43#include <sys/asan.h> 43#include <sys/asan.h>
@@ -903,27 +903,27 @@ pmap_icache_sync_range(pmap_t pm, vaddr_ @@ -903,27 +903,27 @@ pmap_icache_sync_range(pmap_t pm, vaddr_
903 for (va = sva; va < eva; va = (va + blocksize) & ~(blocksize - 1)) { 903 for (va = sva; va < eva; va = (va + blocksize) & ~(blocksize - 1)) {
904 /* va is belong to the same L3 table as before? */ 904 /* va is belong to the same L3 table as before? */
905 if ((blocksize == L3_SIZE) && ((va & L3INDEXMASK) != 0)) { 905 if ((blocksize == L3_SIZE) && ((va & L3INDEXMASK) != 0)) {
906 ptep++; 906 ptep++;
907 } else { 907 } else {
908 ptep = _pmap_pte_lookup_bs(pm, va, &blocksize); 908 ptep = _pmap_pte_lookup_bs(pm, va, &blocksize);
909 if (ptep == NULL) 909 if (ptep == NULL)
910 break; 910 break;
911 } 911 }
912 912
913 pte = *ptep; 913 pte = *ptep;
914 if (lxpde_valid(pte)) { 914 if (lxpde_valid(pte)) {
915 vaddr_t eob = (va + blocksize) & ~(blocksize - 1); 915 vaddr_t eob = (va + blocksize) & ~(blocksize - 1);
916 vsize_t len = ulmin(eva, eob - va); 916 vsize_t len = ulmin(eva, eob) - va;
917 917
918 if (l3pte_writable(pte)) { 918 if (l3pte_writable(pte)) {
919 cpu_icache_sync_range(va, len); 919 cpu_icache_sync_range(va, len);
920 } else { 920 } else {
921 /* 921 /*
922 * change to writable temporally 922 * change to writable temporally
923 * to do cpu_icache_sync_range() 923 * to do cpu_icache_sync_range()
924 */ 924 */
925 pt_entry_t opte = pte; 925 pt_entry_t opte = pte;
926 pte = pte & ~(LX_BLKPAG_AF|LX_BLKPAG_AP); 926 pte = pte & ~(LX_BLKPAG_AF|LX_BLKPAG_AP);
927 pte |= (LX_BLKPAG_AF|LX_BLKPAG_AP_RW); 927 pte |= (LX_BLKPAG_AF|LX_BLKPAG_AP_RW);
928 atomic_swap_64(ptep, pte); 928 atomic_swap_64(ptep, pte);
929 AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true); 929 AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true);