 @@ -1,464 +1,455 @@
-/*	$NetBSD: cpufunc.S,v 1.62 2020/06/15 20:27:30 riastradh Exp $	*/
+/*	$NetBSD: cpufunc.S,v 1.63 2020/06/24 18:09:37 maxv Exp $	*/
 /*
  * Copyright (c) 1998, 2007, 2008, 2020 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum, and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/errno.h>
 #include <machine/asm.h>
 #include <machine/frameasm.h>
 #include <machine/specialreg.h>
 #include <machine/segments.h>
 #include "opt_xen.h"
 #include "opt_svs.h"
 #include "assym.h"
 /* Small and slow, so align less. */
 #undef _ALIGN_TEXT
 #define	_ALIGN_TEXT	.align 8
 ENTRY(x86_lfence)
 	lfence
 	ret
 END(x86_lfence)
 ENTRY(x86_sfence)
 	sfence
 	ret
 END(x86_sfence)
 ENTRY(x86_mfence)
 	mfence
 	ret
 END(x86_mfence)
 #ifndef XENPV
 ENTRY(invlpg)
 #ifdef SVS
 	movb	_C_LABEL(svs_pcid),%al
 	testb	%al,%al
 	jz	1f
 	pushq	%rdi
 	pushq	$PMAP_PCID_USER
 	movq	$INVPCID_ADDRESS,%rax
 	invpcid	(%rsp),%rax
 	addq	$16,%rsp
 :	/* FALLTHROUGH */
 #endif
 	invlpg	(%rdi)
 	ret
 END(invlpg)
 ENTRY(lgdt)
 	/* Reload the descriptor table. */
 	movq	%rdi,%rax
 	lgdt	(%rax)
 	/* Flush the prefetch queue. */
 	jmp	1f
 	nop
 :	jmp	_C_LABEL(lgdt_finish)
 END(lgdt)
 ENTRY(lidt)
 	lidt	(%rdi)
 	ret
 END(lidt)
 ENTRY(lldt)
 	cmpl	%edi, CPUVAR(CURLDT)
 	jne	1f
 	ret
 :
 	movl	%edi, CPUVAR(CURLDT)
 	lldt	%di
 	ret
 END(lldt)
 ENTRY(ltr)
 	ltr	%di
 	ret
 END(ltr)
 ENTRY(tlbflushg)
 	movq	%cr4, %rax
 	testq	$CR4_PGE, %rax
 	jz	tlbflush
 	movq	%rax, %rdx
 	andq	$~CR4_PGE, %rdx
 	movq	%rdx, %cr4
 	movq	%rax, %cr4
 	ret
 END(tlbflushg)
 ENTRY(tlbflush)
 #ifdef SVS
 	movb	_C_LABEL(svs_pcid),%al
 	testb	%al,%al
 	jz	1f
 	xorq	%rax,%rax
 	pushq	%rax
 	pushq	%rax
 	movq	$INVPCID_ALL_NONGLOBAL,%rax
 	invpcid	(%rsp),%rax
 	addq	$16,%rsp
 	ret
 #endif
 :	movq	%cr3, %rax
 	movq	%rax, %cr3
 	ret
 END(tlbflush)
 ENTRY(wbinvd)
 	wbinvd
 	ret
 END(wbinvd)
 ENTRY(setusergs)
 	CLI(ax)
 	swapgs
 	movw	%di, %gs
 	swapgs
 	STI(ax)
 	ret
 END(setusergs)
 ENTRY(x86_read_flags)
 	pushfq
 	popq	%rax
 	KMSAN_INIT_RET(8)
 	ret
 END(x86_read_flags)
 STRONG_ALIAS(x86_read_psl,x86_read_flags)
 ENTRY(x86_write_flags)
 	pushq	%rdi
 	popfq
 	ret
 END(x86_write_flags)
 STRONG_ALIAS(x86_write_psl,x86_write_flags)
 /*
  * %rdi = name
  * %rsi = sel
  */
 ENTRY(x86_hotpatch)
 	/* save RFLAGS, and disable intrs */
 	pushfq
 	cli
 	/* save CR0, and disable WP */
 	movq	%cr0,%rcx
 	pushq	%rcx
 	andq	$~CR0_WP,%rcx
 	movq	%rcx,%cr0
 	callq	_C_LABEL(x86_hotpatch_apply)
 	/* write back and invalidate cache */
 	wbinvd
 	/* restore CR0 */
 	popq	%rcx
 	movq	%rcx,%cr0
 	/* flush instruction pipeline */
 	pushq	%rax
 	callq	x86_flush
 	popq	%rax
 	/* clean up */
 	movq	%rax,%rdi
 	callq	_C_LABEL(x86_hotpatch_cleanup)
 	/* restore RFLAGS */
 	popfq
 	ret
 END(x86_hotpatch)
 #endif /* !XENPV */
 /*
  * cpu_counter and cpu_counter32 could be exact same, but KMSAN needs to have
  * the correct size of the return value.
  */
 #define SERIALIZE_lfence	lfence
 #define SERIALIZE_mfence	mfence
 #define ADD_counter32	addl	CPUVAR(CC_SKEW), %eax
 #define ADD_counter	shlq	$32, %rdx		;\
 			orq	%rdx, %rax		;\
 			addq	CPUVAR(CC_SKEW), %rax
 #define RSIZE_counter32	4
 #define RSIZE_counter	8
 #define CPU_COUNTER_FENCE(counter, fence)	\
 ENTRY(cpu_ ## counter ## _ ## fence)		;\
 	movq	CPUVAR(CURLWP), %rcx		;\
 :						;\
 	movq	L_NCSW(%rcx), %rdi		;\
 	SERIALIZE_ ## fence			;\
 	rdtsc					;\
 	ADD_ ## counter				;\
 	cmpq	%rdi, L_NCSW(%rcx)		;\
 	jne	2f				;\
 	KMSAN_INIT_RET(RSIZE_ ## counter)	;\
 	ret					;\
 :						;\
 	jmp	1b				;\
 END(cpu_ ## counter ## _ ## fence)
 CPU_COUNTER_FENCE(counter, lfence)
 CPU_COUNTER_FENCE(counter, mfence)
 CPU_COUNTER_FENCE(counter32, lfence)
 CPU_COUNTER_FENCE(counter32, mfence)
 #define CPU_COUNTER_CPUID(counter)		\
 ENTRY(cpu_ ## counter ## _cpuid)		;\
 	movq	%rbx, %r9			;\
 	movq	CPUVAR(CURLWP), %r8		;\
 :						;\
 	movq	L_NCSW(%r8), %rdi		;\
 	xor	%eax, %eax			;\
 	cpuid					;\
 	rdtsc					;\
 	ADD_ ## counter				;\
 	cmpq	%rdi, L_NCSW(%r8)		;\
 	jne	2f				;\
 	movq	%r9, %rbx			;\
 	KMSAN_INIT_RET(RSIZE_ ## counter)	;\
 	ret					;\
 :						;\
 	jmp	1b				;\
 END(cpu_ ## counter ## _cpuid)
 CPU_COUNTER_CPUID(counter)
 CPU_COUNTER_CPUID(counter32)
 ENTRY(rdmsr_safe)
 	movq	CPUVAR(CURLWP), %r8
 	movq	L_PCB(%r8), %r8
 	movq	$_C_LABEL(msr_onfault), PCB_ONFAULT(%r8)
 	movl	%edi, %ecx
 	rdmsr
 	salq	$32, %rdx
 	movl	%eax, %eax	/* zero-extend %eax -> %rax */
 	orq	%rdx, %rax
 	movq	%rax, (%rsi)
 	xorq	%rax, %rax
 	movq	%rax, PCB_ONFAULT(%r8)
 #ifdef KMSAN
 	movq	%rsi,%rdi
 	movq	$8,%rsi
 	xorq	%rdx,%rdx
 	callq	_C_LABEL(kmsan_mark)
 #endif
 	KMSAN_INIT_RET(4)
 	ret
 END(rdmsr_safe)
 ENTRY(msr_onfault)
 	movq	CPUVAR(CURLWP), %r8
 	movq	L_PCB(%r8), %r8
 	movq	$0, PCB_ONFAULT(%r8)
 	movl	$EFAULT, %eax
 	ret
 END(msr_onfault)
 ENTRY(breakpoint)
 	pushq	%rbp
 	movq	%rsp, %rbp
 	int	$0x03		/* paranoid, not 'int3' */
 	leave
 	ret
 END(breakpoint)
 ENTRY(x86_curcpu)
 	movq	%gs:(CPU_INFO_SELF), %rax
 	KMSAN_INIT_RET(8)
 	ret
 END(x86_curcpu)
 ENTRY(x86_curlwp)
 	movq	%gs:(CPU_INFO_CURLWP), %rax
 	KMSAN_INIT_RET(8)
 	ret
 END(x86_curlwp)
 ENTRY(__byte_swap_u32_variable)
 	movl	%edi, %eax
 	bswapl	%eax
 	KMSAN_INIT_RET(4)
 	ret
 END(__byte_swap_u32_variable)
 ENTRY(__byte_swap_u16_variable)
 	movl	%edi, %eax
 	xchgb	%al, %ah
 	KMSAN_INIT_RET(2)
 	ret
 END(__byte_swap_u16_variable)
 /*
  * Reload segments after a GDT change.
  */
 ENTRY(lgdt_finish)
 	movl	$GSEL(GDATA_SEL, SEL_KPL),%eax
 	movl	%eax,%ds
 	movl	%eax,%es
 	movl	%eax,%ss
 	jmp	_C_LABEL(x86_flush)
 END(lgdt_finish)
 /*
  * Flush instruction pipelines by doing an intersegment (far) return.
  */
 ENTRY(x86_flush)
 	popq	%rax
 	pushq	$GSEL(GCODE_SEL, SEL_KPL)
 	pushq	%rax
 	lretq
 END(x86_flush)
 /* Waits - set up stack frame. */
 ENTRY(x86_hlt)
 	pushq	%rbp
 	movq	%rsp, %rbp
 	hlt
 	leave
 	ret
 END(x86_hlt)
 /* Waits - set up stack frame. */
 ENTRY(x86_stihlt)
 	pushq	%rbp
 	movq	%rsp, %rbp
 	sti
 	hlt
 	leave
 	ret
 END(x86_stihlt)
 ENTRY(x86_monitor)
 	movq	%rdi, %rax
 	movq	%rsi, %rcx
 	monitor	%rax, %rcx, %rdx
 	ret
 END(x86_monitor)
 /* Waits - set up stack frame. */
 ENTRY(x86_mwait)
 	pushq	%rbp
 	movq	%rsp, %rbp
 	movq	%rdi, %rax
 	movq	%rsi, %rcx
 	mwait	%rax, %rcx
 	leave
 	ret
 END(x86_mwait)
 ENTRY(stts)
 	movq	%cr0, %rax
 	orq	$CR0_TS, %rax
 	movq	%rax, %cr0
 	ret
 END(stts)
 ENTRY(fldummy)
 	ffree	%st(7)
 	fldz
 	ret
 END(fldummy)
 ENTRY(inb)
 	movq	%rdi, %rdx
 	xorq	%rax, %rax
 	inb	%dx, %al
 	KMSAN_INIT_RET(1)
 	ret
 END(inb)
 ENTRY(inw)
 	movq	%rdi, %rdx
 	xorq	%rax, %rax
 	inw	%dx, %ax
 	KMSAN_INIT_RET(2)
 	ret
 END(inw)
 ENTRY(inl)
 	movq	%rdi, %rdx
 	xorq	%rax, %rax
 	inl	%dx, %eax
 	KMSAN_INIT_RET(4)
 	ret
 END(inl)
 ENTRY(outb)
 	movq	%rdi, %rdx
 	movq	%rsi, %rax
 	outb	%al, %dx
 	ret
 END(outb)
 ENTRY(outw)
 	movq	%rdi, %rdx
 	movq	%rsi, %rax
 	outw	%ax, %dx
 	ret
 END(outw)
 ENTRY(outl)
 	movq	%rdi, %rdx
 	movq	%rsi, %rax
 	outl	%eax, %dx
 	ret
 END(outl)
 ENTRY(x86_stos)
 	movq	%rsi,%rax
 	movq	%rdx,%rcx
 	KMSAN_REP_STOS(8)
 	rep
 	stosq
 	ret
 END(x86_stos)
 ENTRY(x86_movs)
 	movq	%rdx,%rcx
 	KMSAN_REP_STOS(8)
 	rep
 	movsq
 	ret
 END(x86_movs)

 @@ -1,387 +1,371 @@
-/*	$NetBSD: cpufunc.S,v 1.47 2020/06/15 09:09:23 msaitoh Exp $	*/
+/*	$NetBSD: cpufunc.S,v 1.48 2020/06/24 18:09:37 maxv Exp $	*/
 /*-
  * Copyright (c) 1998, 2007, 2020 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum, and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Functions to provide access to i386-specific instructions.
+ *
  * These are shared with NetBSD/xen.
  */
 #include <sys/errno.h>
 #include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.S,v 1.47 2020/06/15 09:09:23 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.S,v 1.48 2020/06/24 18:09:37 maxv Exp $");
 #include "opt_xen.h"
 #include <machine/specialreg.h>
 #include <machine/segments.h>
 #include "assym.h"
 ENTRY(x86_lfence)
 	lock
 	addl	$0, -4(%esp)
 	ret
 END(x86_lfence)
 ENTRY(x86_sfence)
 	lock
 	addl	$0, -4(%esp)
 	ret
 END(x86_sfence)
 ENTRY(x86_mfence)
 	lock
 	addl	$0, -4(%esp)
 	ret
 END(x86_mfence)
 #ifndef XENPV
 ENTRY(lidt)
 	movl	4(%esp), %eax
 	lidt	(%eax)
 	ret
 END(lidt)
 ENTRY(x86_hotpatch)
 	/* save EFLAGS, and disable intrs */
 	pushfl
 	cli
 	/* save CR0, and disable WP */
 	movl	%cr0,%ecx
 	pushl	%ecx
 	andl	$~CR0_WP,%ecx
 	movl	%ecx,%cr0
 	pushl	4*4(%esp) /* arg2 */
 	pushl	4*4(%esp) /* arg1 */
 	call	_C_LABEL(x86_hotpatch_apply)
 	addl	$2*4,%esp
 	/* write back and invalidate cache */
 	wbinvd
 	/* restore CR0 */
 	popl	%ecx
 	movl	%ecx,%cr0
 	/* flush instruction pipeline */
 	pushl	%eax
 	call	x86_flush
 	popl	%eax
 	/* clean up */
 	pushl	%eax
 	call	_C_LABEL(x86_hotpatch_cleanup)
 	addl	$4,%esp
 	/* restore RFLAGS */
 	popfl
 	ret
 END(x86_hotpatch)
 #endif /* XENPV */
 ENTRY(x86_read_flags)
 	pushfl
 	popl	%eax
 	ret
 END(x86_read_flags)
 ENTRY(x86_write_flags)
 	movl	4(%esp), %eax
 	pushl	%eax
 	popfl
 	ret
 END(x86_write_flags)
 #ifndef XENPV
 STRONG_ALIAS(x86_write_psl,x86_write_flags)
 STRONG_ALIAS(x86_read_psl,x86_read_flags)
 #endif	/* XENPV */
 /*
  * Support for reading MSRs in the safe manner (returns EFAULT on fault)
  */
 /* int rdmsr_safe(u_int msr, uint64_t *data) */
 ENTRY(rdmsr_safe)
 	movl	CPUVAR(CURLWP), %ecx
 	movl	L_PCB(%ecx), %ecx
 	movl	$_C_LABEL(msr_onfault), PCB_ONFAULT(%ecx)
 	movl	4(%esp), %ecx /* u_int msr */
 	rdmsr
 	movl	8(%esp), %ecx /* *data */
 	movl	%eax, (%ecx)  /* low-order bits */
 	movl	%edx, 4(%ecx) /* high-order bits */
 	xorl	%eax, %eax    /* "no error" */
 	movl	CPUVAR(CURLWP), %ecx
 	movl	L_PCB(%ecx), %ecx
 	movl	%eax, PCB_ONFAULT(%ecx)
 	ret
 END(rdmsr_safe)
 /*
  * MSR operations fault handler
  */
 ENTRY(msr_onfault)
 	movl	CPUVAR(CURLWP), %ecx
 	movl	L_PCB(%ecx), %ecx
 	movl	$0, PCB_ONFAULT(%ecx)
 	movl	$EFAULT, %eax
 	ret
 END(msr_onfault)
 #define ADD_counter32	addl	CPUVAR(CC_SKEW), %eax
 #define ADD_counter	ADD_counter32			;\
 			adcl	CPUVAR(CC_SKEW+4), %edx
 #define SERIALIZE_lfence	lfence
 #define SERIALIZE_mfence	mfence
 #define CPU_COUNTER_FENCE(counter, fence) \
 ENTRY(cpu_ ## counter ## _ ## fence)	;\
 	pushl	%ebx			;\
 	movl	CPUVAR(CURLWP), %ecx	;\
 :					;\
 	movl	L_NCSW(%ecx), %ebx	;\
 	SERIALIZE_ ## fence		;\
 	rdtsc				;\
 	ADD_ ## counter			;\
 	cmpl	%ebx, L_NCSW(%ecx)	;\
 	jne	2f			;\
 	popl	%ebx			;\
 	ret				;\
 :					;\
 	jmp	1b			;\
 END(cpu_ ## counter ## _ ## fence)
 CPU_COUNTER_FENCE(counter, lfence)
 CPU_COUNTER_FENCE(counter, mfence)
 CPU_COUNTER_FENCE(counter32, lfence)
 CPU_COUNTER_FENCE(counter32, mfence)
 #define CPU_COUNTER_CPUID(counter)	\
 ENTRY(cpu_ ## counter ## _cpuid)	;\
 	pushl	%ebx			;\
 	pushl	%esi			;\
 	movl	CPUVAR(CURLWP), %ecx	;\
 :					;\
 	movl	L_NCSW(%ecx), %esi	;\
 	pushl	%ecx			;\
 	xor	%eax, %eax		;\
 	cpuid				;\
 	rdtsc				;\
 	ADD_ ## counter			;\
 	popl	%ecx			;\
 	cmpl	%esi, L_NCSW(%ecx)	;\
 	jne	2f			;\
 	popl	%esi			;\
 	popl	%ebx			;\
 	ret				;\
 :					;\
 	jmp	1b			;\
 END(cpu_ ## counter ##_cpuid)
 CPU_COUNTER_CPUID(counter)
 CPU_COUNTER_CPUID(counter32)
 ENTRY(breakpoint)
 	pushl	%ebp
 	movl	%esp, %ebp
 	int	$0x03		/* paranoid, not 'int3' */
 	popl	%ebp
 	ret
 END(breakpoint)
 ENTRY(x86_curcpu)
 	movl	%fs:(CPU_INFO_SELF), %eax
 	ret
 END(x86_curcpu)
 ENTRY(x86_curlwp)
 	movl	%fs:(CPU_INFO_CURLWP), %eax
 	ret
 END(x86_curlwp)
 ENTRY(__byte_swap_u32_variable)
 	movl	4(%esp), %eax
 	bswapl	%eax
 	ret
 END(__byte_swap_u32_variable)
 ENTRY(__byte_swap_u16_variable)
 	movl	4(%esp), %eax
 	xchgb	%al, %ah
 	ret
 END(__byte_swap_u16_variable)
 /*
  * void x86_flush()
+ *
  * Flush instruction pipelines by doing an intersegment (far) return.
  */
 ENTRY(x86_flush)
 	popl	%eax
 	pushl	$GSEL(GCODE_SEL, SEL_KPL)
 	pushl	%eax
 	lret
 END(x86_flush)
 /* Waits - set up stack frame. */
 ENTRY(x86_hlt)
 	pushl	%ebp
 	movl	%esp, %ebp
 	hlt
 	leave
 	ret
 END(x86_hlt)
 /* Waits - set up stack frame. */
 ENTRY(x86_stihlt)
 	pushl	%ebp
 	movl	%esp, %ebp
 	sti
 	hlt
 	leave
 	ret
 END(x86_stihlt)
 ENTRY(x86_monitor)
 	movl	4(%esp), %eax
 	movl	8(%esp), %ecx
 	movl	12(%esp), %edx
 	monitor	%eax, %ecx, %edx
 	ret
 END(x86_monitor)
 /* Waits - set up stack frame. */
 ENTRY(x86_mwait)
 	pushl	%ebp
 	movl	%esp, %ebp
 	movl	8(%ebp), %eax
 	movl	12(%ebp), %ecx
 	mwait	%eax, %ecx
 	leave
 	ret
 END(x86_mwait)
 ENTRY(stts)
 	movl	%cr0, %eax
 	testl	$CR0_TS, %eax
 	jnz	1f
 	orl	$CR0_TS, %eax
 	movl	%eax, %cr0
 :
 	ret
 END(stts)
 ENTRY(fldummy)
 	ffree	%st(7)
 	fldz
 	ret
 END(fldummy)
 ENTRY(inb)
 	movl	4(%esp), %edx
 	xorl	%eax, %eax
 	inb	%dx, %al
 	ret
 END(inb)
 ENTRY(inw)
 	movl	4(%esp), %edx
 	xorl	%eax, %eax
 	inw	%dx, %ax
 	ret
 END(inw)
 ENTRY(inl)
 	movl	4(%esp), %edx
 	inl	%dx, %eax
 	ret
 END(inl)
 ENTRY(outb)
 	movl	4(%esp), %edx
 	movl	8(%esp), %eax
 	outb	%al, %dx
 	ret
 END(outb)
 ENTRY(outw)
 	movl	4(%esp), %edx
 	movl	8(%esp), %eax
 	outw	%ax, %dx
 	ret
 END(outw)
 ENTRY(outl)
 	movl	4(%esp), %edx
 	movl	8(%esp), %eax
 	outl	%eax, %dx
 	ret
 END(outl)
 ENTRY(x86_stos)
 	pushl	%ebp
 	movl	%esp,%ebp
 	pushl	%edi
 	pushl	%esi
 	movl	8(%ebp),%edi
 	movl	12(%ebp),%eax
 	movl	16(%ebp),%ecx
 	rep
 	stosl
 	popl	%esi
 	popl	%edi
 	leave
 	ret
 END(x86_stos)
 ENTRY(x86_movs)
 	pushl	%ebp
 	movl	%esp,%ebp
 	pushl	%edi
 	pushl	%esi
 	movl	8(%ebp),%edi
 	movl	12(%ebp),%esi
 	movl	16(%ebp),%ecx
 	rep
 	movsl
 	popl	%esi
 	popl	%edi
 	leave
 	ret
 END(x86_movs)

 @@ -1,620 +1,619 @@
-/*	$NetBSD: pmap.h,v 1.122 2020/05/27 19:33:40 ad Exp $	*/
+/*	$NetBSD: pmap.h,v 1.123 2020/06/24 18:09:37 maxv Exp $	*/
 /*
  * Copyright (c) 1997 Charles D. Cranor and Washington University.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Frank van der Linden for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *      This product includes software developed for the NetBSD Project by
  *      Wasabi Systems, Inc.
  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  *    or promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * pmap.h: see pmap.c for the history of this pmap module.
  */
 #ifndef _X86_PMAP_H_
 #define	_X86_PMAP_H_
 /*
  * pl*_pi: index in the ptp page for a pde mapping a VA.
  * (pl*_i below is the index in the virtual array of all pdes per level)
  */
 #define pl1_pi(VA)	(((VA_SIGN_POS(VA)) & L1_MASK) >> L1_SHIFT)
 #define pl2_pi(VA)	(((VA_SIGN_POS(VA)) & L2_MASK) >> L2_SHIFT)
 #define pl3_pi(VA)	(((VA_SIGN_POS(VA)) & L3_MASK) >> L3_SHIFT)
 #define pl4_pi(VA)	(((VA_SIGN_POS(VA)) & L4_MASK) >> L4_SHIFT)
 #define pl_pi(va, lvl) \
         (((VA_SIGN_POS(va)) & ptp_masks[(lvl)-1]) >> ptp_shifts[(lvl)-1])
 /*
  * pl*_i: generate index into pde/pte arrays in virtual space
+ *
  * pl_i(va, X) == plX_i(va) <= pl_i_roundup(va, X)
  */
 #define pl1_i(VA)	(((VA_SIGN_POS(VA)) & L1_FRAME) >> L1_SHIFT)
 #define pl2_i(VA)	(((VA_SIGN_POS(VA)) & L2_FRAME) >> L2_SHIFT)
 #define pl3_i(VA)	(((VA_SIGN_POS(VA)) & L3_FRAME) >> L3_SHIFT)
 #define pl4_i(VA)	(((VA_SIGN_POS(VA)) & L4_FRAME) >> L4_SHIFT)
 #define pl_i(va, lvl) \
         (((VA_SIGN_POS(va)) & ptp_frames[(lvl)-1]) >> ptp_shifts[(lvl)-1])
 #define	pl_i_roundup(va, lvl)	pl_i((va)+ ~ptp_frames[(lvl)-1], (lvl))
 /*
  * PTP macros:
  *   a PTP's index is the PD index of the PDE that points to it
  *   a PTP's offset is the byte-offset in the PTE space that this PTP is at
  *   a PTP's VA is the first VA mapped by that PTP
  */
 #define ptp_va2o(va, lvl)	(pl_i(va, (lvl)+1) * PAGE_SIZE)
 /* size of a PDP: usually one page, except for PAE */
 #ifdef PAE
 #define PDP_SIZE 4
 #else
 #define PDP_SIZE 1
 #endif
 #if defined(_KERNEL)
 #include <sys/kcpuset.h>
 #include <sys/rwlock.h>
 #include <x86/pmap_pv.h>
 #include <uvm/pmap/pmap_pvt.h>
 #define	PATENTRY(n, type)	(type << ((n) * 8))
 #define	PAT_UC		0x0ULL
 #define	PAT_WC		0x1ULL
 #define	PAT_WT		0x4ULL
 #define	PAT_WP		0x5ULL
 #define	PAT_WB		0x6ULL
 #define	PAT_UCMINUS	0x7ULL
 #define BTSEG_NONE	0
 #define BTSEG_TEXT	1
 #define BTSEG_RODATA	2
 #define BTSEG_DATA	3
 #define BTSPACE_NSEGS	64
 struct bootspace {
 	struct {
 		vaddr_t va;
 		paddr_t pa;
 		size_t sz;
 	} head;
 	/* Kernel segments. */
 	struct {
 		int type;
 		vaddr_t va;
 		paddr_t pa;
 		size_t sz;
 	} segs[BTSPACE_NSEGS];
 	/*
 	 * The area used by the early kernel bootstrap. It contains the kernel
 	 * symbols, the preloaded modules, the bootstrap tables, and the ISA I/O
 	 * mem.
 	 */
 	struct {
 		vaddr_t va;
 		paddr_t pa;
 		size_t sz;
 	} boot;
 	/* A magic VA usable by the bootstrap code. */
 	vaddr_t spareva;
 	/* Virtual address of the page directory. */
 	vaddr_t pdir;
 	/* Area dedicated to kernel modules (amd64 only). */
 	vaddr_t smodule;
 	vaddr_t emodule;
 };
 #define SLAREA_USER	0
 #define SLAREA_PTE	1
 #define SLAREA_MAIN	2
 #define SLAREA_PCPU	3
 #define SLAREA_DMAP	4
 #define SLAREA_HYPV	5
 #define SLAREA_ASAN	6
 #define SLAREA_MSAN	7
 #define SLAREA_KERN	8
 #define SLSPACE_NAREAS	9
 struct slotspace {
 	struct {
 		size_t sslot; /* start slot */
 		size_t nslot; /* # of slots */
 		bool active;  /* area is active */
 	} area[SLSPACE_NAREAS];
 };
 extern struct slotspace slotspace;
 #ifndef MAXGDTSIZ
 #define MAXGDTSIZ 65536 /* XXX */
 #endif
 #ifndef MAX_USERLDT_SIZE
 #define MAX_USERLDT_SIZE PAGE_SIZE /* XXX */
 #endif
 struct pcpu_entry {
 	uint8_t gdt[MAXGDTSIZ];
 	uint8_t ldt[MAX_USERLDT_SIZE];
 	uint8_t tss[PAGE_SIZE];
 	uint8_t ist0[PAGE_SIZE];
 	uint8_t ist1[PAGE_SIZE];
 	uint8_t ist2[PAGE_SIZE];
 	uint8_t ist3[PAGE_SIZE];
 	uint8_t rsp0[2 * PAGE_SIZE];
 } __packed;
 struct pcpu_area {
 #ifdef SVS
 	uint8_t utls[PAGE_SIZE];
 #endif
 	uint8_t idt[PAGE_SIZE];
 	uint8_t ldt[PAGE_SIZE];
 	struct pcpu_entry ent[MAXCPUS];
 } __packed;
 extern struct pcpu_area *pcpuarea;
 #define PMAP_PCID_KERN	0
 #define PMAP_PCID_USER	1
 /*
  * pmap data structures: see pmap.c for details of locking.
  */
 /*
  * we maintain a list of all non-kernel pmaps
  */
 LIST_HEAD(pmap_head, pmap); /* struct pmap_head: head of a pmap list */
 /*
  * linked list of all non-kernel pmaps
  */
 extern struct pmap_head pmaps;
 extern kmutex_t pmaps_lock;    /* protects pmaps */
 /*
  * pool_cache(9) that pmaps are allocated from
  */
 extern struct pool_cache pmap_cache;
 /*
  * the pmap structure
+ *
  * note that the pm_obj contains the lock pointer, the reference count,
  * page list, and number of PTPs within the pmap.
+ *
  * pm_lock is the same as the lock for vm object 0.  Changes to
  * the other objects may only be made if that lock has been taken
  * (the other object locks are only used when uvm_pagealloc is called)
  */
 struct pv_page;
 struct pmap {
 	struct uvm_object pm_obj[PTP_LEVELS-1];/* objects for lvl >= 1) */
 	LIST_ENTRY(pmap) pm_list;	/* list of all pmaps */
 	pd_entry_t *pm_pdir;		/* VA of PD */
 	paddr_t pm_pdirpa[PDP_SIZE];	/* PA of PDs (read-only after create) */
 	struct vm_page *pm_ptphint[PTP_LEVELS-1];
 					/* pointer to a PTP in our pmap */
 	struct pmap_statistics pm_stats;  /* pmap stats */
 	struct pv_entry *pm_pve;	/* spare pv_entry */
 	LIST_HEAD(, pv_page) pm_pvp_part;
 	LIST_HEAD(, pv_page) pm_pvp_empty;
 	LIST_HEAD(, pv_page) pm_pvp_full;
 #if !defined(__x86_64__)
 	vaddr_t pm_hiexec;		/* highest executable mapping */
 #endif /* !defined(__x86_64__) */
 	union descriptor *pm_ldt;	/* user-set LDT */
 	size_t pm_ldt_len;		/* XXX unused, remove */
 	int pm_ldt_sel;			/* LDT selector */
 	kcpuset_t *pm_cpus;		/* mask of CPUs using pmap */
 	kcpuset_t *pm_kernel_cpus;	/* mask of CPUs using kernel part
 					 of pmap */
 	kcpuset_t *pm_xen_ptp_cpus;	/* mask of CPUs which have this pmap's
 					 ptp mapped */
 	uint64_t pm_ncsw;		/* for assertions */
 	LIST_HEAD(,vm_page) pm_gc_ptp;	/* PTPs queued for free */
 	/* Used by NVMM and Xen */
 	int (*pm_enter)(struct pmap *, vaddr_t, paddr_t, vm_prot_t, u_int);
 	bool (*pm_extract)(struct pmap *, vaddr_t, paddr_t *);
 	void (*pm_remove)(struct pmap *, vaddr_t, vaddr_t);
 	int (*pm_sync_pv)(struct vm_page *, vaddr_t, paddr_t, int, uint8_t *,
 	    pt_entry_t *);
 	void (*pm_pp_remove_ent)(struct pmap *, struct vm_page *, pt_entry_t,
 	    vaddr_t);
 	void (*pm_write_protect)(struct pmap *, vaddr_t, vaddr_t, vm_prot_t);
 	void (*pm_unwire)(struct pmap *, vaddr_t);
 	void (*pm_tlb_flush)(struct pmap *);
 	void *pm_data;
 	kmutex_t pm_lock		/* locks for pm_objs */
 	    __aligned(64);		/* give lock own cache line */
 	krwlock_t pm_dummy_lock;	/* ugly hack for abusing uvm_object */
 };
 /* macro to access pm_pdirpa slots */
 #ifdef PAE
 #define pmap_pdirpa(pmap, index) \
 	((pmap)->pm_pdirpa[l2tol3(index)] + l2tol2(index) * sizeof(pd_entry_t))
 #else
 #define pmap_pdirpa(pmap, index) \
 	((pmap)->pm_pdirpa[0] + (index) * sizeof(pd_entry_t))
 #endif
 /*
  * MD flags that we use for pmap_enter and pmap_kenter_pa:
  */
 /*
  * global kernel variables
  */
 /*
  * PDPpaddr is the physical address of the kernel's PDP.
  * - i386 non-PAE and amd64: PDPpaddr corresponds directly to the %cr3
  * value associated to the kernel process, proc0.
  * - i386 PAE: it still represents the PA of the kernel's PDP (L2). Due to
  * the L3 PD, it cannot be considered as the equivalent of a %cr3 any more.
  * - Xen: it corresponds to the PFN of the kernel's PDP.
  */
 extern u_long PDPpaddr;
 extern pd_entry_t pmap_pg_g;			/* do we support PTE_G? */
 extern pd_entry_t pmap_pg_nx;			/* do we support PTE_NX? */
 extern int pmap_largepages;
 extern long nkptp[PTP_LEVELS];
 /*
  * macros
  */
 #define	pmap_resident_count(pmap)	((pmap)->pm_stats.resident_count)
 #define	pmap_wired_count(pmap)		((pmap)->pm_stats.wired_count)
 #define pmap_clear_modify(pg)		pmap_clear_attrs(pg, PP_ATTRS_D)
 #define pmap_clear_reference(pg)	pmap_clear_attrs(pg, PP_ATTRS_A)
 #define pmap_copy(DP,SP,D,L,S)		__USE(L)
 #define pmap_is_modified(pg)		pmap_test_attrs(pg, PP_ATTRS_D)
 #define pmap_is_referenced(pg)		pmap_test_attrs(pg, PP_ATTRS_A)
 #define pmap_move(DP,SP,D,L,S)
 #define pmap_phys_address(ppn)		(x86_ptob(ppn) & ~X86_MMAP_FLAG_MASK)
 #define pmap_mmap_flags(ppn)		x86_mmap_flags(ppn)
 #define pmap_valid_entry(E) 		((E) & PTE_P) /* is PDE or PTE valid? */
 #if defined(__x86_64__) || defined(PAE)
 #define X86_MMAP_FLAG_SHIFT	(64 - PGSHIFT)
 #else
 #define X86_MMAP_FLAG_SHIFT	(32 - PGSHIFT)
 #endif
 #define X86_MMAP_FLAG_MASK	0xf
 #define X86_MMAP_FLAG_PREFETCH	0x1
 /*
  * prototypes
  */
 void		pmap_activate(struct lwp *);
 void		pmap_bootstrap(vaddr_t);
 bool		pmap_clear_attrs(struct vm_page *, unsigned);
 bool		pmap_pv_clear_attrs(paddr_t, unsigned);
 void		pmap_deactivate(struct lwp *);
 void		pmap_page_remove(struct vm_page *);
 void		pmap_pv_remove(paddr_t);
 void		pmap_remove(struct pmap *, vaddr_t, vaddr_t);
 bool		pmap_test_attrs(struct vm_page *, unsigned);
 void		pmap_write_protect(struct pmap *, vaddr_t, vaddr_t, vm_prot_t);
 void		pmap_load(void);
 paddr_t		pmap_init_tmp_pgtbl(paddr_t);
 bool		pmap_remove_all(struct pmap *);
 void		pmap_ldt_cleanup(struct lwp *);
 void		pmap_ldt_sync(struct pmap *);
 void		pmap_kremove_local(vaddr_t, vsize_t);
 #define	__HAVE_PMAP_PV_TRACK	1
 void		pmap_pv_init(void);
 void		pmap_pv_track(paddr_t, psize_t);
 void		pmap_pv_untrack(paddr_t, psize_t);
 void		pmap_map_ptes(struct pmap *, struct pmap **, pd_entry_t **,
 		    pd_entry_t * const **);
 void		pmap_unmap_ptes(struct pmap *, struct pmap *);
 bool		pmap_pdes_valid(vaddr_t, pd_entry_t * const *, pd_entry_t *,
 		    int *lastlvl);
 u_int		x86_mmap_flags(paddr_t);
 bool		pmap_is_curpmap(struct pmap *);
 void		pmap_ept_transform(struct pmap *);
 #ifndef __HAVE_DIRECT_MAP
 void		pmap_vpage_cpu_init(struct cpu_info *);
 #endif
 vaddr_t		slotspace_rand(int, size_t, size_t, size_t, vaddr_t);
 vaddr_t reserve_dumppages(vaddr_t); /* XXX: not a pmap fn */
 typedef enum tlbwhy {
 	TLBSHOOT_REMOVE_ALL,
 	TLBSHOOT_KENTER,
 	TLBSHOOT_KREMOVE,
 	TLBSHOOT_FREE_PTP,
 	TLBSHOOT_REMOVE_PTE,
 	TLBSHOOT_SYNC_PV,
 	TLBSHOOT_WRITE_PROTECT,
 	TLBSHOOT_ENTER,
 	TLBSHOOT_NVMM,
 	TLBSHOOT_BUS_DMA,
 	TLBSHOOT_BUS_SPACE,
 	TLBSHOOT__MAX,
 } tlbwhy_t;
 void		pmap_tlb_init(void);
 void		pmap_tlb_cpu_init(struct cpu_info *);
 void		pmap_tlb_shootdown(pmap_t, vaddr_t, pt_entry_t, tlbwhy_t);
 void		pmap_tlb_shootnow(void);
 void		pmap_tlb_intr(void);
 #define PMAP_GROWKERNEL		/* turn on pmap_growkernel interface */
 #define PMAP_FORK		/* turn on pmap_fork interface */
 /*
  * inline functions
  */
 /*
  * pmap_update_pg: flush one page from the TLB (or flush the whole thing
  *	if hardware doesn't support one-page flushing)
  */
 __inline static void __unused
 pmap_update_pg(vaddr_t va)
+{
 	invlpg(va);
+}
 /*
  * pmap_page_protect: change the protection of all recorded mappings
  *	of a managed page
+ *
  * => this function is a frontend for pmap_page_remove/pmap_clear_attrs
  * => we only have to worry about making the page more protected.
  *	unprotecting a page is done on-demand at fault time.
  */
 __inline static void __unused
 pmap_page_protect(struct vm_page *pg, vm_prot_t prot)
+{
 	if ((prot & VM_PROT_WRITE) == 0) {
 		if (prot & (VM_PROT_READ|VM_PROT_EXECUTE)) {
 			(void)pmap_clear_attrs(pg, PP_ATTRS_W);
 		} else {
 			pmap_page_remove(pg);
+		}
+	}
+}
 /*
  * pmap_pv_protect: change the protection of all recorded mappings
  *	of an unmanaged page
  */
 __inline static void __unused
 pmap_pv_protect(paddr_t pa, vm_prot_t prot)
+{
 	if ((prot & VM_PROT_WRITE) == 0) {
 		if (prot & (VM_PROT_READ|VM_PROT_EXECUTE)) {
 			(void)pmap_pv_clear_attrs(pa, PP_ATTRS_W);
 		} else {
 			pmap_pv_remove(pa);
+		}
+	}
+}
 /*
  * pmap_protect: change the protection of pages in a pmap
+ *
  * => this function is a frontend for pmap_remove/pmap_write_protect
  * => we only have to worry about making the page more protected.
  *	unprotecting a page is done on-demand at fault time.
  */
 __inline static void __unused
 pmap_protect(struct pmap *pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot)
+{
 	if ((prot & VM_PROT_WRITE) == 0) {
 		if (prot & (VM_PROT_READ|VM_PROT_EXECUTE)) {
 			pmap_write_protect(pmap, sva, eva, prot);
 		} else {
 			pmap_remove(pmap, sva, eva);
+		}
+	}
+}
 /*
  * various address inlines
+ *
  *  vtopte: return a pointer to the PTE mapping a VA, works only for
  *  user and PT addresses
+ *
  *  kvtopte: return a pointer to the PTE mapping a kernel VA
  */
 #include <lib/libkern/libkern.h>
 static __inline pt_entry_t * __unused
 vtopte(vaddr_t va)
+{
 	KASSERT(va < VM_MIN_KERNEL_ADDRESS);
 	return (PTE_BASE + pl1_i(va));
+}
 static __inline pt_entry_t * __unused
 kvtopte(vaddr_t va)
+{
 	pd_entry_t *pde;
 	KASSERT(va >= VM_MIN_KERNEL_ADDRESS);
 	pde = L2_BASE + pl2_i(va);
 	if (*pde & PTE_PS)
 		return ((pt_entry_t *)pde);
 	return (PTE_BASE + pl1_i(va));
+}
 paddr_t vtophys(vaddr_t);
 vaddr_t	pmap_map(vaddr_t, paddr_t, paddr_t, vm_prot_t);
 void	pmap_cpu_init_late(struct cpu_info *);
 #ifdef XENPV
 #include <sys/bitops.h>
 #define XPTE_MASK	L1_FRAME
 /* Selects the index of a PTE in (A)PTE_BASE */
 #define XPTE_SHIFT	(L1_SHIFT - ilog2(sizeof(pt_entry_t)))
 /* PTE access inline fuctions */
 /*
  * Get the machine address of the pointed pte
  * We use hardware MMU to get value so works only for levels 1-3
  */
 static __inline paddr_t
 xpmap_ptetomach(pt_entry_t *pte)
+{
 	pt_entry_t *up_pte;
 	vaddr_t va = (vaddr_t) pte;
 	va = ((va & XPTE_MASK) >> XPTE_SHIFT) | (vaddr_t) PTE_BASE;
 	up_pte = (pt_entry_t *) va;
 	return (paddr_t) (((*up_pte) & PTE_FRAME) + (((vaddr_t) pte) & (~PTE_FRAME & ~VA_SIGN_MASK)));
+}
 /* Xen helpers to change bits of a pte */
 #define XPMAP_UPDATE_DIRECT	1	/* Update direct map entry flags too */
 paddr_t	vtomach(vaddr_t);
 #define vtomfn(va) (vtomach(va) >> PAGE_SHIFT)
 #endif	/* XENPV */
 /* pmap functions with machine addresses */
 void	pmap_kenter_ma(vaddr_t, paddr_t, vm_prot_t, u_int);
 int	pmap_enter_ma(struct pmap *, vaddr_t, paddr_t, paddr_t,
 	    vm_prot_t, u_int, int);
 bool	pmap_extract_ma(pmap_t, vaddr_t, paddr_t *);
 paddr_t pmap_get_physpage(void);
 /*
  * Hooks for the pool allocator.
  */
 #define	POOL_VTOPHYS(va)	vtophys((vaddr_t) (va))
 #ifdef __HAVE_PCPU_AREA
 extern struct pcpu_area *pcpuarea;
 #define PDIR_SLOT_PCPU		510
 #define PMAP_PCPU_BASE		(VA_SIGN_NEG((PDIR_SLOT_PCPU * NBPD_L4)))
 #endif
 #ifdef __HAVE_DIRECT_MAP
 extern vaddr_t pmap_direct_base;
 extern vaddr_t pmap_direct_end;
 #define PMAP_DIRECT_BASE	pmap_direct_base
 #define PMAP_DIRECT_END		pmap_direct_end
 #define PMAP_DIRECT_MAP(pa)	((vaddr_t)PMAP_DIRECT_BASE + (pa))
 #define PMAP_DIRECT_UNMAP(va)	((paddr_t)(va) - PMAP_DIRECT_BASE)
 /*
  * Alternate mapping hooks for pool pages.
  */
 #define PMAP_MAP_POOLPAGE(pa)	PMAP_DIRECT_MAP((pa))
 #define PMAP_UNMAP_POOLPAGE(va)	PMAP_DIRECT_UNMAP((va))
 #endif /* __HAVE_DIRECT_MAP */
 void	x86_stos(void *, long, long);
 void	x86_movs(void *, void *, long);
 #endif /* _KERNEL */
 #endif /* _X86_PMAP_H_ */