Thu Jun 25 06:45:10 2020 UTC ()

 Use unsigned to avoid undefined behavior in ixgbe_fc_enable_generic().
Same as ixgbe_common.c rev. 1.24. Found by KUBSan.


(msaitoh)

diff -r1.14 -r1.15 src/sys/dev/pci/ixgbe/ixgbe_82598.c

--- src/sys/dev/pci/ixgbe/ixgbe_82598.c 2020/01/03 12:59:46	1.14
+++ src/sys/dev/pci/ixgbe/ixgbe_82598.c 2020/06/25 06:45:10	1.15

 @@ -1,14 +1,14 @@
-/* $NetBSD: ixgbe_82598.c,v 1.14 2020/01/03 12:59:46 pgoyette Exp $ */
+/* $NetBSD: ixgbe_82598.c,v 1.15 2020/06/25 06:45:10 msaitoh Exp $ */
 /******************************************************************************
   SPDX-License-Identifier: BSD-3-Clause
   Copyright (c) 2001-2017, Intel Corporation
   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
 . Redistributions of source code must retain the above copyright notice,
       this list of conditions and the following disclaimer.
 @@ -528,27 +528,27 @@ s32 ixgbe_fc_enable_82598(struct ixgbe_h
 		    hw->fc.high_water[i]) {
 			fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
 			fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
 			IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
 		} else {
 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
 			IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
+		}
+	}
 	/* Configure pause time (2 TCs per register) */
-	reg = hw->fc.pause_time * 0x00010001;
+	reg = (u32)hw->fc.pause_time * 0x00010001;
 	for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
 		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
 	/* Configure flow control refresh threshold value */
 	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
 out:
 	return ret_val;
+}
 /**
  *  ixgbe_start_mac_link_82598 - Configures MAC link settings
  *  @hw: pointer to hardware structure