Mon Jul 6 08:13:00 2020 UTC ()
XXX
Skip KASSERT which fires when !__HAVE_FAST_SOFTINTS. Just for debug.


(rin)
diff -r1.41 -r1.42 src/sys/arch/powerpc/booke/e500_intr.c
cvs diff -r1.41 -r1.42 src/sys/arch/powerpc/booke/e500_intr.c (expand / switch to unified diff)

--- src/sys/arch/powerpc/booke/e500_intr.c 2020/07/04 17:20:45 1.41
+++ src/sys/arch/powerpc/booke/e500_intr.c 2020/07/06 08:13:00 1.42
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: e500_intr.c,v 1.41 2020/07/04 17:20:45 rin Exp $ */ 1/* $NetBSD: e500_intr.c,v 1.42 2020/07/06 08:13:00 rin Exp $ */
2/*- 2/*-
3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry.
9 * 9 *
10 * This material is based upon work supported by the Defense Advanced Research 10 * This material is based upon work supported by the Defense Advanced Research
11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
12 * Contract No. N66001-09-C-2073. 12 * Contract No. N66001-09-C-2073.
13 * Approved for Public Release, Distribution Unlimited 13 * Approved for Public Release, Distribution Unlimited
14 * 14 *
@@ -31,27 +31,27 @@ @@ -31,27 +31,27 @@
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE. 34 * POSSIBILITY OF SUCH DAMAGE.
35 */ 35 */
36 36
37#include "opt_mpc85xx.h" 37#include "opt_mpc85xx.h"
38#include "opt_multiprocessor.h" 38#include "opt_multiprocessor.h"
39#include "opt_ddb.h" 39#include "opt_ddb.h"
40 40
41#define __INTR_PRIVATE 41#define __INTR_PRIVATE
42 42
43#include <sys/cdefs.h> 43#include <sys/cdefs.h>
44__KERNEL_RCSID(0, "$NetBSD: e500_intr.c,v 1.41 2020/07/04 17:20:45 rin Exp $"); 44__KERNEL_RCSID(0, "$NetBSD: e500_intr.c,v 1.42 2020/07/06 08:13:00 rin Exp $");
45 45
46#include <sys/param.h> 46#include <sys/param.h>
47#include <sys/proc.h> 47#include <sys/proc.h>
48#include <sys/intr.h> 48#include <sys/intr.h>
49#include <sys/cpu.h> 49#include <sys/cpu.h>
50#include <sys/kmem.h> 50#include <sys/kmem.h>
51#include <sys/atomic.h> 51#include <sys/atomic.h>
52#include <sys/bus.h> 52#include <sys/bus.h>
53#include <sys/xcall.h> 53#include <sys/xcall.h>
54#include <sys/ipi.h> 54#include <sys/ipi.h>
55#include <sys/bitops.h> 55#include <sys/bitops.h>
56#include <sys/interrupt.h> 56#include <sys/interrupt.h>
57 57
@@ -500,27 +500,29 @@ e500_intr_onchip_name_lookup(int irq) @@ -500,27 +500,29 @@ e500_intr_onchip_name_lookup(int irq)
500 500
501 name = e500_intr_name_lookup(e500_intr_info.ii_onchip_intr_names, irq); 501 name = e500_intr_name_lookup(e500_intr_info.ii_onchip_intr_names, irq);
502 if (name == NULL) 502 if (name == NULL)
503 name = e500_intr_name_lookup(e500_onchip_intr_names, irq); 503 name = e500_intr_name_lookup(e500_onchip_intr_names, irq);
504 504
505 return name; 505 return name;
506} 506}
507 507
508static inline void 508static inline void
509e500_splset(struct cpu_info *ci, int ipl) 509e500_splset(struct cpu_info *ci, int ipl)
510{ 510{
511 struct cpu_softc * const cpu = ci->ci_softc; 511 struct cpu_softc * const cpu = ci->ci_softc;
512 512
 513#ifdef __HAVE_FAST_SOFTINTS /* XXX */
513 KASSERT((curlwp->l_pflag & LP_INTR) == 0 || ipl != IPL_NONE); 514 KASSERT((curlwp->l_pflag & LP_INTR) == 0 || ipl != IPL_NONE);
 515#endif
514 const u_int ctpr = IPL2CTPR(ipl); 516 const u_int ctpr = IPL2CTPR(ipl);
515 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == IPL2CTPR(ci->ci_cpl)); 517 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == IPL2CTPR(ci->ci_cpl));
516 openpic_write(cpu, OPENPIC_CTPR, ctpr); 518 openpic_write(cpu, OPENPIC_CTPR, ctpr);
517 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == ctpr); 519 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == ctpr);
518#ifdef DIAGNOSTIC 520#ifdef DIAGNOSTIC
519 cpu->cpu_spl_tb[ipl][ci->ci_cpl] = mftb(); 521 cpu->cpu_spl_tb[ipl][ci->ci_cpl] = mftb();
520#endif 522#endif
521 ci->ci_cpl = ipl; 523 ci->ci_cpl = ipl;
522} 524}
523 525
524static void 526static void
525e500_spl0(void) 527e500_spl0(void)
526{ 528{