Mon Jul 6 10:54:56 2020 UTC ()
Include missing opt_multiprocessor.h.


(rin)
diff -r1.20 -r1.21 src/sys/arch/powerpc/include/booke/cpuvar.h
diff -r1.16 -r1.17 src/sys/arch/powerpc/pic/pic_openpic.c
cvs diff -r1.20 -r1.21 src/sys/arch/powerpc/include/booke/cpuvar.h (switch to unified diff)

--- src/sys/arch/powerpc/include/booke/cpuvar.h 2019/04/07 05:25:55 1.20
+++ src/sys/arch/powerpc/include/booke/cpuvar.h 2020/07/06 10:54:56 1.21
@@ -1,208 +1,212 @@ @@ -1,208 +1,212 @@
1/* $NetBSD: cpuvar.h,v 1.20 2019/04/07 05:25:55 thorpej Exp $ */ 1/* $NetBSD: cpuvar.h,v 1.21 2020/07/06 10:54:56 rin Exp $ */
2/*- 2/*-
3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry.
9 * 9 *
10 * This material is based upon work supported by the Defense Advanced Research 10 * This material is based upon work supported by the Defense Advanced Research
11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
12 * Contract No. N66001-09-C-2073. 12 * Contract No. N66001-09-C-2073.
13 * Approved for Public Release, Distribution Unlimited 13 * Approved for Public Release, Distribution Unlimited
14 * 14 *
15 * Redistribution and use in source and binary forms, with or without 15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions 16 * modification, are permitted provided that the following conditions
17 * are met: 17 * are met:
18 * 1. Redistributions of source code must retain the above copyright 18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer. 19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright 20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the 21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution. 22 * documentation and/or other materials provided with the distribution.
23 * 23 *
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE. 34 * POSSIBILITY OF SUCH DAMAGE.
35 */ 35 */
36 36
37#ifndef _POWERPC_BOOKE_CPUVAR_H_ 37#ifndef _POWERPC_BOOKE_CPUVAR_H_
38#define _POWERPC_BOOKE_CPUVAR_H_ 38#define _POWERPC_BOOKE_CPUVAR_H_
39 39
 40#ifdef _KERNEL_OPT
 41#include "opt_multiprocessor.h"
 42#endif
 43
40#include <sys/bus.h> 44#include <sys/bus.h>
41#include <prop/proplib.h> 45#include <prop/proplib.h>
42#include <powerpc/psl.h> 46#include <powerpc/psl.h>
43 47
44struct cpunode_softc { 48struct cpunode_softc {
45 device_t sc_dev; 49 device_t sc_dev;
46 u_int sc_children; 50 u_int sc_children;
47}; 51};
48 52
49struct cpu_softc { 53struct cpu_softc {
50 struct cpu_info *cpu_ci; 54 struct cpu_info *cpu_ci;
51 struct evcnt *cpu_evcnt_intrs; 55 struct evcnt *cpu_evcnt_intrs;
52 bus_space_tag_t cpu_bst; 56 bus_space_tag_t cpu_bst;
53 bus_space_tag_t cpu_le_bst; 57 bus_space_tag_t cpu_le_bst;
54 bus_space_handle_t cpu_bsh; 58 bus_space_handle_t cpu_bsh;
55 bus_addr_t cpu_clock_gtbcr; 59 bus_addr_t cpu_clock_gtbcr;
56 60
57 paddr_t cpu_highmem; 61 paddr_t cpu_highmem;
58 62
59 u_int cpu_pcpls[5]; 63 u_int cpu_pcpls[5];
60 struct evcnt cpu_evcnt_spurious_intr; 64 struct evcnt cpu_evcnt_spurious_intr;
61 65
62 struct evcnt cpu_ev_late_clock; 66 struct evcnt cpu_ev_late_clock;
63 u_long cpu_ticks_per_clock_intr; 67 u_long cpu_ticks_per_clock_intr;
64 struct evcnt cpu_ev_exec_trap_sync; 68 struct evcnt cpu_ev_exec_trap_sync;
65 69
66 uint64_t cpu_spl_tb[NIPL][NIPL]; 70 uint64_t cpu_spl_tb[NIPL][NIPL];
67}; 71};
68 72
69struct cpunode_locators { 73struct cpunode_locators {
70 const char *cnl_name; 74 const char *cnl_name;
71 bus_addr_t cnl_addr; 75 bus_addr_t cnl_addr;
72 bus_size_t cnl_size; 76 bus_size_t cnl_size;
73 uint8_t cnl_instance; 77 uint8_t cnl_instance;
74 uint8_t cnl_nintr; 78 uint8_t cnl_nintr;
75 uint8_t cnl_intrs[4]; 79 uint8_t cnl_intrs[4];
76 uint32_t cnl_flags; 80 uint32_t cnl_flags;
77 uint16_t cnl_ids[6]; 81 uint16_t cnl_ids[6];
78}; 82};
79 83
80struct cpunode_attach_args { 84struct cpunode_attach_args {
81 const char *cna_busname; 85 const char *cna_busname;
82 bus_space_tag_t cna_memt; 86 bus_space_tag_t cna_memt;
83 bus_space_tag_t cna_le_memt; 87 bus_space_tag_t cna_le_memt;
84 bus_dma_tag_t cna_dmat; 88 bus_dma_tag_t cna_dmat;
85 struct cpunode_locators cna_locs; 89 struct cpunode_locators cna_locs;
86 u_int cna_childmask; 90 u_int cna_childmask;
87}; 91};
88 92
89struct mainbus_attach_args { 93struct mainbus_attach_args {
90 const char *ma_name; 94 const char *ma_name;
91 bus_space_tag_t ma_memt; 95 bus_space_tag_t ma_memt;
92 bus_space_tag_t ma_le_memt; 96 bus_space_tag_t ma_le_memt;
93 bus_dma_tag_t ma_dmat; 97 bus_dma_tag_t ma_dmat;
94 int ma_node; 98 int ma_node;
95}; 99};
96 100
97struct generic_attach_args { 101struct generic_attach_args {
98 const char *ga_name; 102 const char *ga_name;
99 bus_space_tag_t ga_bst; 103 bus_space_tag_t ga_bst;
100 bus_dma_tag_t ga_dmat; 104 bus_dma_tag_t ga_dmat;
101 bus_addr_t ga_addr; 105 bus_addr_t ga_addr;
102 bus_size_t ga_size; 106 bus_size_t ga_size;
103 int ga_cs; 107 int ga_cs;
104 int ga_irq; 108 int ga_irq;
105}; 109};
106 110
107#ifndef __BSD_PT_ENTRY_T 111#ifndef __BSD_PT_ENTRY_T
108#define __BSD_PT_ENTRY_T __uint32_t 112#define __BSD_PT_ENTRY_T __uint32_t
109typedef __BSD_PT_ENTRY_T pt_entry_t; 113typedef __BSD_PT_ENTRY_T pt_entry_t;
110#define PRIxPTE PRIx32 114#define PRIxPTE PRIx32
111#endif 115#endif
112 116
113#include <uvm/pmap/tlb.h> 117#include <uvm/pmap/tlb.h>
114 118
115struct tlb_md_io_ops { 119struct tlb_md_io_ops {
116 /* 120 /*
117 * We need mapiodev to be first so we can easily override it in 121 * We need mapiodev to be first so we can easily override it in
118 * early boot by doing cpu_md_ops.tlb_md_ops = (const struct 122 * early boot by doing cpu_md_ops.tlb_md_ops = (const struct
119 * tlb_md_ops *) &<variable containing mapiodev pointer>. 123 * tlb_md_ops *) &<variable containing mapiodev pointer>.
120 */ 124 */
121 void *(*md_tlb_mapiodev)(paddr_t, psize_t, bool); 125 void *(*md_tlb_mapiodev)(paddr_t, psize_t, bool);
122 void (*md_tlb_unmapiodev)(vaddr_t, vsize_t); 126 void (*md_tlb_unmapiodev)(vaddr_t, vsize_t);
123 int (*md_tlb_ioreserve)(vaddr_t, vsize_t, uint32_t); 127 int (*md_tlb_ioreserve)(vaddr_t, vsize_t, uint32_t);
124 int (*md_tlb_iorelease)(vaddr_t); 128 int (*md_tlb_iorelease)(vaddr_t);
125}; 129};
126 130
127struct cpu_md_ops { 131struct cpu_md_ops {
128 const struct cpunode_locators *md_cpunode_locs; 132 const struct cpunode_locators *md_cpunode_locs;
129 void (*md_cpu_attach)(device_t, u_int); 133 void (*md_cpu_attach)(device_t, u_int);
130 134
131 void (*md_device_register)(device_t, void *); 135 void (*md_device_register)(device_t, void *);
132 void (*md_cpu_startup)(void); 136 void (*md_cpu_startup)(void);
133 void (*md_cpu_reset)(void); 137 void (*md_cpu_reset)(void);
134 void (*md_cpunode_attach)(device_t, device_t, void *); 138 void (*md_cpunode_attach)(device_t, device_t, void *);
135 139
136 const struct tlb_md_ops *md_tlb_ops; 140 const struct tlb_md_ops *md_tlb_ops;
137 const struct tlb_md_io_ops *md_tlb_io_ops; 141 const struct tlb_md_io_ops *md_tlb_io_ops;
138}; 142};
139 143
140 144
141#ifdef _KERNEL 145#ifdef _KERNEL
142 146
143static __inline register_t 147static __inline register_t
144wrtee(register_t msr) 148wrtee(register_t msr)
145{ 149{
146 register_t old_msr; 150 register_t old_msr;
147 __asm("mfmsr\t%0" : "=r"(old_msr)); 151 __asm("mfmsr\t%0" : "=r"(old_msr));
148 152
149 if (__builtin_constant_p(msr)) { 153 if (__builtin_constant_p(msr)) {
150 __asm __volatile("wrteei\t%0" :: "n"((msr & PSL_EE) ? 1 : 0)); 154 __asm __volatile("wrteei\t%0" :: "n"((msr & PSL_EE) ? 1 : 0));
151 } else { 155 } else {
152 __asm __volatile("wrtee\t%0" :: "r"(msr)); 156 __asm __volatile("wrtee\t%0" :: "r"(msr));
153 } 157 }
154 return old_msr; 158 return old_msr;
155} 159}
156 160
157struct trapframe; 161struct trapframe;
158void booke_sstep(struct trapframe *); 162void booke_sstep(struct trapframe *);
159 163
160void booke_cpu_startup(const char *); /* model name */ 164void booke_cpu_startup(const char *); /* model name */
161extern struct powerpc_bus_dma_tag booke_bus_dma_tag; 165extern struct powerpc_bus_dma_tag booke_bus_dma_tag;
162 166
163extern struct cpu_info cpu_info[]; 167extern struct cpu_info cpu_info[];
164#ifdef MULTIPROCESSOR 168#ifdef MULTIPROCESSOR
165extern volatile struct cpu_hatch_data cpu_hatch_data; 169extern volatile struct cpu_hatch_data cpu_hatch_data;
166#endif 170#endif
167 171
168void cpu_evcnt_attach(struct cpu_info *); 172void cpu_evcnt_attach(struct cpu_info *);
169uint32_t cpu_read_4(bus_size_t); 173uint32_t cpu_read_4(bus_size_t);
170uint8_t cpu_read_1(bus_size_t); 174uint8_t cpu_read_1(bus_size_t);
171void cpu_write_4(bus_size_t, uint32_t); 175void cpu_write_4(bus_size_t, uint32_t);
172void cpu_write_1(bus_size_t, uint8_t); 176void cpu_write_1(bus_size_t, uint8_t);
173 177
174void dump_splhist(struct cpu_info *, void (*)(const char *, ...)); 178void dump_splhist(struct cpu_info *, void (*)(const char *, ...));
175void calc_delayconst(void); 179void calc_delayconst(void);
176 180
177struct intrsw; 181struct intrsw;
178void exception_init(const struct intrsw *); 182void exception_init(const struct intrsw *);
179 183
180void *tlb_mapiodev(paddr_t, psize_t, bool); 184void *tlb_mapiodev(paddr_t, psize_t, bool);
181void tlb_unmapiodev(vaddr_t, vsize_t); 185void tlb_unmapiodev(vaddr_t, vsize_t);
182int tlb_ioreserve(vaddr_t, vsize_t, pt_entry_t); 186int tlb_ioreserve(vaddr_t, vsize_t, pt_entry_t);
183int tlb_iorelease(vaddr_t); 187int tlb_iorelease(vaddr_t);
184 188
185extern struct cpu_md_ops cpu_md_ops; 189extern struct cpu_md_ops cpu_md_ops;
186 190
187void board_info_init(void); 191void board_info_init(void);
188void board_info_add_number(const char *, uint64_t); 192void board_info_add_number(const char *, uint64_t);
189void board_info_add_data(const char *, const void *, size_t); 193void board_info_add_data(const char *, const void *, size_t);
190void board_info_add_string(const char *, const char *); 194void board_info_add_string(const char *, const char *);
191void board_info_add_bool(const char *); 195void board_info_add_bool(const char *);
192void board_info_add_object(const char *, void *); 196void board_info_add_object(const char *, void *);
193uint64_t board_info_get_number(const char *); 197uint64_t board_info_get_number(const char *);
194bool board_info_get_bool(const char *); 198bool board_info_get_bool(const char *);
195void *board_info_get_object(const char *); 199void *board_info_get_object(const char *);
196const void * 200const void *
197 board_info_get_data(const char *, size_t *); 201 board_info_get_data(const char *, size_t *);
198 202
199/* trap.c */ 203/* trap.c */
200void dump_trapframe(const struct trapframe *, void (*)(const char *, ...)); 204void dump_trapframe(const struct trapframe *, void (*)(const char *, ...));
201 205
202extern char root_string[]; 206extern char root_string[];
203extern paddr_t msgbuf_paddr; 207extern paddr_t msgbuf_paddr;
204extern prop_dictionary_t board_properties; 208extern prop_dictionary_t board_properties;
205extern psize_t pmemsize; 209extern psize_t pmemsize;
206#endif 210#endif
207 211
208#endif /* !_POWERPC_BOOKE_CPUVAR_H_ */ 212#endif /* !_POWERPC_BOOKE_CPUVAR_H_ */
cvs diff -r1.16 -r1.17 src/sys/arch/powerpc/pic/pic_openpic.c (switch to unified diff)

--- src/sys/arch/powerpc/pic/pic_openpic.c 2020/07/06 09:34:18 1.16
+++ src/sys/arch/powerpc/pic/pic_openpic.c 2020/07/06 10:54:56 1.17
@@ -1,192 +1,196 @@ @@ -1,192 +1,196 @@
1/* $NetBSD: pic_openpic.c,v 1.16 2020/07/06 09:34:18 rin Exp $ */ 1/* $NetBSD: pic_openpic.c,v 1.17 2020/07/06 10:54:56 rin Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2007 Michael Lorenz 4 * Copyright (c) 2007 Michael Lorenz
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
15 * 15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE. 26 * POSSIBILITY OF SUCH DAMAGE.
27 */ 27 */
28 28
29#include <sys/cdefs.h> 29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: pic_openpic.c,v 1.16 2020/07/06 09:34:18 rin Exp $"); 30__KERNEL_RCSID(0, "$NetBSD: pic_openpic.c,v 1.17 2020/07/06 10:54:56 rin Exp $");
31 31
32#ifdef _KERNEL_OPT 32#ifdef _KERNEL_OPT
33#include "opt_interrupt.h" 33#include "opt_interrupt.h"
34#endif 34#endif
35 35
 36#ifdef _KERNEL_OPT
 37#include "opt_multiprocessor.h"
 38#endif
 39
36#include <sys/param.h> 40#include <sys/param.h>
37#include <sys/kmem.h> 41#include <sys/kmem.h>
38#include <sys/kernel.h> 42#include <sys/kernel.h>
39 43
40#include <uvm/uvm_extern.h> 44#include <uvm/uvm_extern.h>
41 45
42#include <machine/pio.h> 46#include <machine/pio.h>
43#include <powerpc/openpic.h> 47#include <powerpc/openpic.h>
44 48
45#include <powerpc/pic/picvar.h> 49#include <powerpc/pic/picvar.h>
46 50
47static void opic_enable_irq(struct pic_ops *, int, int); 51static void opic_enable_irq(struct pic_ops *, int, int);
48static void opic_disable_irq(struct pic_ops *, int); 52static void opic_disable_irq(struct pic_ops *, int);
49static void opic_establish_irq(struct pic_ops*, int, int, int); 53static void opic_establish_irq(struct pic_ops*, int, int, int);
50 54
51struct pic_ops * 55struct pic_ops *
52setup_openpic(void *addr, int passthrough) 56setup_openpic(void *addr, int passthrough)
53{ 57{
54 struct openpic_ops *opicops; 58 struct openpic_ops *opicops;
55 struct pic_ops *pic; 59 struct pic_ops *pic;
56 int irq; 60 int irq;
57 u_int x; 61 u_int x;
58 62
59 openpic_base = addr; 63 openpic_base = addr;
60 opicops = kmem_alloc(sizeof(*opicops), KM_SLEEP); 64 opicops = kmem_alloc(sizeof(*opicops), KM_SLEEP);
61 pic = &opicops->pic; 65 pic = &opicops->pic;
62 66
63 x = openpic_read(OPENPIC_FEATURE); 67 x = openpic_read(OPENPIC_FEATURE);
64 if (((x & 0x07ff0000) >> 16) == 0) 68 if (((x & 0x07ff0000) >> 16) == 0)
65 panic("setup_openpic() called on distributed openpic"); 69 panic("setup_openpic() called on distributed openpic");
66  70
67 aprint_normal("OpenPIC Version 1.%d: " 71 aprint_normal("OpenPIC Version 1.%d: "
68 "Supports %d CPUs and %d interrupt sources.\n", 72 "Supports %d CPUs and %d interrupt sources.\n",
69 x & 0xff, ((x & 0x1f00) >> 8) + 1, ((x & 0x07ff0000) >> 16) + 1); 73 x & 0xff, ((x & 0x1f00) >> 8) + 1, ((x & 0x07ff0000) >> 16) + 1);
70 74
71 pic->pic_numintrs = IPI_VECTOR + 1; 75 pic->pic_numintrs = IPI_VECTOR + 1;
72 pic->pic_cookie = addr; 76 pic->pic_cookie = addr;
73 pic->pic_enable_irq = opic_enable_irq; 77 pic->pic_enable_irq = opic_enable_irq;
74 pic->pic_reenable_irq = opic_enable_irq; 78 pic->pic_reenable_irq = opic_enable_irq;
75 pic->pic_disable_irq = opic_disable_irq; 79 pic->pic_disable_irq = opic_disable_irq;
76 pic->pic_get_irq = opic_get_irq; 80 pic->pic_get_irq = opic_get_irq;
77 pic->pic_ack_irq = opic_ack_irq; 81 pic->pic_ack_irq = opic_ack_irq;
78 pic->pic_establish_irq = opic_establish_irq; 82 pic->pic_establish_irq = opic_establish_irq;
79 pic->pic_finish_setup = opic_finish_setup; 83 pic->pic_finish_setup = opic_finish_setup;
80 opicops->isu = NULL; 84 opicops->isu = NULL;
81 opicops->nrofisus = 0; /* internal only */ 85 opicops->nrofisus = 0; /* internal only */
82 opicops->flags = 0; /* no flags (yet) */ 86 opicops->flags = 0; /* no flags (yet) */
83 opicops->irq_per = NULL; /* internal ISU only */ 87 opicops->irq_per = NULL; /* internal ISU only */
84 strcpy(pic->pic_name, "openpic"); 88 strcpy(pic->pic_name, "openpic");
85 pic_add(pic); 89 pic_add(pic);
86 90
87 /* 91 /*
88 * the following sequence should make the same effects as openpic 92 * the following sequence should make the same effects as openpic
89 * controller reset by writing a one at the self-clearing 93 * controller reset by writing a one at the self-clearing
90 * OPENPIC_CONFIG_RESET bit. Please check the document of your 94 * OPENPIC_CONFIG_RESET bit. Please check the document of your
91 * OpenPIC compliant interrupt controller and see whether #else 95 * OpenPIC compliant interrupt controller and see whether #else
92 * portion can work as described. 96 * portion can work as described.
93 */ 97 */
94#if 1 98#if 1
95 openpic_set_priority(0, 15); 99 openpic_set_priority(0, 15);
96 100
97 for (irq = 0; irq < (pic->pic_numintrs - 1); irq++) { 101 for (irq = 0; irq < (pic->pic_numintrs - 1); irq++) {
98 /* make sure to keep disabled */ 102 /* make sure to keep disabled */
99 openpic_write(OPENPIC_SRC_VECTOR(irq), OPENPIC_IMASK); 103 openpic_write(OPENPIC_SRC_VECTOR(irq), OPENPIC_IMASK);
100 /* send all interrupts to CPU 0 */ 104 /* send all interrupts to CPU 0 */
101 openpic_write(OPENPIC_IDEST(irq), 1 << 0); 105 openpic_write(OPENPIC_IDEST(irq), 1 << 0);
102 } 106 }
103 107
104 x = openpic_read(OPENPIC_CONFIG); 108 x = openpic_read(OPENPIC_CONFIG);
105 if (passthrough) 109 if (passthrough)
106 x &= ~OPENPIC_CONFIG_8259_PASSTHRU_DISABLE; 110 x &= ~OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
107 else  111 else
108 x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE; 112 x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
109 openpic_write(OPENPIC_CONFIG, x); 113 openpic_write(OPENPIC_CONFIG, x);
110 114
111 openpic_write(OPENPIC_SPURIOUS_VECTOR, 0xff); 115 openpic_write(OPENPIC_SPURIOUS_VECTOR, 0xff);
112 116
113 openpic_set_priority(0, 0); 117 openpic_set_priority(0, 0);
114 118
115 /* clear all pending interrunts */ 119 /* clear all pending interrunts */
116 for (irq = 0; irq < pic->pic_numintrs; irq++) { 120 for (irq = 0; irq < pic->pic_numintrs; irq++) {
117 openpic_read_irq(0); 121 openpic_read_irq(0);
118 openpic_eoi(0); 122 openpic_eoi(0);
119 } 123 }
120#else 124#else
121 irq = 0; 125 irq = 0;
122 openpic_write(OPENPIC_CONFIG, OPENPIC_CONFIG_RESET); 126 openpic_write(OPENPIC_CONFIG, OPENPIC_CONFIG_RESET);
123 do { 127 do {
124 x = openpic_read(OPENPIC_CONFIG); 128 x = openpic_read(OPENPIC_CONFIG);
125 } while (x & OPENPIC_CONFIG_RESET); /* S1C bit */ 129 } while (x & OPENPIC_CONFIG_RESET); /* S1C bit */
126 if (passthrough) 130 if (passthrough)
127 x &= ~OPENPIC_CONFIG_8259_PASSTHRU_DISABLE; 131 x &= ~OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
128 else  132 else
129 x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE; 133 x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
130 openpic_write(OPENPIC_CONFIG, x); 134 openpic_write(OPENPIC_CONFIG, x);
131 openpic_set_priority(0, 0); 135 openpic_set_priority(0, 0);
132#endif 136#endif
133 137
134#if 0 138#if 0
135 printf("timebase freq=%d\n", openpic_read(0x10f0)); 139 printf("timebase freq=%d\n", openpic_read(0x10f0));
136#endif 140#endif
137 return pic; 141 return pic;
138} 142}
139 143
140static void 144static void
141opic_establish_irq(struct pic_ops *pic, int irq, int type, int pri) 145opic_establish_irq(struct pic_ops *pic, int irq, int type, int pri)
142{ 146{
143 int realpri = uimax(1, uimin(15, pri)); 147 int realpri = uimax(1, uimin(15, pri));
144 uint32_t x; 148 uint32_t x;
145 149
146 x = irq; 150 x = irq;
147 x |= OPENPIC_IMASK; 151 x |= OPENPIC_IMASK;
148 152
149 if (type == IST_EDGE_RISING || type == IST_LEVEL_HIGH) 153 if (type == IST_EDGE_RISING || type == IST_LEVEL_HIGH)
150 x |= OPENPIC_POLARITY_POSITIVE; 154 x |= OPENPIC_POLARITY_POSITIVE;
151 else 155 else
152 x |= OPENPIC_POLARITY_NEGATIVE; 156 x |= OPENPIC_POLARITY_NEGATIVE;
153 157
154 if (type == IST_EDGE_FALLING || type == IST_EDGE_RISING) 158 if (type == IST_EDGE_FALLING || type == IST_EDGE_RISING)
155 x |= OPENPIC_SENSE_EDGE; 159 x |= OPENPIC_SENSE_EDGE;
156 else 160 else
157 x |= OPENPIC_SENSE_LEVEL; 161 x |= OPENPIC_SENSE_LEVEL;
158 162
159 x |= realpri << OPENPIC_PRIORITY_SHIFT; 163 x |= realpri << OPENPIC_PRIORITY_SHIFT;
160#ifdef MULTIPROCESSOR 164#ifdef MULTIPROCESSOR
161 if (irq < IPI_VECTOR) 165 if (irq < IPI_VECTOR)
162#endif  166#endif
163 openpic_write(OPENPIC_SRC_VECTOR(irq), x); 167 openpic_write(OPENPIC_SRC_VECTOR(irq), x);
164 168
165 aprint_debug("%s: setting IRQ %d to priority %d\n", __func__, irq, 169 aprint_debug("%s: setting IRQ %d to priority %d\n", __func__, irq,
166 realpri); 170 realpri);
167} 171}
168 172
169static void 173static void
170opic_enable_irq(struct pic_ops *pic, int irq, int type) 174opic_enable_irq(struct pic_ops *pic, int irq, int type)
171{ 175{
172 u_int x; 176 u_int x;
173#ifdef MULTIPROCESSOR 177#ifdef MULTIPROCESSOR
174 if (irq == IPI_VECTOR) return; 178 if (irq == IPI_VECTOR) return;
175#endif 179#endif
176 x = openpic_read(OPENPIC_SRC_VECTOR(irq)); 180 x = openpic_read(OPENPIC_SRC_VECTOR(irq));
177 x &= ~OPENPIC_IMASK; 181 x &= ~OPENPIC_IMASK;
178 openpic_write(OPENPIC_SRC_VECTOR(irq), x); 182 openpic_write(OPENPIC_SRC_VECTOR(irq), x);
179} 183}
180 184
181static void 185static void
182opic_disable_irq(struct pic_ops *pic, int irq) 186opic_disable_irq(struct pic_ops *pic, int irq)
183{ 187{
184 u_int x; 188 u_int x;
185 189
186#ifdef MULTIPROCESSOR 190#ifdef MULTIPROCESSOR
187 if (irq == IPI_VECTOR) return; 191 if (irq == IPI_VECTOR) return;
188#endif 192#endif
189 x = openpic_read(OPENPIC_SRC_VECTOR(irq)); 193 x = openpic_read(OPENPIC_SRC_VECTOR(irq));
190 x |= OPENPIC_IMASK; 194 x |= OPENPIC_IMASK;
191 openpic_write(OPENPIC_SRC_VECTOR(irq), x); 195 openpic_write(OPENPIC_SRC_VECTOR(irq), x);
192} 196}