Tue Jul 7 00:28:31 2020 UTC ()
Fix kernel panic due to tmpfs.

pmap for booke assumes that the ``va'' argument for pmap_kenter_pa(9) is
page-aligned. However, by recent changes, tmpfs became to use ``va'' with
page offset via ubc_uiomove(9). So, truncate it to page boundary.


(rin)
diff -r1.21 -r1.22 src/sys/arch/powerpc/booke/e500_tlb.c
cvs diff -r1.21 -r1.22 src/sys/arch/powerpc/booke/e500_tlb.c (expand / switch to unified diff)

--- src/sys/arch/powerpc/booke/e500_tlb.c 2020/07/06 10:12:04 1.21
+++ src/sys/arch/powerpc/booke/e500_tlb.c 2020/07/07 00:28:30 1.22
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: e500_tlb.c,v 1.21 2020/07/06 10:12:04 rin Exp $ */ 1/* $NetBSD: e500_tlb.c,v 1.22 2020/07/07 00:28:30 rin Exp $ */
2/*- 2/*-
3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry.
9 * 9 *
10 * This material is based upon work supported by the Defense Advanced Research 10 * This material is based upon work supported by the Defense Advanced Research
11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
12 * Contract No. N66001-09-C-2073. 12 * Contract No. N66001-09-C-2073.
13 * Approved for Public Release, Distribution Unlimited 13 * Approved for Public Release, Distribution Unlimited
14 * 14 *
@@ -27,27 +27,27 @@ @@ -27,27 +27,27 @@
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE. 34 * POSSIBILITY OF SUCH DAMAGE.
35 */ 35 */
36 36
37#define __PMAP_PRIVATE 37#define __PMAP_PRIVATE
38 38
39#include <sys/cdefs.h> 39#include <sys/cdefs.h>
40__KERNEL_RCSID(0, "$NetBSD: e500_tlb.c,v 1.21 2020/07/06 10:12:04 rin Exp $"); 40__KERNEL_RCSID(0, "$NetBSD: e500_tlb.c,v 1.22 2020/07/07 00:28:30 rin Exp $");
41 41
42#ifdef _KERNEL_OPT 42#ifdef _KERNEL_OPT
43#include "opt_multiprocessor.h" 43#include "opt_multiprocessor.h"
44#include "opt_pmap.h" 44#include "opt_pmap.h"
45#include "opt_ppcparam.h" 45#include "opt_ppcparam.h"
46#endif 46#endif
47 47
48#include <sys/param.h> 48#include <sys/param.h>
49 49
50#include <uvm/uvm_extern.h> 50#include <uvm/uvm_extern.h>
51 51
52#include <powerpc/spr.h> 52#include <powerpc/spr.h>
53#include <powerpc/booke/spr.h> 53#include <powerpc/booke/spr.h>
@@ -526,26 +526,33 @@ e500_tlb_invalidate_addr(vaddr_t va, tlb @@ -526,26 +526,33 @@ e500_tlb_invalidate_addr(vaddr_t va, tlb
526 if (asid == KERNEL_PID) { 526 if (asid == KERNEL_PID) {
527 /* 527 /*
528 * The context-synchronizing instruction after tlbwe or tlbivax 528 * The context-synchronizing instruction after tlbwe or tlbivax
529 * ensures that subsequent accesses (data and instruction) use 529 * ensures that subsequent accesses (data and instruction) use
530 * the updated value in any TLB entries affected. 530 * the updated value in any TLB entries affected.
531 */ 531 */
532 __asm volatile("isync\n\tsync"); 532 __asm volatile("isync\n\tsync");
533 } 533 }
534} 534}
535 535
536static bool 536static bool
537e500_tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert) 537e500_tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert)
538{ 538{
 539
 540 /*
 541 * In case where pmap_kenter_pa(9) is called for va with page offset.
 542 * Required for tmpfs.
 543 */
 544 va &= ~PAGE_MASK;
 545
539#if defined(MULTIPROCESSOR) 546#if defined(MULTIPROCESSOR)
540 e500_tlb_invalidate_addr(va, asid); 547 e500_tlb_invalidate_addr(va, asid);
541 return true; 548 return true;
542#else /* !MULTIPROCESSOR */ 549#else /* !MULTIPROCESSOR */
543 struct e500_hwtlb hwtlb = tlb_to_hwtlb( 550 struct e500_hwtlb hwtlb = tlb_to_hwtlb(
544 (struct e500_tlb){ .tlb_va = va, .tlb_asid = asid, 551 (struct e500_tlb){ .tlb_va = va, .tlb_asid = asid,
545 .tlb_size = PAGE_SIZE, .tlb_pte = pte,}); 552 .tlb_size = PAGE_SIZE, .tlb_pte = pte,});
546 553
547 register_t msr = wrtee(0); 554 register_t msr = wrtee(0);
548 mtspr(SPR_MAS6, asid ? __SHIFTIN(asid, MAS6_SPID0) | MAS6_SAS : 0); 555 mtspr(SPR_MAS6, asid ? __SHIFTIN(asid, MAS6_SPID0) | MAS6_SAS : 0);
549 __asm volatile("tlbsx 0, %0" :: "b"(va)); 556 __asm volatile("tlbsx 0, %0" :: "b"(va));
550 register_t mas1 = mfspr(SPR_MAS1); 557 register_t mas1 = mfspr(SPR_MAS1);
551 if ((mas1 & MAS1_V) == 0) { 558 if ((mas1 & MAS1_V) == 0) {