| @@ -1,14 +1,14 @@ | | | @@ -1,14 +1,14 @@ |
1 | /* $NetBSD: fpu_emu.c,v 1.26 2020/07/15 07:52:58 rin Exp $ */ | | 1 | /* $NetBSD: fpu_emu.c,v 1.27 2020/07/15 07:54:25 rin Exp $ */ |
2 | | | 2 | |
3 | /* | | 3 | /* |
4 | * Copyright 2001 Wasabi Systems, Inc. | | 4 | * Copyright 2001 Wasabi Systems, Inc. |
5 | * All rights reserved. | | 5 | * All rights reserved. |
6 | * | | 6 | * |
7 | * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. | | 7 | * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. |
8 | * | | 8 | * |
9 | * Redistribution and use in source and binary forms, with or without | | 9 | * Redistribution and use in source and binary forms, with or without |
10 | * modification, are permitted provided that the following conditions | | 10 | * modification, are permitted provided that the following conditions |
11 | * are met: | | 11 | * are met: |
12 | * 1. Redistributions of source code must retain the above copyright | | 12 | * 1. Redistributions of source code must retain the above copyright |
13 | * notice, this list of conditions and the following disclaimer. | | 13 | * notice, this list of conditions and the following disclaimer. |
14 | * 2. Redistributions in binary form must reproduce the above copyright | | 14 | * 2. Redistributions in binary form must reproduce the above copyright |
| @@ -66,27 +66,27 @@ | | | @@ -66,27 +66,27 @@ |
66 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE | | 66 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
67 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | | 67 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
68 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | | 68 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
69 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | | 69 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
70 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | | 70 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
71 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | | 71 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
72 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | | 72 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
73 | * SUCH DAMAGE. | | 73 | * SUCH DAMAGE. |
74 | * | | 74 | * |
75 | * @(#)fpu.c 8.1 (Berkeley) 6/11/93 | | 75 | * @(#)fpu.c 8.1 (Berkeley) 6/11/93 |
76 | */ | | 76 | */ |
77 | | | 77 | |
78 | #include <sys/cdefs.h> | | 78 | #include <sys/cdefs.h> |
79 | __KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.26 2020/07/15 07:52:58 rin Exp $"); | | 79 | __KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.27 2020/07/15 07:54:25 rin Exp $"); |
80 | | | 80 | |
81 | #ifdef _KERNEL_OPT | | 81 | #ifdef _KERNEL_OPT |
82 | #include "opt_ddb.h" | | 82 | #include "opt_ddb.h" |
83 | #endif | | 83 | #endif |
84 | | | 84 | |
85 | #include <sys/param.h> | | 85 | #include <sys/param.h> |
86 | #include <sys/systm.h> | | 86 | #include <sys/systm.h> |
87 | #include <sys/evcnt.h> | | 87 | #include <sys/evcnt.h> |
88 | #include <sys/proc.h> | | 88 | #include <sys/proc.h> |
89 | #include <sys/siginfo.h> | | 89 | #include <sys/siginfo.h> |
90 | #include <sys/signal.h> | | 90 | #include <sys/signal.h> |
91 | #include <sys/signalvar.h> | | 91 | #include <sys/signalvar.h> |
92 | #include <sys/syslog.h> | | 92 | #include <sys/syslog.h> |
| @@ -214,27 +214,27 @@ fpu_emulate(struct trapframe *tf, struct | | | @@ -214,27 +214,27 @@ fpu_emulate(struct trapframe *tf, struct |
214 | return true; | | 214 | return true; |
215 | } | | 215 | } |
216 | | | 216 | |
217 | DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", | | 217 | DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", |
218 | insn.i_int, (void *)tf->tf_srr0)); | | 218 | insn.i_int, (void *)tf->tf_srr0)); |
219 | | | 219 | |
220 | if ((insn.i_any.i_opcd == OPC_TWI) || | | 220 | if ((insn.i_any.i_opcd == OPC_TWI) || |
221 | ((insn.i_any.i_opcd == OPC_integer_31) && | | 221 | ((insn.i_any.i_opcd == OPC_integer_31) && |
222 | (insn.i_x.i_xo == OPC31_TW))) { | | 222 | (insn.i_x.i_xo == OPC31_TW))) { |
223 | /* Check for the two trap insns. */ | | 223 | /* Check for the two trap insns. */ |
224 | DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); | | 224 | DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); |
225 | ksi->ksi_signo = SIGTRAP; | | 225 | ksi->ksi_signo = SIGTRAP; |
226 | ksi->ksi_trap = EXC_PGM; | | 226 | ksi->ksi_trap = EXC_PGM; |
227 | ksi->ksi_code = TRAP_TRACE; | | 227 | ksi->ksi_code = TRAP_BRKPT; |
228 | return true; | | 228 | return true; |
229 | } | | 229 | } |
230 | switch (fpu_execute(tf, &fe, &insn)) { | | 230 | switch (fpu_execute(tf, &fe, &insn)) { |
231 | case 0: | | 231 | case 0: |
232 | DPRINTF(FPE_EX, ("fpu_emulate: success\n")); | | 232 | DPRINTF(FPE_EX, ("fpu_emulate: success\n")); |
233 | tf->tf_srr0 += 4; | | 233 | tf->tf_srr0 += 4; |
234 | return true; | | 234 | return true; |
235 | | | 235 | |
236 | case FPE: | | 236 | case FPE: |
237 | DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); | | 237 | DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); |
238 | ksi->ksi_signo = SIGFPE; | | 238 | ksi->ksi_signo = SIGFPE; |
239 | ksi->ksi_trap = EXC_PGM; | | 239 | ksi->ksi_trap = EXC_PGM; |
240 | return true; | | 240 | return true; |