 @@ -1,2944 +1,2958 @@
-/*	$NetBSD: if_ixl.c,v 1.67 2020/06/11 02:39:30 thorpej Exp $	*/
+/*	$NetBSD: if_ixl.c,v 1.68 2020/07/16 01:20:38 yamaguchi Exp $	*/
 /*
  * Copyright (c) 2013-2015, Intel Corporation
  * All rights reserved.
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
+ *
  *  1. Redistributions of source code must retain the above copyright notice,
  *     this list of conditions and the following disclaimer.
+ *
  *  2. Redistributions in binary form must reproduce the above copyright
  *     notice, this list of conditions and the following disclaimer in the
  *     documentation and/or other materials provided with the distribution.
+ *
  *  3. Neither the name of the Intel Corporation nor the names of its
  *     contributors may be used to endorse or promote products derived from
  *     this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Copyright (c) 2016,2017 David Gwynne <dlg@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 /*
  * Copyright (c) 2019 Internet Initiative Japan, Inc.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_ixl.c,v 1.67 2020/06/11 02:39:30 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_ixl.c,v 1.68 2020/07/16 01:20:38 yamaguchi Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_net_mpsafe.h"
 #include "opt_if_ixl.h"
 #endif
 #include <sys/param.h>
 #include <sys/types.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/evcnt.h>
 #include <sys/interrupt.h>
 #include <sys/kmem.h>
 #include <sys/module.h>
 #include <sys/mutex.h>
 #include <sys/pcq.h>
 #include <sys/syslog.h>
 #include <sys/workqueue.h>
 #include <sys/bus.h>
 #include <net/bpf.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/if_ether.h>
 #include <net/rss_config.h>
 #include <netinet/tcp.h>	/* for struct tcphdr */
 #include <netinet/udp.h>	/* for struct udphdr */
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/if_ixlreg.h>
 #include <dev/pci/if_ixlvar.h>
 #include <prop/proplib.h>
 struct ixl_softc; /* defined */
 #define I40E_PF_RESET_WAIT_COUNT	200
 #define I40E_AQ_LARGE_BUF		512
 /* bitfields for Tx queue mapping in QTX_CTL */
 #define I40E_QTX_CTL_VF_QUEUE		0x0
 #define I40E_QTX_CTL_VM_QUEUE		0x1
 #define I40E_QTX_CTL_PF_QUEUE		0x2
 #define I40E_QUEUE_TYPE_EOL		0x7ff
 #define I40E_INTR_NOTX_QUEUE		0
 #define I40E_QUEUE_TYPE_RX		0x0
 #define I40E_QUEUE_TYPE_TX		0x1
 #define I40E_QUEUE_TYPE_PE_CEQ		0x2
 #define I40E_QUEUE_TYPE_UNKNOWN		0x3
 #define I40E_ITR_INDEX_RX		0x0
 #define I40E_ITR_INDEX_TX		0x1
 #define I40E_ITR_INDEX_OTHER		0x2
 #define I40E_ITR_INDEX_NONE		0x3
 #define IXL_ITR_RX			0x7a /* 4K intrs/sec */
 #define IXL_ITR_TX			0x7a /* 4K intrs/sec */
 #define I40E_INTR_NOTX_QUEUE		0
 #define I40E_INTR_NOTX_INTR		0
 #define I40E_INTR_NOTX_RX_QUEUE		0
 #define I40E_INTR_NOTX_TX_QUEUE		1
 #define I40E_INTR_NOTX_RX_MASK		I40E_PFINT_ICR0_QUEUE_0_MASK
 #define I40E_INTR_NOTX_TX_MASK		I40E_PFINT_ICR0_QUEUE_1_MASK
 #define BIT_ULL(a)	(1ULL << (a))
 #define IXL_RSS_HENA_DEFAULT_BASE			\
 	(BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |	\
 	 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |	\
 	 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) |	\
 	 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) |	\
 	 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) |	\
 	 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |	\
 	 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |	\
 	 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) |	\
 	 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |	\
 	 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) |	\
 	 BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD))
 #define IXL_RSS_HENA_DEFAULT_XL710	IXL_RSS_HENA_DEFAULT_BASE
 #define IXL_RSS_HENA_DEFAULT_X722	(IXL_RSS_HENA_DEFAULT_XL710 |	\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |		\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) |		\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |		\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) |		\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) |	\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
 #define I40E_HASH_LUT_SIZE_128		0
 #define IXL_RSS_KEY_SIZE_REG		13
 #define IXL_ICR0_CRIT_ERR_MASK			\
 	(I40E_PFINT_ICR0_PCI_EXCEPTION_MASK |	\
 	I40E_PFINT_ICR0_ECC_ERR_MASK |		\
 	I40E_PFINT_ICR0_PE_CRITERR_MASK)
 #define IXL_QUEUE_MAX_XL710		64
 #define IXL_QUEUE_MAX_X722		128
 #define IXL_TX_PKT_DESCS		8
 #define IXL_TX_PKT_MAXSIZE		(MCLBYTES * IXL_TX_PKT_DESCS)
 #define IXL_TX_QUEUE_ALIGN		128
 #define IXL_RX_QUEUE_ALIGN		128
 #define IXL_MCLBYTES			(MCLBYTES - ETHER_ALIGN)
 #define IXL_MTU_ETHERLEN		ETHER_HDR_LEN		\
 					+ ETHER_CRC_LEN
 #if 0
 #define IXL_MAX_MTU			(9728 - IXL_MTU_ETHERLEN)
 #else
 /* (dbuff * 5) - ETHER_HDR_LEN - ETHER_CRC_LEN */
 #define IXL_MAX_MTU			(9600 - IXL_MTU_ETHERLEN)
 #endif
 #define IXL_MIN_MTU			(ETHER_MIN_LEN - ETHER_CRC_LEN)
 #define IXL_PCIREG			PCI_MAPREG_START
 #define IXL_ITR0			0x0
 #define IXL_ITR1			0x1
 #define IXL_ITR2			0x2
 #define IXL_NOITR			0x3
 #define IXL_AQ_NUM			256
 #define IXL_AQ_MASK			(IXL_AQ_NUM - 1)
 #define IXL_AQ_ALIGN			64 /* lol */
 #define IXL_AQ_BUFLEN			4096
 #define IXL_HMC_ROUNDUP			512
 #define IXL_HMC_PGSIZE			4096
 #define IXL_HMC_DVASZ			sizeof(uint64_t)
 #define IXL_HMC_PGS			(IXL_HMC_PGSIZE / IXL_HMC_DVASZ)
 #define IXL_HMC_L2SZ			(IXL_HMC_PGSIZE * IXL_HMC_PGS)
 #define IXL_HMC_PDVALID			1ULL
 #define IXL_ATQ_EXEC_TIMEOUT		(10 * hz)
 #define IXL_SRRD_SRCTL_ATTEMPTS		100000
 struct ixl_aq_regs {
 	bus_size_t		atq_tail;
 	bus_size_t		atq_head;
 	bus_size_t		atq_len;
 	bus_size_t		atq_bal;
 	bus_size_t		atq_bah;
 	bus_size_t		arq_tail;
 	bus_size_t		arq_head;
 	bus_size_t		arq_len;
 	bus_size_t		arq_bal;
 	bus_size_t		arq_bah;
 	uint32_t		atq_len_enable;
 	uint32_t		atq_tail_mask;
 	uint32_t		atq_head_mask;
 	uint32_t		arq_len_enable;
 	uint32_t		arq_tail_mask;
 	uint32_t		arq_head_mask;
 };
 struct ixl_phy_type {
 	uint64_t	phy_type;
 	uint64_t	ifm_type;
 };
 struct ixl_speed_type {
 	uint8_t		dev_speed;
 	uint64_t	net_speed;
 };
 struct ixl_aq_buf {
 	SIMPLEQ_ENTRY(ixl_aq_buf)
 				 aqb_entry;
 	void			*aqb_data;
 	bus_dmamap_t		 aqb_map;
 	bus_dma_segment_t	 aqb_seg;
 	size_t			 aqb_size;
 	int			 aqb_nsegs;
 };
 SIMPLEQ_HEAD(ixl_aq_bufs, ixl_aq_buf);
 struct ixl_dmamem {
 	bus_dmamap_t		 ixm_map;
 	bus_dma_segment_t	 ixm_seg;
 	int			 ixm_nsegs;
 	size_t			 ixm_size;
 	void			*ixm_kva;
 };
 #define IXL_DMA_MAP(_ixm)	((_ixm)->ixm_map)
 #define IXL_DMA_DVA(_ixm)	((_ixm)->ixm_map->dm_segs[0].ds_addr)
 #define IXL_DMA_KVA(_ixm)	((void *)(_ixm)->ixm_kva)
 #define IXL_DMA_LEN(_ixm)	((_ixm)->ixm_size)
 struct ixl_hmc_entry {
 	uint64_t		 hmc_base;
 	uint32_t		 hmc_count;
 	uint64_t		 hmc_size;
 };
 enum  ixl_hmc_types {
 	IXL_HMC_LAN_TX = 0,
 	IXL_HMC_LAN_RX,
 	IXL_HMC_FCOE_CTX,
 	IXL_HMC_FCOE_FILTER,
 	IXL_HMC_COUNT
 };
 struct ixl_hmc_pack {
 	uint16_t		offset;
 	uint16_t		width;
 	uint16_t		lsb;
 };
 /*
  * these hmc objects have weird sizes and alignments, so these are abstract
  * representations of them that are nice for c to populate.
+ *
  * the packing code relies on little-endian values being stored in the fields,
  * no high bits in the fields being set, and the fields must be packed in the
  * same order as they are in the ctx structure.
  */
 struct ixl_hmc_rxq {
 	uint16_t		 head;
 	uint8_t			 cpuid;
 	uint64_t		 base;
 #define IXL_HMC_RXQ_BASE_UNIT		128
 	uint16_t		 qlen;
 	uint16_t		 dbuff;
 #define IXL_HMC_RXQ_DBUFF_UNIT		128
 	uint8_t			 hbuff;
 #define IXL_HMC_RXQ_HBUFF_UNIT		64
 	uint8_t			 dtype;
 #define IXL_HMC_RXQ_DTYPE_NOSPLIT	0x0
 #define IXL_HMC_RXQ_DTYPE_HSPLIT	0x1
 #define IXL_HMC_RXQ_DTYPE_SPLIT_ALWAYS	0x2
 	uint8_t			 dsize;
 #define IXL_HMC_RXQ_DSIZE_16		0
 #define IXL_HMC_RXQ_DSIZE_32		1
 	uint8_t			 crcstrip;
 	uint8_t			 fc_ena;
 	uint8_t			 l2sel;
 	uint8_t			 hsplit_0;
 	uint8_t			 hsplit_1;
 	uint8_t			 showiv;
 	uint16_t		 rxmax;
 	uint8_t			 tphrdesc_ena;
 	uint8_t			 tphwdesc_ena;
 	uint8_t			 tphdata_ena;
 	uint8_t			 tphhead_ena;
 	uint8_t			 lrxqthresh;
 	uint8_t			 prefena;
 };
 static const struct ixl_hmc_pack ixl_hmc_pack_rxq[] = {
 	{ offsetof(struct ixl_hmc_rxq, head),		13,	0 },
 	{ offsetof(struct ixl_hmc_rxq, cpuid),		8,	13 },
 	{ offsetof(struct ixl_hmc_rxq, base),		57,	32 },
 	{ offsetof(struct ixl_hmc_rxq, qlen),		13,	89 },
 	{ offsetof(struct ixl_hmc_rxq, dbuff),		7,	102 },
 	{ offsetof(struct ixl_hmc_rxq, hbuff),		5,	109 },
 	{ offsetof(struct ixl_hmc_rxq, dtype),		2,	114 },
 	{ offsetof(struct ixl_hmc_rxq, dsize),		1,	116 },
 	{ offsetof(struct ixl_hmc_rxq, crcstrip),	1,	117 },
 	{ offsetof(struct ixl_hmc_rxq, fc_ena),		1,	118 },
 	{ offsetof(struct ixl_hmc_rxq, l2sel),		1,	119 },
 	{ offsetof(struct ixl_hmc_rxq, hsplit_0),	4,	120 },
 	{ offsetof(struct ixl_hmc_rxq, hsplit_1),	2,	124 },
 	{ offsetof(struct ixl_hmc_rxq, showiv),		1,	127 },
 	{ offsetof(struct ixl_hmc_rxq, rxmax),		14,	174 },
 	{ offsetof(struct ixl_hmc_rxq, tphrdesc_ena),	1,	193 },
 	{ offsetof(struct ixl_hmc_rxq, tphwdesc_ena),	1,	194 },
 	{ offsetof(struct ixl_hmc_rxq, tphdata_ena),	1,	195 },
 	{ offsetof(struct ixl_hmc_rxq, tphhead_ena),	1,	196 },
 	{ offsetof(struct ixl_hmc_rxq, lrxqthresh),	3,	198 },
 	{ offsetof(struct ixl_hmc_rxq, prefena),	1,	201 },
 };
 #define IXL_HMC_RXQ_MINSIZE (201 + 1)
 struct ixl_hmc_txq {
 	uint16_t		head;
 	uint8_t			new_context;
 	uint64_t		base;
 #define IXL_HMC_TXQ_BASE_UNIT		128
 	uint8_t			fc_ena;
 	uint8_t			timesync_ena;
 	uint8_t			fd_ena;
 	uint8_t			alt_vlan_ena;
 	uint8_t			cpuid;
 	uint16_t		thead_wb;
 	uint8_t			head_wb_ena;
 #define IXL_HMC_TXQ_DESC_WB		0
 #define IXL_HMC_TXQ_HEAD_WB		1
 	uint16_t		qlen;
 	uint8_t			tphrdesc_ena;
 	uint8_t			tphrpacket_ena;
 	uint8_t			tphwdesc_ena;
 	uint64_t		head_wb_addr;
 	uint32_t		crc;
 	uint16_t		rdylist;
 	uint8_t			rdylist_act;
 };
 static const struct ixl_hmc_pack ixl_hmc_pack_txq[] = {
 	{ offsetof(struct ixl_hmc_txq, head),		13,	0 },
 	{ offsetof(struct ixl_hmc_txq, new_context),	1,	30 },
 	{ offsetof(struct ixl_hmc_txq, base),		57,	32 },
 	{ offsetof(struct ixl_hmc_txq, fc_ena),		1,	89 },
 	{ offsetof(struct ixl_hmc_txq, timesync_ena),	1,	90 },
 	{ offsetof(struct ixl_hmc_txq, fd_ena),		1,	91 },
 	{ offsetof(struct ixl_hmc_txq, alt_vlan_ena),	1,	92 },
 	{ offsetof(struct ixl_hmc_txq, cpuid),		8,	96 },
 /* line 1 */
 	{ offsetof(struct ixl_hmc_txq, thead_wb),	13,	0 + 128 },
 	{ offsetof(struct ixl_hmc_txq, head_wb_ena),	1,	32 + 128 },
 	{ offsetof(struct ixl_hmc_txq, qlen),		13,	33 + 128 },
 	{ offsetof(struct ixl_hmc_txq, tphrdesc_ena),	1,	46 + 128 },
 	{ offsetof(struct ixl_hmc_txq, tphrpacket_ena),	1,	47 + 128 },
 	{ offsetof(struct ixl_hmc_txq, tphwdesc_ena),	1,	48 + 128 },
 	{ offsetof(struct ixl_hmc_txq, head_wb_addr),	64,	64 + 128 },
 /* line 7 */
 	{ offsetof(struct ixl_hmc_txq, crc),		32,	0 + (7*128) },
 	{ offsetof(struct ixl_hmc_txq, rdylist),	10,	84 + (7*128) },
 	{ offsetof(struct ixl_hmc_txq, rdylist_act),	1,	94 + (7*128) },
 };
 #define IXL_HMC_TXQ_MINSIZE (94 + (7*128) + 1)
 struct ixl_work {
 	struct work	 ixw_cookie;
 	void		(*ixw_func)(void *);
 	void		*ixw_arg;
 	unsigned int	 ixw_added;
 };
 #define IXL_WORKQUEUE_PRI	PRI_SOFTNET
 struct ixl_tx_map {
 	struct mbuf		*txm_m;
 	bus_dmamap_t		 txm_map;
 	unsigned int		 txm_eop;
 };
 struct ixl_tx_ring {
 	kmutex_t		 txr_lock;
 	struct ixl_softc	*txr_sc;
 	unsigned int		 txr_prod;
 	unsigned int		 txr_cons;
 	struct ixl_tx_map	*txr_maps;
 	struct ixl_dmamem	 txr_mem;
 	bus_size_t		 txr_tail;
 	unsigned int		 txr_qid;
 	pcq_t			*txr_intrq;
 	void			*txr_si;
 	struct evcnt		 txr_defragged;
 	struct evcnt		 txr_defrag_failed;
 	struct evcnt		 txr_pcqdrop;
 	struct evcnt		 txr_transmitdef;
 	struct evcnt		 txr_intr;
 	struct evcnt		 txr_defer;
 };
 struct ixl_rx_map {
 	struct mbuf		*rxm_m;
 	bus_dmamap_t		 rxm_map;
 };
 struct ixl_rx_ring {
 	kmutex_t		 rxr_lock;
 	unsigned int		 rxr_prod;
 	unsigned int		 rxr_cons;
 	struct ixl_rx_map	*rxr_maps;
 	struct ixl_dmamem	 rxr_mem;
 	struct mbuf		*rxr_m_head;
 	struct mbuf		**rxr_m_tail;
 	bus_size_t		 rxr_tail;
 	unsigned int		 rxr_qid;
 	struct evcnt		 rxr_mgethdr_failed;
 	struct evcnt		 rxr_mgetcl_failed;
 	struct evcnt		 rxr_mbuf_load_failed;
 	struct evcnt		 rxr_intr;
 	struct evcnt		 rxr_defer;
 };
 struct ixl_queue_pair {
 	struct ixl_softc	*qp_sc;
 	struct ixl_tx_ring	*qp_txr;
 	struct ixl_rx_ring	*qp_rxr;
 	char			 qp_name[16];
 	void			*qp_si;
 	struct work		 qp_work;
 	bool			 qp_workqueue;
 };
 struct ixl_atq {
 	struct ixl_aq_desc	 iatq_desc;
 	void			(*iatq_fn)(struct ixl_softc *,
 				    const struct ixl_aq_desc *);
 };
 SIMPLEQ_HEAD(ixl_atq_list, ixl_atq);
 struct ixl_product {
 	unsigned int	 vendor_id;
 	unsigned int	 product_id;
 };
 struct ixl_stats_counters {
 	bool		 isc_has_offset;
 	struct evcnt	 isc_crc_errors;
 	uint64_t	 isc_crc_errors_offset;
 	struct evcnt	 isc_illegal_bytes;
 	uint64_t	 isc_illegal_bytes_offset;
 	struct evcnt	 isc_rx_bytes;
 	uint64_t	 isc_rx_bytes_offset;
 	struct evcnt	 isc_rx_discards;
 	uint64_t	 isc_rx_discards_offset;
 	struct evcnt	 isc_rx_unicast;
 	uint64_t	 isc_rx_unicast_offset;
 	struct evcnt	 isc_rx_multicast;
 	uint64_t	 isc_rx_multicast_offset;
 	struct evcnt	 isc_rx_broadcast;
 	uint64_t	 isc_rx_broadcast_offset;
 	struct evcnt	 isc_rx_size_64;
 	uint64_t	 isc_rx_size_64_offset;
 	struct evcnt	 isc_rx_size_127;
 	uint64_t	 isc_rx_size_127_offset;
 	struct evcnt	 isc_rx_size_255;
 	uint64_t	 isc_rx_size_255_offset;
 	struct evcnt	 isc_rx_size_511;
 	uint64_t	 isc_rx_size_511_offset;
 	struct evcnt	 isc_rx_size_1023;
 	uint64_t	 isc_rx_size_1023_offset;
 	struct evcnt	 isc_rx_size_1522;
 	uint64_t	 isc_rx_size_1522_offset;
 	struct evcnt	 isc_rx_size_big;
 	uint64_t	 isc_rx_size_big_offset;
 	struct evcnt	 isc_rx_undersize;
 	uint64_t	 isc_rx_undersize_offset;
 	struct evcnt	 isc_rx_oversize;
 	uint64_t	 isc_rx_oversize_offset;
 	struct evcnt	 isc_rx_fragments;
 	uint64_t	 isc_rx_fragments_offset;
 	struct evcnt	 isc_rx_jabber;
 	uint64_t	 isc_rx_jabber_offset;
 	struct evcnt	 isc_tx_bytes;
 	uint64_t	 isc_tx_bytes_offset;
 	struct evcnt	 isc_tx_dropped_link_down;
 	uint64_t	 isc_tx_dropped_link_down_offset;
 	struct evcnt	 isc_tx_unicast;
 	uint64_t	 isc_tx_unicast_offset;
 	struct evcnt	 isc_tx_multicast;
 	uint64_t	 isc_tx_multicast_offset;
 	struct evcnt	 isc_tx_broadcast;
 	uint64_t	 isc_tx_broadcast_offset;
 	struct evcnt	 isc_tx_size_64;
 	uint64_t	 isc_tx_size_64_offset;
 	struct evcnt	 isc_tx_size_127;
 	uint64_t	 isc_tx_size_127_offset;
 	struct evcnt	 isc_tx_size_255;
 	uint64_t	 isc_tx_size_255_offset;
 	struct evcnt	 isc_tx_size_511;
 	uint64_t	 isc_tx_size_511_offset;
 	struct evcnt	 isc_tx_size_1023;
 	uint64_t	 isc_tx_size_1023_offset;
 	struct evcnt	 isc_tx_size_1522;
 	uint64_t	 isc_tx_size_1522_offset;
 	struct evcnt	 isc_tx_size_big;
 	uint64_t	 isc_tx_size_big_offset;
 	struct evcnt	 isc_mac_local_faults;
 	uint64_t	 isc_mac_local_faults_offset;
 	struct evcnt	 isc_mac_remote_faults;
 	uint64_t	 isc_mac_remote_faults_offset;
 	struct evcnt	 isc_link_xon_rx;
 	uint64_t	 isc_link_xon_rx_offset;
 	struct evcnt	 isc_link_xon_tx;
 	uint64_t	 isc_link_xon_tx_offset;
 	struct evcnt	 isc_link_xoff_rx;
 	uint64_t	 isc_link_xoff_rx_offset;
 	struct evcnt	 isc_link_xoff_tx;
 	uint64_t	 isc_link_xoff_tx_offset;
 	struct evcnt	 isc_vsi_rx_discards;
 	uint64_t	 isc_vsi_rx_discards_offset;
 	struct evcnt	 isc_vsi_rx_bytes;
 	uint64_t	 isc_vsi_rx_bytes_offset;
 	struct evcnt	 isc_vsi_rx_unicast;
 	uint64_t	 isc_vsi_rx_unicast_offset;
 	struct evcnt	 isc_vsi_rx_multicast;
 	uint64_t	 isc_vsi_rx_multicast_offset;
 	struct evcnt	 isc_vsi_rx_broadcast;
 	uint64_t	 isc_vsi_rx_broadcast_offset;
 	struct evcnt	 isc_vsi_tx_errors;
 	uint64_t	 isc_vsi_tx_errors_offset;
 	struct evcnt	 isc_vsi_tx_bytes;
 	uint64_t	 isc_vsi_tx_bytes_offset;
 	struct evcnt	 isc_vsi_tx_unicast;
 	uint64_t	 isc_vsi_tx_unicast_offset;
 	struct evcnt	 isc_vsi_tx_multicast;
 	uint64_t	 isc_vsi_tx_multicast_offset;
 	struct evcnt	 isc_vsi_tx_broadcast;
 	uint64_t	 isc_vsi_tx_broadcast_offset;
 };
 /*
  * Locking notes:
  * + a field in ixl_tx_ring is protected by txr_lock (a spin mutex), and
  *   a field in ixl_rx_ring is protected by rxr_lock (a spin mutex).
  *    - more than one lock of them cannot be held at once.
  * + a field named sc_atq_* in ixl_softc is protected by sc_atq_lock
  *   (a spin mutex).
  *    - the lock cannot held with txr_lock or rxr_lock.
  * + a field named sc_arq_* is not protected by any lock.
  *    - operations for sc_arq_* is done in one context related to
  *      sc_arq_task.
  * + other fields in ixl_softc is protected by sc_cfg_lock
  *   (an adaptive mutex)
  *    - It must be held before another lock is held, and It can be
  *      released after the other lock is released.
  * */
 struct ixl_softc {
 	device_t		 sc_dev;
 	struct ethercom		 sc_ec;
 	bool			 sc_attached;
 	bool			 sc_dead;
 	uint32_t		 sc_port;
 	struct sysctllog	*sc_sysctllog;
 	struct workqueue	*sc_workq;
 	struct workqueue	*sc_workq_txrx;
 	int			 sc_stats_intval;
 	callout_t		 sc_stats_callout;
 	struct ixl_work		 sc_stats_task;
 	struct ixl_stats_counters
 				 sc_stats_counters;
 	uint8_t			 sc_enaddr[ETHER_ADDR_LEN];
 	struct ifmedia		 sc_media;
 	uint64_t		 sc_media_status;
 	uint64_t		 sc_media_active;
 	uint64_t		 sc_phy_types;
 	uint8_t			 sc_phy_abilities;
 	uint8_t			 sc_phy_linkspeed;
 	uint8_t			 sc_phy_fec_cfg;
 	uint16_t		 sc_eee_cap;
 	uint32_t		 sc_eeer_val;
 	uint8_t			 sc_d3_lpan;
 	kmutex_t		 sc_cfg_lock;
 	enum i40e_mac_type	 sc_mac_type;
 	uint32_t		 sc_rss_table_size;
 	uint32_t		 sc_rss_table_entry_width;
 	bool			 sc_txrx_workqueue;
 	u_int			 sc_tx_process_limit;
 	u_int			 sc_rx_process_limit;
 	u_int			 sc_tx_intr_process_limit;
 	u_int			 sc_rx_intr_process_limit;
 	int			 sc_cur_ec_capenable;
 	struct pci_attach_args	 sc_pa;
 	pci_intr_handle_t	*sc_ihp;
 	void			**sc_ihs;
 	unsigned int		 sc_nintrs;
 	bus_dma_tag_t		 sc_dmat;
 	bus_space_tag_t		 sc_memt;
 	bus_space_handle_t	 sc_memh;
 	bus_size_t		 sc_mems;
 	uint8_t			 sc_pf_id;
 	uint16_t		 sc_uplink_seid;	/* le */
 	uint16_t		 sc_downlink_seid;	/* le */
 	uint16_t		 sc_vsi_number;
 	uint16_t		 sc_vsi_stat_counter_idx;
 	uint16_t		 sc_seid;
 	unsigned int		 sc_base_queue;
 	pci_intr_type_t		 sc_intrtype;
 	unsigned int		 sc_msix_vector_queue;
 	struct ixl_dmamem	 sc_scratch;
 	struct ixl_dmamem	 sc_aqbuf;
 	const struct ixl_aq_regs *
 				 sc_aq_regs;
 	uint32_t		 sc_aq_flags;
 #define IXL_SC_AQ_FLAG_RXCTL	__BIT(0)
 #define IXL_SC_AQ_FLAG_NVMLOCK	__BIT(1)
 #define IXL_SC_AQ_FLAG_NVMREAD	__BIT(2)
 #define IXL_SC_AQ_FLAG_RSS	__BIT(3)
 	kmutex_t		 sc_atq_lock;
 	kcondvar_t		 sc_atq_cv;
 	struct ixl_dmamem	 sc_atq;
 	unsigned int		 sc_atq_prod;
 	unsigned int		 sc_atq_cons;
 	struct ixl_dmamem	 sc_arq;
 	struct ixl_work		 sc_arq_task;
 	struct ixl_aq_bufs	 sc_arq_idle;
 	struct ixl_aq_buf	*sc_arq_live[IXL_AQ_NUM];
 	unsigned int		 sc_arq_prod;
 	unsigned int		 sc_arq_cons;
 	struct ixl_work		 sc_link_state_task;
 	struct ixl_atq		 sc_link_state_atq;
 	struct ixl_dmamem	 sc_hmc_sd;
 	struct ixl_dmamem	 sc_hmc_pd;
 	struct ixl_hmc_entry	 sc_hmc_entries[IXL_HMC_COUNT];
 	unsigned int		 sc_tx_ring_ndescs;
 	unsigned int		 sc_rx_ring_ndescs;
 	unsigned int		 sc_nqueue_pairs;
 	unsigned int		 sc_nqueue_pairs_max;
 	unsigned int		 sc_nqueue_pairs_device;
 	struct ixl_queue_pair	*sc_qps;
 	uint32_t		 sc_itr_rx;
 	uint32_t		 sc_itr_tx;
 	struct evcnt		 sc_event_atq;
 	struct evcnt		 sc_event_link;
 	struct evcnt		 sc_event_ecc_err;
 	struct evcnt		 sc_event_pci_exception;
 	struct evcnt		 sc_event_crit_err;
 };
 #define IXL_TXRX_PROCESS_UNLIMIT	UINT_MAX
 #define IXL_TX_PROCESS_LIMIT		256
 #define IXL_RX_PROCESS_LIMIT		256
 #define IXL_TX_INTR_PROCESS_LIMIT	256
 #define IXL_RX_INTR_PROCESS_LIMIT	0U
 #define IXL_IFCAP_RXCSUM	(IFCAP_CSUM_IPv4_Rx |	\
 				 IFCAP_CSUM_TCPv4_Rx |	\
 				 IFCAP_CSUM_UDPv4_Rx |	\
 				 IFCAP_CSUM_TCPv6_Rx |	\
 				 IFCAP_CSUM_UDPv6_Rx)
 #define IXL_IFCAP_TXCSUM	(IFCAP_CSUM_IPv4_Tx |	\
 				 IFCAP_CSUM_TCPv4_Tx |	\
 				 IFCAP_CSUM_UDPv4_Tx |	\
 				 IFCAP_CSUM_TCPv6_Tx |	\
 				 IFCAP_CSUM_UDPv6_Tx)
 #define IXL_CSUM_ALL_OFFLOAD	(M_CSUM_IPv4 |			\
 				 M_CSUM_TCPv4 | M_CSUM_TCPv6 |	\
 				 M_CSUM_UDPv4 | M_CSUM_UDPv6)
 #define delaymsec(_x)	DELAY(1000 * (_x))
 #ifdef IXL_DEBUG
 #define DDPRINTF(sc, fmt, args...)			\
 do {							\
 	if ((sc) != NULL) {				\
 		device_printf(				\
 		    ((struct ixl_softc *)(sc))->sc_dev,	\
 		    "");				\
 	}						\
 	printf("%s:\t" fmt, __func__, ##args);		\
 } while (0)
 #else
 #define DDPRINTF(sc, fmt, args...)	__nothing
 #endif
 #ifndef IXL_STATS_INTERVAL_MSEC
 #define IXL_STATS_INTERVAL_MSEC	10000
 #endif
 #ifndef IXL_QUEUE_NUM
 #define IXL_QUEUE_NUM		0
 #endif
 static bool		 ixl_param_nomsix = false;
 static int		 ixl_param_stats_interval = IXL_STATS_INTERVAL_MSEC;
 static int		 ixl_param_nqps_limit = IXL_QUEUE_NUM;
 static unsigned int	 ixl_param_tx_ndescs = 1024;
 static unsigned int	 ixl_param_rx_ndescs = 1024;
 static enum i40e_mac_type
-    ixl_mactype(pci_product_id_t);
+	    ixl_mactype(pci_product_id_t);
 static void	ixl_pci_csr_setup(pci_chipset_tag_t, pcitag_t);
 static void	ixl_clear_hw(struct ixl_softc *);
 static int	ixl_pf_reset(struct ixl_softc *);
 static int	ixl_dmamem_alloc(struct ixl_softc *, struct ixl_dmamem *,
 		    bus_size_t, bus_size_t);
 static void	ixl_dmamem_free(struct ixl_softc *, struct ixl_dmamem *);
 static int	ixl_arq_fill(struct ixl_softc *);
 static void	ixl_arq_unfill(struct ixl_softc *);
 static int	ixl_atq_poll(struct ixl_softc *, struct ixl_aq_desc *,
 		    unsigned int);
 static void	ixl_atq_set(struct ixl_atq *,
 		    void (*)(struct ixl_softc *, const struct ixl_aq_desc *));
 static int	ixl_atq_post_locked(struct ixl_softc *, struct ixl_atq *);
 static void	ixl_atq_done(struct ixl_softc *);
 static int	ixl_atq_exec(struct ixl_softc *, struct ixl_atq *);
 static int	ixl_atq_exec_locked(struct ixl_softc *, struct ixl_atq *);
 static int	ixl_get_version(struct ixl_softc *);
 static int	ixl_get_nvm_version(struct ixl_softc *);
 static int	ixl_get_hw_capabilities(struct ixl_softc *);
 static int	ixl_pxe_clear(struct ixl_softc *);
 static int	ixl_lldp_shut(struct ixl_softc *);
 static int	ixl_get_mac(struct ixl_softc *);
 static int	ixl_get_switch_config(struct ixl_softc *);
 static int	ixl_phy_mask_ints(struct ixl_softc *);
 static int	ixl_get_phy_info(struct ixl_softc *);
 static int	ixl_set_phy_config(struct ixl_softc *, uint8_t, uint8_t, bool);
 static int	ixl_set_phy_autoselect(struct ixl_softc *);
 static int	ixl_restart_an(struct ixl_softc *);
 static int	ixl_hmc(struct ixl_softc *);
 static void	ixl_hmc_free(struct ixl_softc *);
 static int	ixl_get_vsi(struct ixl_softc *);
 static int	ixl_set_vsi(struct ixl_softc *);
 static void	ixl_set_filter_control(struct ixl_softc *);
 static void	ixl_get_link_status(void *);
 static int	ixl_get_link_status_poll(struct ixl_softc *, int *);
 static void	ixl_get_link_status_done(struct ixl_softc *,
 		    const struct ixl_aq_desc *);
 static int	ixl_set_link_status_locked(struct ixl_softc *,
 		    const struct ixl_aq_desc *);
 static uint64_t	ixl_search_link_speed(uint8_t);
 static uint8_t	ixl_search_baudrate(uint64_t);
 static void	ixl_config_rss(struct ixl_softc *);
 static int	ixl_add_macvlan(struct ixl_softc *, const uint8_t *,
 		    uint16_t, uint16_t);
 static int	ixl_remove_macvlan(struct ixl_softc *, const uint8_t *,
 		    uint16_t, uint16_t);
 static void	ixl_arq(void *);
 static void	ixl_hmc_pack(void *, const void *,
 		    const struct ixl_hmc_pack *, unsigned int);
 static uint32_t	ixl_rd_rx_csr(struct ixl_softc *, uint32_t);
 static void	ixl_wr_rx_csr(struct ixl_softc *, uint32_t, uint32_t);
 static int	ixl_rd16_nvm(struct ixl_softc *, uint16_t, uint16_t *);
 static int	ixl_match(device_t, cfdata_t, void *);
 static void	ixl_attach(device_t, device_t, void *);
 static int	ixl_detach(device_t, int);
 static void	ixl_media_add(struct ixl_softc *);
 static int	ixl_media_change(struct ifnet *);
 static void	ixl_media_status(struct ifnet *, struct ifmediareq *);
 static void	ixl_watchdog(struct ifnet *);
 static int	ixl_ioctl(struct ifnet *, u_long, void *);
 static void	ixl_start(struct ifnet *);
 static int	ixl_transmit(struct ifnet *, struct mbuf *);
 static void	ixl_deferred_transmit(void *);
 static int	ixl_intr(void *);
 static int	ixl_queue_intr(void *);
 static int	ixl_other_intr(void *);
 static void	ixl_handle_queue(void *);
 static void	ixl_handle_queue_wk(struct work *, void *);
 static void	ixl_sched_handle_queue(struct ixl_softc *,
 		    struct ixl_queue_pair *);
 static int	ixl_init(struct ifnet *);
 static int	ixl_init_locked(struct ixl_softc *);
 static void	ixl_stop(struct ifnet *, int);
 static void	ixl_stop_locked(struct ixl_softc *);
 static int	ixl_iff(struct ixl_softc *);
 static int	ixl_ifflags_cb(struct ethercom *);
 static int	ixl_setup_interrupts(struct ixl_softc *);
 static int	ixl_establish_intx(struct ixl_softc *);
 static int	ixl_establish_msix(struct ixl_softc *);
 static void	ixl_enable_queue_intr(struct ixl_softc *,
 		    struct ixl_queue_pair *);
 static void	ixl_disable_queue_intr(struct ixl_softc *,
 		    struct ixl_queue_pair *);
 static void	ixl_enable_other_intr(struct ixl_softc *);
 static void	ixl_disable_other_intr(struct ixl_softc *);
 static void	ixl_config_queue_intr(struct ixl_softc *);
 static void	ixl_config_other_intr(struct ixl_softc *);
 static struct ixl_tx_ring *
 		ixl_txr_alloc(struct ixl_softc *, unsigned int);
 static void	ixl_txr_qdis(struct ixl_softc *, struct ixl_tx_ring *, int);
 static void	ixl_txr_config(struct ixl_softc *, struct ixl_tx_ring *);
 static int	ixl_txr_enabled(struct ixl_softc *, struct ixl_tx_ring *);
 static int	ixl_txr_disabled(struct ixl_softc *, struct ixl_tx_ring *);
 static void	ixl_txr_unconfig(struct ixl_softc *, struct ixl_tx_ring *);
 static void	ixl_txr_clean(struct ixl_softc *, struct ixl_tx_ring *);
 static void	ixl_txr_free(struct ixl_softc *, struct ixl_tx_ring *);
 static int	ixl_txeof(struct ixl_softc *, struct ixl_tx_ring *, u_int);
 static struct ixl_rx_ring *
 		ixl_rxr_alloc(struct ixl_softc *, unsigned int);
 static void	ixl_rxr_config(struct ixl_softc *, struct ixl_rx_ring *);
 static int	ixl_rxr_enabled(struct ixl_softc *, struct ixl_rx_ring *);
 static int	ixl_rxr_disabled(struct ixl_softc *, struct ixl_rx_ring *);
 static void	ixl_rxr_unconfig(struct ixl_softc *, struct ixl_rx_ring *);
 static void	ixl_rxr_clean(struct ixl_softc *, struct ixl_rx_ring *);
 static void	ixl_rxr_free(struct ixl_softc *, struct ixl_rx_ring *);
 static int	ixl_rxeof(struct ixl_softc *, struct ixl_rx_ring *, u_int);
 static int	ixl_rxfill(struct ixl_softc *, struct ixl_rx_ring *);
 static struct workqueue *
     ixl_workq_create(const char *, pri_t, int, int);
 static void	ixl_workq_destroy(struct workqueue *);
 static int	ixl_workqs_teardown(device_t);
 static void	ixl_work_set(struct ixl_work *, void (*)(void *), void *);
 static void	ixl_work_add(struct workqueue *, struct ixl_work *);
 static void	ixl_work_wait(struct workqueue *, struct ixl_work *);
 static void	ixl_workq_work(struct work *, void *);
 static const struct ixl_product *
 		ixl_lookup(const struct pci_attach_args *pa);
 static void	ixl_link_state_update(struct ixl_softc *,
 		    const struct ixl_aq_desc *);
 static int	ixl_vlan_cb(struct ethercom *, uint16_t, bool);
 static int	ixl_setup_vlan_hwfilter(struct ixl_softc *);
 static void	ixl_teardown_vlan_hwfilter(struct ixl_softc *);
 static int	ixl_update_macvlan(struct ixl_softc *);
 static int	ixl_setup_interrupts(struct ixl_softc *);
 static void	ixl_teardown_interrupts(struct ixl_softc *);
 static int	ixl_setup_stats(struct ixl_softc *);
 static void	ixl_teardown_stats(struct ixl_softc *);
 static void	ixl_stats_callout(void *);
 static void	ixl_stats_update(void *);
 static int	ixl_setup_sysctls(struct ixl_softc *);
 static void	ixl_teardown_sysctls(struct ixl_softc *);
 static int	ixl_queue_pairs_alloc(struct ixl_softc *);
 static void	ixl_queue_pairs_free(struct ixl_softc *);
 static const struct ixl_phy_type ixl_phy_type_map[] = {
 	{ 1ULL << IXL_PHY_TYPE_SGMII,		IFM_1000_SGMII },
 	{ 1ULL << IXL_PHY_TYPE_1000BASE_KX,	IFM_1000_KX },
 	{ 1ULL << IXL_PHY_TYPE_10GBASE_KX4,	IFM_10G_KX4 },
 	{ 1ULL << IXL_PHY_TYPE_10GBASE_KR,	IFM_10G_KR },
 	{ 1ULL << IXL_PHY_TYPE_40GBASE_KR4,	IFM_40G_KR4 },
 	{ 1ULL << IXL_PHY_TYPE_XAUI |
 ULL << IXL_PHY_TYPE_XFI,		IFM_10G_CX4 },
 	{ 1ULL << IXL_PHY_TYPE_SFI,		IFM_10G_SFI },
 	{ 1ULL << IXL_PHY_TYPE_XLAUI |
 ULL << IXL_PHY_TYPE_XLPPI,		IFM_40G_XLPPI },
 	{ 1ULL << IXL_PHY_TYPE_40GBASE_CR4_CU |
 ULL << IXL_PHY_TYPE_40GBASE_CR4,	IFM_40G_CR4 },
 	{ 1ULL << IXL_PHY_TYPE_10GBASE_CR1_CU |
 ULL << IXL_PHY_TYPE_10GBASE_CR1,	IFM_10G_CR1 },
 	{ 1ULL << IXL_PHY_TYPE_10GBASE_AOC,	IFM_10G_AOC },
 	{ 1ULL << IXL_PHY_TYPE_40GBASE_AOC,	IFM_40G_AOC },
 	{ 1ULL << IXL_PHY_TYPE_100BASE_TX,	IFM_100_TX },
 	{ 1ULL << IXL_PHY_TYPE_1000BASE_T_OPTICAL |
 ULL << IXL_PHY_TYPE_1000BASE_T,	IFM_1000_T },
 	{ 1ULL << IXL_PHY_TYPE_10GBASE_T,	IFM_10G_T },
 	{ 1ULL << IXL_PHY_TYPE_10GBASE_SR,	IFM_10G_SR },
 	{ 1ULL << IXL_PHY_TYPE_10GBASE_LR,	IFM_10G_LR },
 	{ 1ULL << IXL_PHY_TYPE_10GBASE_SFPP_CU,	IFM_10G_TWINAX },
 	{ 1ULL << IXL_PHY_TYPE_40GBASE_SR4,	IFM_40G_SR4 },
 	{ 1ULL << IXL_PHY_TYPE_40GBASE_LR4,	IFM_40G_LR4 },
 	{ 1ULL << IXL_PHY_TYPE_1000BASE_SX,	IFM_1000_SX },
 	{ 1ULL << IXL_PHY_TYPE_1000BASE_LX,	IFM_1000_LX },
 	{ 1ULL << IXL_PHY_TYPE_20GBASE_KR2,	IFM_20G_KR2 },
 	{ 1ULL << IXL_PHY_TYPE_25GBASE_KR,	IFM_25G_KR },
 	{ 1ULL << IXL_PHY_TYPE_25GBASE_CR,	IFM_25G_CR },
 	{ 1ULL << IXL_PHY_TYPE_25GBASE_SR,	IFM_25G_SR },
 	{ 1ULL << IXL_PHY_TYPE_25GBASE_LR,	IFM_25G_LR },
 	{ 1ULL << IXL_PHY_TYPE_25GBASE_AOC,	IFM_25G_AOC },
 	{ 1ULL << IXL_PHY_TYPE_25GBASE_ACC,	IFM_25G_ACC },
 };
 static const struct ixl_speed_type ixl_speed_type_map[] = {
 	{ IXL_AQ_LINK_SPEED_40GB,		IF_Gbps(40) },
 	{ IXL_AQ_LINK_SPEED_25GB,		IF_Gbps(25) },
 	{ IXL_AQ_LINK_SPEED_10GB,		IF_Gbps(10) },
 	{ IXL_AQ_LINK_SPEED_1000MB,		IF_Mbps(1000) },
 	{ IXL_AQ_LINK_SPEED_100MB,		IF_Mbps(100)},
 };
 static const struct ixl_aq_regs ixl_pf_aq_regs = {
 	.atq_tail	= I40E_PF_ATQT,
 	.atq_tail_mask	= I40E_PF_ATQT_ATQT_MASK,
 	.atq_head	= I40E_PF_ATQH,
 	.atq_head_mask	= I40E_PF_ATQH_ATQH_MASK,
 	.atq_len	= I40E_PF_ATQLEN,
 	.atq_bal	= I40E_PF_ATQBAL,
 	.atq_bah	= I40E_PF_ATQBAH,
 	.atq_len_enable	= I40E_PF_ATQLEN_ATQENABLE_MASK,
 	.arq_tail	= I40E_PF_ARQT,
 	.arq_tail_mask	= I40E_PF_ARQT_ARQT_MASK,
 	.arq_head	= I40E_PF_ARQH,
 	.arq_head_mask	= I40E_PF_ARQH_ARQH_MASK,
 	.arq_len	= I40E_PF_ARQLEN,
 	.arq_bal	= I40E_PF_ARQBAL,
 	.arq_bah	= I40E_PF_ARQBAH,
 	.arq_len_enable	= I40E_PF_ARQLEN_ARQENABLE_MASK,
 };
 #define ixl_rd(_s, _r)			\
 	bus_space_read_4((_s)->sc_memt, (_s)->sc_memh, (_r))
 #define ixl_wr(_s, _r, _v)		\
 	bus_space_write_4((_s)->sc_memt, (_s)->sc_memh, (_r), (_v))
 #define ixl_barrier(_s, _r, _l, _o) \
     bus_space_barrier((_s)->sc_memt, (_s)->sc_memh, (_r), (_l), (_o))
 #define ixl_flush(_s)	(void)ixl_rd((_s), I40E_GLGEN_STAT)
 #define ixl_nqueues(_sc)	(1 << ((_sc)->sc_nqueue_pairs - 1))
 static inline uint32_t
 ixl_dmamem_hi(struct ixl_dmamem *ixm)
+{
 	uint32_t retval;
 	uint64_t val;
 	if (sizeof(IXL_DMA_DVA(ixm)) > 4) {
 		val = (intptr_t)IXL_DMA_DVA(ixm);
 		retval = (uint32_t)(val >> 32);
 	} else {
 		retval = 0;
+	}
 	return retval;
+}
 static inline uint32_t
 ixl_dmamem_lo(struct ixl_dmamem *ixm)
+{
 	return (uint32_t)IXL_DMA_DVA(ixm);
+}
 static inline void
 ixl_aq_dva(struct ixl_aq_desc *iaq, bus_addr_t addr)
+{
 	uint64_t val;
 	if (sizeof(addr) > 4) {
 		val = (intptr_t)addr;
 		iaq->iaq_param[2] = htole32(val >> 32);
 	} else {
 		iaq->iaq_param[2] = htole32(0);
+	}
 	iaq->iaq_param[3] = htole32(addr);
+}
 static inline unsigned int
 ixl_rxr_unrefreshed(unsigned int prod, unsigned int cons, unsigned int ndescs)
+{
 	unsigned int num;
 	if (prod  < cons)
 		num = cons - prod;
 	else
 		num  = (ndescs - prod) + cons;
 	if (__predict_true(num > 0)) {
 		/* device cannot receive packets if all descripter is filled */
 		num -= 1;
+	}
 	return num;
+}
 CFATTACH_DECL3_NEW(ixl, sizeof(struct ixl_softc),
     ixl_match, ixl_attach, ixl_detach, NULL, NULL, NULL,
     DVF_DETACH_SHUTDOWN);
 static const struct ixl_product ixl_products[] = {
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_XL710_SFP },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_XL710_KX_B },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_XL710_KX_C },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_XL710_QSFP_A },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_XL710_QSFP_B },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_XL710_QSFP_C },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_X710_10G_T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_XL710_20G_BP_1 },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_XL710_20G_BP_2 },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_X710_T4_10G },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_XXV710_25G_BP },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_XXV710_25G_SFP28 },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_X722_KX },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_X722_QSFP },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_X722_SFP },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_X722_1G_BASET },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_X722_10G_BASET },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_X722_I_SFP },
 	/* required last entry */
 	{0, 0}
 };
 static const struct ixl_product *
 ixl_lookup(const struct pci_attach_args *pa)
+{
 	const struct ixl_product *ixlp;
 	for (ixlp = ixl_products; ixlp->vendor_id != 0; ixlp++) {
 		if (PCI_VENDOR(pa->pa_id) == ixlp->vendor_id &&
 		    PCI_PRODUCT(pa->pa_id) == ixlp->product_id)
 			return ixlp;
+	}
 	return NULL;
+}
 static int
 ixl_match(device_t parent, cfdata_t match, void *aux)
+{
 	const struct pci_attach_args *pa = aux;
 	return (ixl_lookup(pa) != NULL) ? 1 : 0;
+}
 static void
 ixl_attach(device_t parent, device_t self, void *aux)
+{
 	struct ixl_softc *sc;
 	struct pci_attach_args *pa = aux;
 	struct ifnet *ifp;
 	pcireg_t memtype;
 	uint32_t firstq, port, ari, func;
 	char xnamebuf[32];
 	int tries, rv, link;
 	sc = device_private(self);
 	sc->sc_dev = self;
 	ifp = &sc->sc_ec.ec_if;
 	sc->sc_pa = *pa;
 	sc->sc_dmat = (pci_dma64_available(pa)) ?
 	    pa->pa_dmat64 : pa->pa_dmat;
 	sc->sc_aq_regs = &ixl_pf_aq_regs;
 	sc->sc_mac_type = ixl_mactype(PCI_PRODUCT(pa->pa_id));
 	ixl_pci_csr_setup(pa->pa_pc, pa->pa_tag);
 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IXL_PCIREG);
 	if (pci_mapreg_map(pa, IXL_PCIREG, memtype, 0,
 	    &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) {
 		aprint_error(": unable to map registers\n");
 		return;
+	}
 	mutex_init(&sc->sc_cfg_lock, MUTEX_DEFAULT, IPL_SOFTNET);
 	firstq = ixl_rd(sc, I40E_PFLAN_QALLOC);
 	firstq &= I40E_PFLAN_QALLOC_FIRSTQ_MASK;
 	firstq >>= I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
 	sc->sc_base_queue = firstq;
 	ixl_clear_hw(sc);
 	if (ixl_pf_reset(sc) == -1) {
 		/* error printed by ixl pf_reset */
 		goto unmap;
+	}
 	port = ixl_rd(sc, I40E_PFGEN_PORTNUM);
 	port &= I40E_PFGEN_PORTNUM_PORT_NUM_MASK;
 	port >>= I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
 	sc->sc_port = port;
 	aprint_normal(": port %u", sc->sc_port);
 	ari = ixl_rd(sc, I40E_GLPCI_CAPSUP);
 	ari &= I40E_GLPCI_CAPSUP_ARI_EN_MASK;
 	ari >>= I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
 	func = ixl_rd(sc, I40E_PF_FUNC_RID);
 	sc->sc_pf_id = func & (ari ? 0xff : 0x7);
 	/* initialise the adminq */
 	mutex_init(&sc->sc_atq_lock, MUTEX_DEFAULT, IPL_NET);
 	if (ixl_dmamem_alloc(sc, &sc->sc_atq,
 	    sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) {
 		aprint_error("\n" "%s: unable to allocate atq\n",
 		    device_xname(self));
 		goto unmap;
+	}
 	SIMPLEQ_INIT(&sc->sc_arq_idle);
 	ixl_work_set(&sc->sc_arq_task, ixl_arq, sc);
 	sc->sc_arq_cons = 0;
 	sc->sc_arq_prod = 0;
 	if (ixl_dmamem_alloc(sc, &sc->sc_arq,
 	    sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) {
 		aprint_error("\n" "%s: unable to allocate arq\n",
 		    device_xname(self));
 		goto free_atq;
+	}
 	if (!ixl_arq_fill(sc)) {
 		aprint_error("\n" "%s: unable to fill arq descriptors\n",
 		    device_xname(self));
 		goto free_arq;
+	}
 	bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq),
 , IXL_DMA_LEN(&sc->sc_atq),
 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 	bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq),
 , IXL_DMA_LEN(&sc->sc_arq),
 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 	for (tries = 0; tries < 10; tries++) {
 		sc->sc_atq_cons = 0;
 		sc->sc_atq_prod = 0;
 		ixl_wr(sc, sc->sc_aq_regs->atq_head, 0);
 		ixl_wr(sc, sc->sc_aq_regs->arq_head, 0);
 		ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0);
 		ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0);
 		ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE);
 		ixl_wr(sc, sc->sc_aq_regs->atq_bal,
 		    ixl_dmamem_lo(&sc->sc_atq));
 		ixl_wr(sc, sc->sc_aq_regs->atq_bah,
 		    ixl_dmamem_hi(&sc->sc_atq));
 		ixl_wr(sc, sc->sc_aq_regs->atq_len,
 		    sc->sc_aq_regs->atq_len_enable | IXL_AQ_NUM);
 		ixl_wr(sc, sc->sc_aq_regs->arq_bal,
 		    ixl_dmamem_lo(&sc->sc_arq));
 		ixl_wr(sc, sc->sc_aq_regs->arq_bah,
 		    ixl_dmamem_hi(&sc->sc_arq));
 		ixl_wr(sc, sc->sc_aq_regs->arq_len,
 		    sc->sc_aq_regs->arq_len_enable | IXL_AQ_NUM);
 		rv = ixl_get_version(sc);
 		if (rv == 0)
 			break;
 		if (rv != ETIMEDOUT) {
 			aprint_error(", unable to get firmware version\n");
 			goto shutdown;
+		}
 		delaymsec(100);
+	}
 	ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod);
 	if (ixl_dmamem_alloc(sc, &sc->sc_aqbuf, IXL_AQ_BUFLEN, 0) != 0) {
 		aprint_error_dev(self, ", unable to allocate nvm buffer\n");
 		goto shutdown;
+	}
 	ixl_get_nvm_version(sc);
 	if (sc->sc_mac_type == I40E_MAC_X722)
 		sc->sc_nqueue_pairs_device = IXL_QUEUE_MAX_X722;
 	else
 		sc->sc_nqueue_pairs_device = IXL_QUEUE_MAX_XL710;
 	rv = ixl_get_hw_capabilities(sc);
 	if (rv != 0) {
 		aprint_error(", GET HW CAPABILITIES %s\n",
 		    rv == ETIMEDOUT ? "timeout" : "error");
 		goto free_aqbuf;
+	}
 	sc->sc_nqueue_pairs_max = MIN((int)sc->sc_nqueue_pairs_device, ncpu);
 	if (ixl_param_nqps_limit > 0) {
 		sc->sc_nqueue_pairs_max = MIN((int)sc->sc_nqueue_pairs_max,
 		    ixl_param_nqps_limit);
+	}
 	sc->sc_nqueue_pairs = sc->sc_nqueue_pairs_max;
 	sc->sc_tx_ring_ndescs = ixl_param_tx_ndescs;
 	sc->sc_rx_ring_ndescs = ixl_param_rx_ndescs;
 	KASSERT(IXL_TXRX_PROCESS_UNLIMIT > sc->sc_rx_ring_ndescs);
 	KASSERT(IXL_TXRX_PROCESS_UNLIMIT > sc->sc_tx_ring_ndescs);
 	if (ixl_get_mac(sc) != 0) {
 		/* error printed by ixl_get_mac */
 		goto free_aqbuf;
+	}
 	aprint_normal("\n");
 	aprint_naive("\n");
 	aprint_normal_dev(self, "Ethernet address %s\n",
 	    ether_sprintf(sc->sc_enaddr));
 	rv = ixl_pxe_clear(sc);
 	if (rv != 0) {
 		aprint_debug_dev(self, "CLEAR PXE MODE %s\n",
 		    rv == ETIMEDOUT ? "timeout" : "error");
+	}
 	ixl_set_filter_control(sc);
 	if (ixl_hmc(sc) != 0) {
 		/* error printed by ixl_hmc */
 		goto free_aqbuf;
+	}
 	if (ixl_lldp_shut(sc) != 0) {
 		/* error printed by ixl_lldp_shut */
 		goto free_hmc;
+	}
 	if (ixl_phy_mask_ints(sc) != 0) {
 		/* error printed by ixl_phy_mask_ints */
 		goto free_hmc;
+	}
 	if (ixl_restart_an(sc) != 0) {
 		/* error printed by ixl_restart_an */
 		goto free_hmc;
+	}
 	if (ixl_get_switch_config(sc) != 0) {
 		/* error printed by ixl_get_switch_config */
 		goto free_hmc;
+	}
 	rv = ixl_get_link_status_poll(sc, NULL);
 	if (rv != 0) {
 		aprint_error_dev(self, "GET LINK STATUS %s\n",
 		    rv == ETIMEDOUT ? "timeout" : "error");
 		goto free_hmc;
+	}
 	/*
 	 * The FW often returns EIO in "Get PHY Abilities" command
 	 * if there is no delay
 	 */
 	DELAY(500);
 	if (ixl_get_phy_info(sc) != 0) {
 		/* error printed by ixl_get_phy_info */
 		goto free_hmc;
+	}
 	if (ixl_dmamem_alloc(sc, &sc->sc_scratch,
 	    sizeof(struct ixl_aq_vsi_data), 8) != 0) {
 		aprint_error_dev(self, "unable to allocate scratch buffer\n");
 		goto free_hmc;
+	}
 	rv = ixl_get_vsi(sc);
 	if (rv != 0) {
 		aprint_error_dev(self, "GET VSI %s %d\n",
 		    rv == ETIMEDOUT ? "timeout" : "error", rv);
 		goto free_scratch;
+	}
 	rv = ixl_set_vsi(sc);
 	if (rv != 0) {
 		aprint_error_dev(self, "UPDATE VSI error %s %d\n",
 		    rv == ETIMEDOUT ? "timeout" : "error", rv);
 		goto free_scratch;
+	}
 	if (ixl_queue_pairs_alloc(sc) != 0) {
 		/* error printed by ixl_queue_pairs_alloc */
 		goto free_scratch;
+	}
 	if (ixl_setup_interrupts(sc) != 0) {
 		/* error printed by ixl_setup_interrupts */
 		goto free_queue_pairs;
+	}
 	if (ixl_setup_stats(sc) != 0) {
 		aprint_error_dev(self, "failed to setup event counters\n");
 		goto teardown_intrs;
+	}
 	if (ixl_setup_sysctls(sc) != 0) {
 		/* error printed by ixl_setup_sysctls */
 		goto teardown_stats;
+	}
 	snprintf(xnamebuf, sizeof(xnamebuf), "%s_wq_cfg", device_xname(self));
 	sc->sc_workq = ixl_workq_create(xnamebuf, IXL_WORKQUEUE_PRI,
 	    IPL_NET, WQ_MPSAFE);
 	if (sc->sc_workq == NULL)
 		goto teardown_sysctls;
 	snprintf(xnamebuf, sizeof(xnamebuf), "%s_wq_txrx", device_xname(self));
 	rv = workqueue_create(&sc->sc_workq_txrx, xnamebuf, ixl_handle_queue_wk,
 	    sc, IXL_WORKQUEUE_PRI, IPL_NET, WQ_PERCPU | WQ_MPSAFE);
 	if (rv != 0) {
 		sc->sc_workq_txrx = NULL;
 		goto teardown_wqs;
+	}
 	snprintf(xnamebuf, sizeof(xnamebuf), "%s_atq_cv", device_xname(self));
 	cv_init(&sc->sc_atq_cv, xnamebuf);
 	strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
 	ifp->if_softc = sc;
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	ifp->if_extflags = IFEF_MPSAFE;
 	ifp->if_ioctl = ixl_ioctl;
 	ifp->if_start = ixl_start;
 	ifp->if_transmit = ixl_transmit;
 	ifp->if_watchdog = ixl_watchdog;
 	ifp->if_init = ixl_init;
 	ifp->if_stop = ixl_stop;
 	IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_tx_ring_ndescs);
 	IFQ_SET_READY(&ifp->if_snd);
 	ifp->if_capabilities |= IXL_IFCAP_RXCSUM;
 	ifp->if_capabilities |= IXL_IFCAP_TXCSUM;
 #if 0
 	ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6;
 #endif
 	ether_set_vlan_cb(&sc->sc_ec, ixl_vlan_cb);
 	sc->sc_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU;
 	sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING;
 	sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWFILTER;
 	sc->sc_ec.ec_capenable = sc->sc_ec.ec_capabilities;
 	/* Disable VLAN_HWFILTER by default */
 	CLR(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER);
 	sc->sc_cur_ec_capenable = sc->sc_ec.ec_capenable;
 	sc->sc_ec.ec_ifmedia = &sc->sc_media;
 	ifmedia_init_with_lock(&sc->sc_media, IFM_IMASK, ixl_media_change,
 	    ixl_media_status, &sc->sc_cfg_lock);
 	ixl_media_add(sc);
 	ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
 	if (ISSET(sc->sc_phy_abilities,
 	    (IXL_PHY_ABILITY_PAUSE_TX | IXL_PHY_ABILITY_PAUSE_RX))) {
 		ifmedia_add(&sc->sc_media,
 		    IFM_ETHER | IFM_AUTO | IFM_FLOW, 0, NULL);
+	}
 	ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_NONE, 0, NULL);
 	ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO);
 	if_attach(ifp);
 	if_deferred_start_init(ifp, NULL);
 	ether_ifattach(ifp, sc->sc_enaddr);
 	ether_set_ifflags_cb(&sc->sc_ec, ixl_ifflags_cb);
 	rv = ixl_get_link_status_poll(sc, &link);
 	if (rv != 0)
 		link = LINK_STATE_UNKNOWN;
 	if_link_state_change(ifp, link);
 	ixl_atq_set(&sc->sc_link_state_atq, ixl_get_link_status_done);
 	ixl_work_set(&sc->sc_link_state_task, ixl_get_link_status, sc);
 	ixl_config_other_intr(sc);
 	ixl_enable_other_intr(sc);
 	ixl_set_phy_autoselect(sc);
 	/* remove default mac filter and replace it so we can see vlans */
 	rv = ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 0);
 	if (rv != ENOENT) {
 		aprint_debug_dev(self,
 		    "unable to remove macvlan %u\n", rv);
+	}
 	rv = ixl_remove_macvlan(sc, sc->sc_enaddr, 0,
 	    IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN);
 	if (rv != ENOENT) {
 		aprint_debug_dev(self,
 		    "unable to remove macvlan, ignore vlan %u\n", rv);
+	}
 	if (ixl_update_macvlan(sc) != 0) {
 		aprint_debug_dev(self,
 		    "couldn't enable vlan hardware filter\n");
 		CLR(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER);
 		CLR(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER);
+	}
 	sc->sc_txrx_workqueue = true;
 	sc->sc_tx_process_limit = IXL_TX_PROCESS_LIMIT;
 	sc->sc_rx_process_limit = IXL_RX_PROCESS_LIMIT;
 	sc->sc_tx_intr_process_limit = IXL_TX_INTR_PROCESS_LIMIT;
 	sc->sc_rx_intr_process_limit = IXL_RX_INTR_PROCESS_LIMIT;
 	ixl_stats_update(sc);
 	sc->sc_stats_counters.isc_has_offset = true;
 	if (pmf_device_register(self, NULL, NULL) != true)
 		aprint_debug_dev(self, "couldn't establish power handler\n");
 	sc->sc_itr_rx = IXL_ITR_RX;
 	sc->sc_itr_tx = IXL_ITR_TX;
 	sc->sc_attached = true;
 	return;
 teardown_wqs:
 	config_finalize_register(self, ixl_workqs_teardown);
 teardown_sysctls:
 	ixl_teardown_sysctls(sc);
 teardown_stats:
 	ixl_teardown_stats(sc);
 teardown_intrs:
 	ixl_teardown_interrupts(sc);
 free_queue_pairs:
 	ixl_queue_pairs_free(sc);
 free_scratch:
 	ixl_dmamem_free(sc, &sc->sc_scratch);
 free_hmc:
 	ixl_hmc_free(sc);
 free_aqbuf:
 	ixl_dmamem_free(sc, &sc->sc_aqbuf);
 shutdown:
 	ixl_wr(sc, sc->sc_aq_regs->atq_head, 0);
 	ixl_wr(sc, sc->sc_aq_regs->arq_head, 0);
 	ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0);
 	ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0);
 	ixl_wr(sc, sc->sc_aq_regs->atq_bal, 0);
 	ixl_wr(sc, sc->sc_aq_regs->atq_bah, 0);
 	ixl_wr(sc, sc->sc_aq_regs->atq_len, 0);
 	ixl_wr(sc, sc->sc_aq_regs->arq_bal, 0);
 	ixl_wr(sc, sc->sc_aq_regs->arq_bah, 0);
 	ixl_wr(sc, sc->sc_aq_regs->arq_len, 0);
 	bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq),
 , IXL_DMA_LEN(&sc->sc_arq),
 	    BUS_DMASYNC_POSTREAD);
 	bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq),
 , IXL_DMA_LEN(&sc->sc_atq),
 	    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 	ixl_arq_unfill(sc);
 free_arq:
 	ixl_dmamem_free(sc, &sc->sc_arq);
 free_atq:
 	ixl_dmamem_free(sc, &sc->sc_atq);
 unmap:
 	mutex_destroy(&sc->sc_atq_lock);
 	bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems);
 	mutex_destroy(&sc->sc_cfg_lock);
 	sc->sc_mems = 0;
 	sc->sc_attached = false;
+}
 static int
 ixl_detach(device_t self, int flags)
+{
 	struct ixl_softc *sc = device_private(self);
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	if (!sc->sc_attached)
 		return 0;
 	ixl_stop(ifp, 1);
 	ixl_disable_other_intr(sc);
 	callout_halt(&sc->sc_stats_callout, NULL);
 	ixl_work_wait(sc->sc_workq, &sc->sc_stats_task);
 	/* wait for ATQ handler */
 	mutex_enter(&sc->sc_atq_lock);
 	mutex_exit(&sc->sc_atq_lock);
 	ixl_work_wait(sc->sc_workq, &sc->sc_arq_task);
 	ixl_work_wait(sc->sc_workq, &sc->sc_link_state_task);
 	if (sc->sc_workq != NULL) {
 		ixl_workq_destroy(sc->sc_workq);
 		sc->sc_workq = NULL;
+	}
 	if (sc->sc_workq_txrx != NULL) {
 		workqueue_destroy(sc->sc_workq_txrx);
 		sc->sc_workq_txrx = NULL;
+	}
 	ether_ifdetach(ifp);
 	if_detach(ifp);
 	ifmedia_fini(&sc->sc_media);
 	ixl_teardown_interrupts(sc);
 	ixl_teardown_stats(sc);
 	ixl_teardown_sysctls(sc);
 	ixl_queue_pairs_free(sc);
 	ixl_dmamem_free(sc, &sc->sc_scratch);
 	ixl_hmc_free(sc);
 	/* shutdown */
 	ixl_wr(sc, sc->sc_aq_regs->atq_head, 0);
 	ixl_wr(sc, sc->sc_aq_regs->arq_head, 0);
 	ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0);
 	ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0);
 	ixl_wr(sc, sc->sc_aq_regs->atq_bal, 0);
 	ixl_wr(sc, sc->sc_aq_regs->atq_bah, 0);
 	ixl_wr(sc, sc->sc_aq_regs->atq_len, 0);
 	ixl_wr(sc, sc->sc_aq_regs->arq_bal, 0);
 	ixl_wr(sc, sc->sc_aq_regs->arq_bah, 0);
 	ixl_wr(sc, sc->sc_aq_regs->arq_len, 0);
 	bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq),
 , IXL_DMA_LEN(&sc->sc_arq),
 	    BUS_DMASYNC_POSTREAD);
 	bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq),
 , IXL_DMA_LEN(&sc->sc_atq),
 	    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 	ixl_arq_unfill(sc);
 	ixl_dmamem_free(sc, &sc->sc_arq);
 	ixl_dmamem_free(sc, &sc->sc_atq);
 	ixl_dmamem_free(sc, &sc->sc_aqbuf);
 	cv_destroy(&sc->sc_atq_cv);
 	mutex_destroy(&sc->sc_atq_lock);
 	if (sc->sc_mems != 0) {
 		bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems);
 		sc->sc_mems = 0;
+	}
 	mutex_destroy(&sc->sc_cfg_lock);
 	return 0;
+}
 static int
 ixl_workqs_teardown(device_t self)
+{
 	struct ixl_softc *sc = device_private(self);
 	if (sc->sc_workq != NULL) {
 		ixl_workq_destroy(sc->sc_workq);
 		sc->sc_workq = NULL;
+	}
 	if (sc->sc_workq_txrx != NULL) {
 		workqueue_destroy(sc->sc_workq_txrx);
 		sc->sc_workq_txrx = NULL;
+	}
 	return 0;
+}
 static int
 ixl_vlan_cb(struct ethercom *ec, uint16_t vid, bool set)
+{
 	struct ifnet *ifp = &ec->ec_if;
 	struct ixl_softc *sc = ifp->if_softc;
 	int rv;
 	if (!ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER)) {
 		return 0;
+	}
 	if (set) {
 		rv = ixl_add_macvlan(sc, sc->sc_enaddr, vid,
 		    IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH);
 		if (rv == 0) {
 			rv = ixl_add_macvlan(sc, etherbroadcastaddr,
 			    vid, IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH);
+		}
 	} else {
 		rv = ixl_remove_macvlan(sc, sc->sc_enaddr, vid,
 		    IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH);
 		(void)ixl_remove_macvlan(sc, etherbroadcastaddr, vid,
 		    IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH);
+	}
 	return rv;
+}
 static void
 ixl_media_add(struct ixl_softc *sc)
+{
 	struct ifmedia *ifm = &sc->sc_media;
 	const struct ixl_phy_type *itype;
 	unsigned int i;
 	bool flow;
 	if (ISSET(sc->sc_phy_abilities,
 	    (IXL_PHY_ABILITY_PAUSE_TX | IXL_PHY_ABILITY_PAUSE_RX))) {
 		flow = true;
 	} else {
 		flow = false;
+	}
 	for (i = 0; i < __arraycount(ixl_phy_type_map); i++) {
 		itype = &ixl_phy_type_map[i];
 		if (ISSET(sc->sc_phy_types, itype->phy_type)) {
 			ifmedia_add(ifm,
 			    IFM_ETHER | IFM_FDX | itype->ifm_type, 0, NULL);
 			if (flow) {
 				ifmedia_add(ifm,
 				    IFM_ETHER | IFM_FDX | IFM_FLOW |
 				    itype->ifm_type, 0, NULL);
+			}
 			if (itype->ifm_type != IFM_100_TX)
 				continue;
 			ifmedia_add(ifm, IFM_ETHER | itype->ifm_type,
 , NULL);
 			if (flow) {
 				ifmedia_add(ifm,
 				    IFM_ETHER | IFM_FLOW | itype->ifm_type,
 , NULL);
+			}
+		}
+	}
+}
 static void
 ixl_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
 	struct ixl_softc *sc = ifp->if_softc;
 	KASSERT(mutex_owned(&sc->sc_cfg_lock));
 	ifmr->ifm_status = sc->sc_media_status;
 	ifmr->ifm_active = sc->sc_media_active;
+}
 static int
 ixl_media_change(struct ifnet *ifp)
+{
 	struct ixl_softc *sc = ifp->if_softc;
 	struct ifmedia *ifm = &sc->sc_media;
 	uint64_t ifm_active = sc->sc_media_active;
 	uint8_t link_speed, abilities;
 	switch (IFM_SUBTYPE(ifm_active)) {
 	case IFM_1000_SGMII:
 	case IFM_1000_KX:
 	case IFM_10G_KX4:
 	case IFM_10G_KR:
 	case IFM_40G_KR4:
 	case IFM_20G_KR2:
 	case IFM_25G_KR:
 		/* backplanes */
 		return EINVAL;
+	}
 	abilities = IXL_PHY_ABILITY_AUTONEGO | IXL_PHY_ABILITY_LINKUP;
 	switch (IFM_SUBTYPE(ifm->ifm_media)) {
 	case IFM_AUTO:
 		link_speed = sc->sc_phy_linkspeed;
 		break;
 	case IFM_NONE:
 		link_speed = 0;
 		CLR(abilities, IXL_PHY_ABILITY_LINKUP);
 		break;
 	default:
 		link_speed = ixl_search_baudrate(
 		    ifmedia_baudrate(ifm->ifm_media));
+	}
 	if (ISSET(abilities, IXL_PHY_ABILITY_LINKUP)) {
 		if (ISSET(link_speed, sc->sc_phy_linkspeed) == 0)
 			return EINVAL;
+	}
 	if (ifm->ifm_media & IFM_FLOW) {
 		abilities |= sc->sc_phy_abilities &
 		    (IXL_PHY_ABILITY_PAUSE_TX | IXL_PHY_ABILITY_PAUSE_RX);
+	}
 	return ixl_set_phy_config(sc, link_speed, abilities, false);
+}
 static void
 ixl_watchdog(struct ifnet *ifp)
+{
+}
 static void
 ixl_del_all_multiaddr(struct ixl_softc *sc)
+{
 	struct ethercom *ec = &sc->sc_ec;
 	struct ether_multi *enm;
 	struct ether_multistep step;
 	ETHER_LOCK(ec);
 	for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL;
 	    ETHER_NEXT_MULTI(step, enm)) {
 		ixl_remove_macvlan(sc, enm->enm_addrlo, 0,
 		    IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN);
+	}
 	ETHER_UNLOCK(ec);
+}
 static int
 ixl_add_multi(struct ixl_softc *sc, uint8_t *addrlo, uint8_t *addrhi)
+{
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	int rv;
 	if (ISSET(ifp->if_flags, IFF_ALLMULTI))
 		return 0;
 	if (memcmp(addrlo, addrhi, ETHER_ADDR_LEN) != 0) {
 		ixl_del_all_multiaddr(sc);
 		SET(ifp->if_flags, IFF_ALLMULTI);
 		return ENETRESET;
+	}
 	/* multicast address can not use VLAN HWFILTER */
 	rv = ixl_add_macvlan(sc, addrlo, 0,
 	    IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN);
 	if (rv == ENOSPC) {
 		ixl_del_all_multiaddr(sc);
 		SET(ifp->if_flags, IFF_ALLMULTI);
 		return ENETRESET;
+	}
 	return rv;
+}
 static int
 ixl_del_multi(struct ixl_softc *sc, uint8_t *addrlo, uint8_t *addrhi)
+{
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	struct ethercom *ec = &sc->sc_ec;
 	struct ether_multi *enm, *enm_last;
 	struct ether_multistep step;
 	int error, rv = 0;
 	if (!ISSET(ifp->if_flags, IFF_ALLMULTI)) {
 		ixl_remove_macvlan(sc, addrlo, 0,
 		    IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN);
 		return 0;
+	}
 	ETHER_LOCK(ec);
 	for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL;
 	    ETHER_NEXT_MULTI(step, enm)) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
 		    ETHER_ADDR_LEN) != 0) {
 			goto out;
+		}
+	}
 	for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL;
 	    ETHER_NEXT_MULTI(step, enm)) {
 		error = ixl_add_macvlan(sc, enm->enm_addrlo, 0,
 		    IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN);
 		if (error != 0)
 			break;
+	}
 	if (enm != NULL) {
 		enm_last = enm;
 		for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL;
 		    ETHER_NEXT_MULTI(step, enm)) {
 			if (enm == enm_last)
 				break;
 			ixl_remove_macvlan(sc, enm->enm_addrlo, 0,
 			    IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN);
+		}
 	} else {
 		CLR(ifp->if_flags, IFF_ALLMULTI);
 		rv = ENETRESET;
+	}
 out:
 	ETHER_UNLOCK(ec);
 	return rv;
+}
 static int
 ixl_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
 	struct ifreq *ifr = (struct ifreq *)data;
 	struct ixl_softc *sc = (struct ixl_softc *)ifp->if_softc;
 	const struct sockaddr *sa;
 	uint8_t addrhi[ETHER_ADDR_LEN], addrlo[ETHER_ADDR_LEN];
 	int s, error = 0;
 	unsigned int nmtu;
 	switch (cmd) {
 	case SIOCSIFMTU:
 		nmtu = ifr->ifr_mtu;
 		if (nmtu < IXL_MIN_MTU || nmtu > IXL_MAX_MTU) {
 			error = EINVAL;
 			break;
+		}
 		if (ifp->if_mtu != nmtu) {
 			s = splnet();
 			error = ether_ioctl(ifp, cmd, data);
 			splx(s);
 			if (error == ENETRESET)
 				error = ixl_init(ifp);
+		}
 		break;
 	case SIOCADDMULTI:
 		sa = ifreq_getaddr(SIOCADDMULTI, ifr);
 		if (ether_addmulti(sa, &sc->sc_ec) == ENETRESET) {
 			error = ether_multiaddr(sa, addrlo, addrhi);
 			if (error != 0)
 				return error;
 			error = ixl_add_multi(sc, addrlo, addrhi);
 			if (error != 0 && error != ENETRESET) {
 				ether_delmulti(sa, &sc->sc_ec);
 				error = EIO;
+			}
+		}
 		break;
 	case SIOCDELMULTI:
 		sa = ifreq_getaddr(SIOCDELMULTI, ifr);
 		if (ether_delmulti(sa, &sc->sc_ec) == ENETRESET) {
 			error = ether_multiaddr(sa, addrlo, addrhi);
 			if (error != 0)
 				return error;
 			error = ixl_del_multi(sc, addrlo, addrhi);
+		}
 		break;
 	default:
 		s = splnet();
 		error = ether_ioctl(ifp, cmd, data);
 		splx(s);
+	}
 	if (error == ENETRESET)
 		error = ixl_iff(sc);
 	return error;
+}
 static enum i40e_mac_type
 ixl_mactype(pci_product_id_t id)
+{
 	switch (id) {
 	case PCI_PRODUCT_INTEL_XL710_SFP:
 	case PCI_PRODUCT_INTEL_XL710_KX_B:
 	case PCI_PRODUCT_INTEL_XL710_KX_C:
 	case PCI_PRODUCT_INTEL_XL710_QSFP_A:
 	case PCI_PRODUCT_INTEL_XL710_QSFP_B:
 	case PCI_PRODUCT_INTEL_XL710_QSFP_C:
 	case PCI_PRODUCT_INTEL_X710_10G_T:
 	case PCI_PRODUCT_INTEL_XL710_20G_BP_1:
 	case PCI_PRODUCT_INTEL_XL710_20G_BP_2:
 	case PCI_PRODUCT_INTEL_X710_T4_10G:
 	case PCI_PRODUCT_INTEL_XXV710_25G_BP:
 	case PCI_PRODUCT_INTEL_XXV710_25G_SFP28:
 		return I40E_MAC_XL710;
 	case PCI_PRODUCT_INTEL_X722_KX:
 	case PCI_PRODUCT_INTEL_X722_QSFP:
 	case PCI_PRODUCT_INTEL_X722_SFP:
 	case PCI_PRODUCT_INTEL_X722_1G_BASET:
 	case PCI_PRODUCT_INTEL_X722_10G_BASET:
 	case PCI_PRODUCT_INTEL_X722_I_SFP:
 		return I40E_MAC_X722;
+	}
 	return I40E_MAC_GENERIC;
+}
 static void
 ixl_pci_csr_setup(pci_chipset_tag_t pc, pcitag_t tag)
+{
 	pcireg_t csr;
 	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
 	csr |= (PCI_COMMAND_MASTER_ENABLE |
 	    PCI_COMMAND_MEM_ENABLE);
 	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
+}
 static inline void *
 ixl_hmc_kva(struct ixl_softc *sc, enum ixl_hmc_types type, unsigned int i)
+{
 	uint8_t *kva = IXL_DMA_KVA(&sc->sc_hmc_pd);
 	struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type];
 	if (i >= e->hmc_count)
 		return NULL;
 	kva += e->hmc_base;
 	kva += i * e->hmc_size;
 	return kva;
+}
 static inline size_t
 ixl_hmc_len(struct ixl_softc *sc, enum ixl_hmc_types type)
+{
 	struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type];
 	return e->hmc_size;
+}
 static void
 ixl_enable_queue_intr(struct ixl_softc *sc, struct ixl_queue_pair *qp)
+{
 	struct ixl_rx_ring *rxr = qp->qp_rxr;
 	ixl_wr(sc, I40E_PFINT_DYN_CTLN(rxr->rxr_qid),
 	    I40E_PFINT_DYN_CTLN_INTENA_MASK |
 	    I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 	    (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT));
 	ixl_flush(sc);
+}
 static void
 ixl_disable_queue_intr(struct ixl_softc *sc, struct ixl_queue_pair *qp)
+{
 	struct ixl_rx_ring *rxr = qp->qp_rxr;
 	ixl_wr(sc, I40E_PFINT_DYN_CTLN(rxr->rxr_qid),
 	    (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT));
 	ixl_flush(sc);
+}
 static void
 ixl_enable_other_intr(struct ixl_softc *sc)
+{
 	ixl_wr(sc, I40E_PFINT_DYN_CTL0,
 	    I40E_PFINT_DYN_CTL0_INTENA_MASK |
 	    I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
 	    (IXL_NOITR << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT));
 	ixl_flush(sc);
+}
 static void
 ixl_disable_other_intr(struct ixl_softc *sc)
+{
 	ixl_wr(sc, I40E_PFINT_DYN_CTL0,
 	    (IXL_NOITR << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT));
 	ixl_flush(sc);
+}
 static int
 ixl_reinit(struct ixl_softc *sc)
+{
 	struct ixl_rx_ring *rxr;
 	struct ixl_tx_ring *txr;
 	unsigned int i;
 	uint32_t reg;
 	KASSERT(mutex_owned(&sc->sc_cfg_lock));
 	if (ixl_get_vsi(sc) != 0)
 		return EIO;
 	if (ixl_set_vsi(sc) != 0)
 		return EIO;
 	for (i = 0; i < sc->sc_nqueue_pairs; i++) {
 		txr = sc->sc_qps[i].qp_txr;
 		rxr = sc->sc_qps[i].qp_rxr;
 		ixl_txr_config(sc, txr);
 		ixl_rxr_config(sc, rxr);
+	}
 	bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd),
 , IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_PREWRITE);
 	for (i = 0; i < sc->sc_nqueue_pairs; i++) {
 		txr = sc->sc_qps[i].qp_txr;
 		rxr = sc->sc_qps[i].qp_rxr;
 		ixl_wr(sc, I40E_QTX_CTL(i), I40E_QTX_CTL_PF_QUEUE |
 		    (sc->sc_pf_id << I40E_QTX_CTL_PF_INDX_SHIFT));
 		ixl_flush(sc);
 		ixl_wr(sc, txr->txr_tail, txr->txr_prod);
 		ixl_wr(sc, rxr->rxr_tail, rxr->rxr_prod);
 		/* ixl_rxfill() needs lock held */
 		mutex_enter(&rxr->rxr_lock);
 		ixl_rxfill(sc, rxr);
 		mutex_exit(&rxr->rxr_lock);
 		reg = ixl_rd(sc, I40E_QRX_ENA(i));
 		SET(reg, I40E_QRX_ENA_QENA_REQ_MASK);
 		ixl_wr(sc, I40E_QRX_ENA(i), reg);
 		if (ixl_rxr_enabled(sc, rxr) != 0)
 			goto stop;
 		ixl_txr_qdis(sc, txr, 1);
 		reg = ixl_rd(sc, I40E_QTX_ENA(i));
 		SET(reg, I40E_QTX_ENA_QENA_REQ_MASK);
 		ixl_wr(sc, I40E_QTX_ENA(i), reg);
 		if (ixl_txr_enabled(sc, txr) != 0)
 			goto stop;
+	}
 	bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd),
 , IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_POSTWRITE);
 	return 0;
 stop:
 	bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd),
 , IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_POSTWRITE);
 	return ETIMEDOUT;
+}
 static int
 ixl_init_locked(struct ixl_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	unsigned int i;
 	int error, eccap_change;
 	KASSERT(mutex_owned(&sc->sc_cfg_lock));
 	if (ISSET(ifp->if_flags, IFF_RUNNING))
 		ixl_stop_locked(sc);
 	if (sc->sc_dead) {
 		return ENXIO;
+	}
 	eccap_change = sc->sc_ec.ec_capenable ^ sc->sc_cur_ec_capenable;
 	if (ISSET(eccap_change, ETHERCAP_VLAN_HWTAGGING))
 		sc->sc_cur_ec_capenable ^= ETHERCAP_VLAN_HWTAGGING;
 	if (ISSET(eccap_change, ETHERCAP_VLAN_HWFILTER)) {
 		if (ixl_update_macvlan(sc) == 0) {
 			sc->sc_cur_ec_capenable ^= ETHERCAP_VLAN_HWFILTER;
 		} else {
 			CLR(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER);
 			CLR(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER);
+		}
+	}
 	if (sc->sc_intrtype != PCI_INTR_TYPE_MSIX)
 		sc->sc_nqueue_pairs = 1;
 	else
 		sc->sc_nqueue_pairs = sc->sc_nqueue_pairs_max;
 	error = ixl_reinit(sc);
 	if (error) {
 		ixl_stop_locked(sc);
 		return error;
+	}
 	SET(ifp->if_flags, IFF_RUNNING);
 	CLR(ifp->if_flags, IFF_OACTIVE);
 	ixl_config_rss(sc);
 	ixl_config_queue_intr(sc);
 	for (i = 0; i < sc->sc_nqueue_pairs; i++) {
 		ixl_enable_queue_intr(sc, &sc->sc_qps[i]);
+	}
 	error = ixl_iff(sc);
 	if (error) {
 		ixl_stop_locked(sc);
 		return error;
+	}
 	callout_schedule(&sc->sc_stats_callout, mstohz(sc->sc_stats_intval));
 	return 0;
+}
 static int
 ixl_init(struct ifnet *ifp)
+{
 	struct ixl_softc *sc = ifp->if_softc;
 	int error;
 	mutex_enter(&sc->sc_cfg_lock);
 	error = ixl_init_locked(sc);
 	mutex_exit(&sc->sc_cfg_lock);
 	if (error == 0)
 		(void)ixl_get_link_status(sc);
 	return error;
+}
 static int
 ixl_iff(struct ixl_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	struct ixl_atq iatq;
 	struct ixl_aq_desc *iaq;
 	struct ixl_aq_vsi_promisc_param *param;
 	uint16_t flag_add, flag_del;
 	int error;
 	if (!ISSET(ifp->if_flags, IFF_RUNNING))
 		return 0;
 	memset(&iatq, 0, sizeof(iatq));
 	iaq = &iatq.iatq_desc;
 	iaq->iaq_opcode = htole16(IXL_AQ_OP_SET_VSI_PROMISC);
 	param = (struct ixl_aq_vsi_promisc_param *)&iaq->iaq_param;
 	param->flags = htole16(0);
 	if (!ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER)
 	    || ISSET(ifp->if_flags, IFF_PROMISC)) {
 		param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_BCAST |
 		    IXL_AQ_VSI_PROMISC_FLAG_VLAN);
+	}
 	if (ISSET(ifp->if_flags, IFF_PROMISC)) {
 		param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST |
 		    IXL_AQ_VSI_PROMISC_FLAG_MCAST);
 	} else if (ISSET(ifp->if_flags, IFF_ALLMULTI)) {
 		param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_MCAST);
+	}
 	param->valid_flags = htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST |
 	    IXL_AQ_VSI_PROMISC_FLAG_MCAST | IXL_AQ_VSI_PROMISC_FLAG_BCAST |
 	    IXL_AQ_VSI_PROMISC_FLAG_VLAN);
 	param->seid = sc->sc_seid;
 	error = ixl_atq_exec(sc, &iatq);
 	if (error)
 		return error;
 	if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK))
 		return EIO;
 	if (memcmp(sc->sc_enaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN) != 0) {
 		if (ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER)) {
 			flag_add = IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH;
 			flag_del = IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH;
 		} else {
 			flag_add = IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN;
 			flag_del = IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN;
+		}
 		ixl_remove_macvlan(sc, sc->sc_enaddr, 0, flag_del);
 		memcpy(sc->sc_enaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN);
 		ixl_add_macvlan(sc, sc->sc_enaddr, 0, flag_add);
+	}
 	return 0;
+}
 static void
 ixl_stop_rendezvous(struct ixl_softc *sc)
+{
 	struct ixl_tx_ring *txr;
 	struct ixl_rx_ring *rxr;
 	unsigned int i;
 	for (i = 0; i < sc->sc_nqueue_pairs; i++) {
 		txr = sc->sc_qps[i].qp_txr;
 		rxr = sc->sc_qps[i].qp_rxr;
 		mutex_enter(&txr->txr_lock);
 		mutex_exit(&txr->txr_lock);
 		mutex_enter(&rxr->rxr_lock);
 		mutex_exit(&rxr->rxr_lock);
 		sc->sc_qps[i].qp_workqueue = false;
 		workqueue_wait(sc->sc_workq_txrx,
 		    &sc->sc_qps[i].qp_work);
+	}
+}
 static void
 ixl_stop_locked(struct ixl_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	struct ixl_rx_ring *rxr;
 	struct ixl_tx_ring *txr;
 	unsigned int i;
 	uint32_t reg;
 	KASSERT(mutex_owned(&sc->sc_cfg_lock));
 	CLR(ifp->if_flags, IFF_RUNNING | IFF_OACTIVE);
 	callout_stop(&sc->sc_stats_callout);
 	for (i = 0; i < sc->sc_nqueue_pairs; i++) {
 		txr = sc->sc_qps[i].qp_txr;
 		rxr = sc->sc_qps[i].qp_rxr;
 		ixl_disable_queue_intr(sc, &sc->sc_qps[i]);
 		mutex_enter(&txr->txr_lock);
 		ixl_txr_qdis(sc, txr, 0);
 		mutex_exit(&txr->txr_lock);
+	}
 	/* XXX wait at least 400 usec for all tx queues in one go */
 	ixl_flush(sc);
 	DELAY(500);
 	for (i = 0; i < sc->sc_nqueue_pairs; i++) {
 		txr = sc->sc_qps[i].qp_txr;
 		rxr = sc->sc_qps[i].qp_rxr;
 		mutex_enter(&txr->txr_lock);
 		reg = ixl_rd(sc, I40E_QTX_ENA(i));
 		CLR(reg, I40E_QTX_ENA_QENA_REQ_MASK);
 		ixl_wr(sc, I40E_QTX_ENA(i), reg);
 		mutex_exit(&txr->txr_lock);
 		mutex_enter(&rxr->rxr_lock);
 		reg = ixl_rd(sc, I40E_QRX_ENA(i));
 		CLR(reg, I40E_QRX_ENA_QENA_REQ_MASK);
 		ixl_wr(sc, I40E_QRX_ENA(i), reg);
 		mutex_exit(&rxr->rxr_lock);
+	}
 	/* XXX short wait for all queue disables to settle */
 	ixl_flush(sc);
 	DELAY(50);
 	for (i = 0; i < sc->sc_nqueue_pairs; i++) {
 		txr = sc->sc_qps[i].qp_txr;
 		rxr = sc->sc_qps[i].qp_rxr;
 		mutex_enter(&txr->txr_lock);
 		if (ixl_txr_disabled(sc, txr) != 0) {
 			mutex_exit(&txr->txr_lock);
 			goto die;
+		}
 		mutex_exit(&txr->txr_lock);
 		mutex_enter(&rxr->rxr_lock);
 		if (ixl_rxr_disabled(sc, rxr) != 0) {
 			mutex_exit(&rxr->rxr_lock);
 			goto die;
+		}
 		mutex_exit(&rxr->rxr_lock);
+	}
 	ixl_stop_rendezvous(sc);
 	for (i = 0; i < sc->sc_nqueue_pairs; i++) {
 		txr = sc->sc_qps[i].qp_txr;
 		rxr = sc->sc_qps[i].qp_rxr;
 		mutex_enter(&txr->txr_lock);
 		ixl_txr_unconfig(sc, txr);
 		mutex_exit(&txr->txr_lock);
 		mutex_enter(&rxr->rxr_lock);
 		ixl_rxr_unconfig(sc, rxr);
 		mutex_exit(&rxr->rxr_lock);
 		ixl_txr_clean(sc, txr);
 		ixl_rxr_clean(sc, rxr);
+	}
 	return;
 die:
 	sc->sc_dead = true;
 	log(LOG_CRIT, "%s: failed to shut down rings",
 	    device_xname(sc->sc_dev));
 	return;
+}
 static void
 ixl_stop(struct ifnet *ifp, int disable)
+{
 	struct ixl_softc *sc = ifp->if_softc;
 	mutex_enter(&sc->sc_cfg_lock);
 	ixl_stop_locked(sc);
 	mutex_exit(&sc->sc_cfg_lock);
+}
 static int
 ixl_queue_pairs_alloc(struct ixl_softc *sc)
+{
 	struct ixl_queue_pair *qp;
 	unsigned int i;
 	size_t sz;
 	sz = sizeof(sc->sc_qps[0]) * sc->sc_nqueue_pairs_max;
 	sc->sc_qps = kmem_zalloc(sz, KM_SLEEP);
 	for (i = 0; i < sc->sc_nqueue_pairs_max; i++) {
 		qp = &sc->sc_qps[i];
 		qp->qp_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
 		    ixl_handle_queue, qp);
 		if (qp->qp_si == NULL)
 			goto free;
 		qp->qp_txr = ixl_txr_alloc(sc, i);
 		if (qp->qp_txr == NULL)
 			goto free;
 		qp->qp_rxr = ixl_rxr_alloc(sc, i);
 		if (qp->qp_rxr == NULL)
 			goto free;
 		qp->qp_sc = sc;
 		snprintf(qp->qp_name, sizeof(qp->qp_name),
 		    "%s-TXRX%d", device_xname(sc->sc_dev), i);
+	}
 	return 0;
 free:
 	if (sc->sc_qps != NULL) {
 		for (i = 0; i < sc->sc_nqueue_pairs_max; i++) {
 			qp = &sc->sc_qps[i];
 			if (qp->qp_txr != NULL)
 				ixl_txr_free(sc, qp->qp_txr);
 			if (qp->qp_rxr != NULL)
 				ixl_rxr_free(sc, qp->qp_rxr);
 			if (qp->qp_si != NULL)
 				softint_disestablish(qp->qp_si);
+		}
 		sz = sizeof(sc->sc_qps[0]) * sc->sc_nqueue_pairs_max;
 		kmem_free(sc->sc_qps, sz);
 		sc->sc_qps = NULL;
+	}
 	return -1;
+}
 static void
 ixl_queue_pairs_free(struct ixl_softc *sc)
+{
 	struct ixl_queue_pair *qp;
 	unsigned int i;
 	size_t sz;
 	for (i = 0; i < sc->sc_nqueue_pairs_max; i++) {
 		qp = &sc->sc_qps[i];
 		ixl_txr_free(sc, qp->qp_txr);
 		ixl_rxr_free(sc, qp->qp_rxr);
 		softint_disestablish(qp->qp_si);
+	}
 	sz = sizeof(sc->sc_qps[0]) * sc->sc_nqueue_pairs_max;
 	kmem_free(sc->sc_qps, sz);
 	sc->sc_qps = NULL;
+}
 static struct ixl_tx_ring *
 ixl_txr_alloc(struct ixl_softc *sc, unsigned int qid)
+{
 	struct ixl_tx_ring *txr = NULL;
 	struct ixl_tx_map *maps = NULL, *txm;
 	unsigned int i;
 	txr = kmem_zalloc(sizeof(*txr), KM_SLEEP);
 	maps = kmem_zalloc(sizeof(maps[0]) * sc->sc_tx_ring_ndescs,
 	    KM_SLEEP);
 	if (ixl_dmamem_alloc(sc, &txr->txr_mem,
 	    sizeof(struct ixl_tx_desc) * sc->sc_tx_ring_ndescs,
 	    IXL_TX_QUEUE_ALIGN) != 0)
 	    goto free;
 	for (i = 0; i < sc->sc_tx_ring_ndescs; i++) {
 		txm = &maps[i];
 		if (bus_dmamap_create(sc->sc_dmat, IXL_TX_PKT_MAXSIZE,
 		    IXL_TX_PKT_DESCS, IXL_TX_PKT_MAXSIZE, 0,
 		    BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &txm->txm_map) != 0)
 			goto uncreate;
 		txm->txm_eop = -1;
 		txm->txm_m = NULL;
+	}
 	txr->txr_cons = txr->txr_prod = 0;
 	txr->txr_maps = maps;
 	txr->txr_intrq = pcq_create(sc->sc_tx_ring_ndescs, KM_NOSLEEP);
 	if (txr->txr_intrq == NULL)
 		goto uncreate;
 	txr->txr_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
 	    ixl_deferred_transmit, txr);
 	if (txr->txr_si == NULL)
 		goto destroy_pcq;
 	txr->txr_tail = I40E_QTX_TAIL(qid);
 	txr->txr_qid = qid;
 	txr->txr_sc = sc;
 	mutex_init(&txr->txr_lock, MUTEX_DEFAULT, IPL_NET);
 	return txr;
 destroy_pcq:
 	pcq_destroy(txr->txr_intrq);
 uncreate:
 	for (i = 0; i < sc->sc_tx_ring_ndescs; i++) {
 		txm = &maps[i];
 		if (txm->txm_map == NULL)
 			continue;
 		bus_dmamap_destroy(sc->sc_dmat, txm->txm_map);
+	}
 	ixl_dmamem_free(sc, &txr->txr_mem);
 free:
 	kmem_free(maps, sizeof(maps[0]) * sc->sc_tx_ring_ndescs);
 	kmem_free(txr, sizeof(*txr));
 	return NULL;
+}
 static void
 ixl_txr_qdis(struct ixl_softc *sc, struct ixl_tx_ring *txr, int enable)
+{
 	unsigned int qid;
 	bus_size_t reg;
 	uint32_t r;
 	qid = txr->txr_qid + sc->sc_base_queue;
 	reg = I40E_GLLAN_TXPRE_QDIS(qid / 128);
 	qid %= 128;
 	r = ixl_rd(sc, reg);
 	CLR(r, I40E_GLLAN_TXPRE_QDIS_QINDX_MASK);
 	SET(r, qid << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
 	SET(r, enable ? I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK :
 	    I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK);
 	ixl_wr(sc, reg, r);
+}
 static void
 ixl_txr_config(struct ixl_softc *sc, struct ixl_tx_ring *txr)
+{
 	struct ixl_hmc_txq txq;
 	struct ixl_aq_vsi_data *data = IXL_DMA_KVA(&sc->sc_scratch);
 	void *hmc;
 	memset(&txq, 0, sizeof(txq));
 	txq.head = htole16(txr->txr_cons);
 	txq.new_context = 1;
 	txq.base = htole64(IXL_DMA_DVA(&txr->txr_mem) / IXL_HMC_TXQ_BASE_UNIT);
 	txq.head_wb_ena = IXL_HMC_TXQ_DESC_WB;
 	txq.qlen = htole16(sc->sc_tx_ring_ndescs);
 	txq.tphrdesc_ena = 0;
 	txq.tphrpacket_ena = 0;
 	txq.tphwdesc_ena = 0;
 	txq.rdylist = data->qs_handle[0];
 	hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid);
 	memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX));
 	ixl_hmc_pack(hmc, &txq, ixl_hmc_pack_txq,
 	    __arraycount(ixl_hmc_pack_txq));
+}
 static void
 ixl_txr_unconfig(struct ixl_softc *sc, struct ixl_tx_ring *txr)
+{
 	void *hmc;
 	hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid);
 	memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX));
 	txr->txr_cons = txr->txr_prod = 0;
+}
 static void
 ixl_txr_clean(struct ixl_softc *sc, struct ixl_tx_ring *txr)
+{
 	struct ixl_tx_map *maps, *txm;
 	bus_dmamap_t map;
 	unsigned int i;
 	maps = txr->txr_maps;
 	for (i = 0; i < sc->sc_tx_ring_ndescs; i++) {
 		txm = &maps[i];
 		if (txm->txm_m == NULL)
 			continue;
 		map = txm->txm_map;
 		bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
 		    BUS_DMASYNC_POSTWRITE);
 		bus_dmamap_unload(sc->sc_dmat, map);
 		m_freem(txm->txm_m);
 		txm->txm_m = NULL;
+	}
+}
 static int
 ixl_txr_enabled(struct ixl_softc *sc, struct ixl_tx_ring *txr)
+{
 	bus_size_t ena = I40E_QTX_ENA(txr->txr_qid);
 	uint32_t reg;
 	int i;
 	for (i = 0; i < 10; i++) {
 		reg = ixl_rd(sc, ena);
 		if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK))
 			return 0;
 		delaymsec(10);
+	}
 	return ETIMEDOUT;
+}
 static int
 ixl_txr_disabled(struct ixl_softc *sc, struct ixl_tx_ring *txr)
+{
 	bus_size_t ena = I40E_QTX_ENA(txr->txr_qid);
 	uint32_t reg;
 	int i;
 	KASSERT(mutex_owned(&txr->txr_lock));
 	for (i = 0; i < 10; i++) {
 		reg = ixl_rd(sc, ena);
 		if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK) == 0)
 			return 0;
 		delaymsec(10);
+	}
 	return ETIMEDOUT;
+}
 static void
 ixl_txr_free(struct ixl_softc *sc, struct ixl_tx_ring *txr)
+{
 	struct ixl_tx_map *maps, *txm;
 	struct mbuf *m;
 	unsigned int i;
 	softint_disestablish(txr->txr_si);
 	while ((m = pcq_get(txr->txr_intrq)) != NULL)
 		m_freem(m);
 	pcq_destroy(txr->txr_intrq);
 	maps = txr->txr_maps;
 	for (i = 0; i < sc->sc_tx_ring_ndescs; i++) {
 		txm = &maps[i];
 		bus_dmamap_destroy(sc->sc_dmat, txm->txm_map);
+	}
 	ixl_dmamem_free(sc, &txr->txr_mem);
 	mutex_destroy(&txr->txr_lock);
 	kmem_free(maps, sizeof(maps[0]) * sc->sc_tx_ring_ndescs);
 	kmem_free(txr, sizeof(*txr));
+}
 static inline int
 ixl_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf **m0,
     struct ixl_tx_ring *txr)
+{
 	struct mbuf *m;
 	int error;
 	KASSERT(mutex_owned(&txr->txr_lock));
 	m = *m0;
 	error = bus_dmamap_load_mbuf(dmat, map, m,
 	    BUS_DMA_STREAMING | BUS_DMA_WRITE | BUS_DMA_NOWAIT);
 	if (error != EFBIG)
 		return error;
 	m = m_defrag(m, M_DONTWAIT);
 	if (m != NULL) {
 		*m0 = m;
 		txr->txr_defragged.ev_count++;
 		error = bus_dmamap_load_mbuf(dmat, map, m,
 		    BUS_DMA_STREAMING | BUS_DMA_WRITE | BUS_DMA_NOWAIT);
 	} else {
 		txr->txr_defrag_failed.ev_count++;
 		error = ENOBUFS;
+	}
 	return error;
+}
 static inline int
 ixl_tx_setup_offloads(struct mbuf *m, uint64_t *cmd_txd)
+{
 	struct ether_header *eh;
 	size_t len;
 	uint64_t cmd;
 	cmd = 0;
 	eh = mtod(m, struct ether_header *);
 	switch (htons(eh->ether_type)) {
 	case ETHERTYPE_IP:
 	case ETHERTYPE_IPV6:
 		len = ETHER_HDR_LEN;
 		break;
 	case ETHERTYPE_VLAN:
 		len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
 		break;
 	default:
 		len = 0;
+	}
 	cmd |= ((len >> 1) << IXL_TX_DESC_MACLEN_SHIFT);
 	if (m->m_pkthdr.csum_flags &
 	    (M_CSUM_TSOv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) {
 		cmd |= IXL_TX_DESC_CMD_IIPT_IPV4;
+	}
 	if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) {
 		cmd |= IXL_TX_DESC_CMD_IIPT_IPV4_CSUM;
+	}
 	if (m->m_pkthdr.csum_flags &
 	    (M_CSUM_TSOv6 | M_CSUM_TCPv6 | M_CSUM_UDPv6)) {
 		cmd |= IXL_TX_DESC_CMD_IIPT_IPV6;
+	}
 	switch (cmd & IXL_TX_DESC_CMD_IIPT_MASK) {
 	case IXL_TX_DESC_CMD_IIPT_IPV4:
 	case IXL_TX_DESC_CMD_IIPT_IPV4_CSUM:
 		len = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data);
 		break;
 	case IXL_TX_DESC_CMD_IIPT_IPV6:
 		len = M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data);
 		break;
 	default:
 		len = 0;
+	}
 	cmd |= ((len >> 2) << IXL_TX_DESC_IPLEN_SHIFT);
 	if (m->m_pkthdr.csum_flags &
 	    (M_CSUM_TSOv4 | M_CSUM_TSOv6 | M_CSUM_TCPv4 | M_CSUM_TCPv6)) {
 		len = sizeof(struct tcphdr);
 		cmd |= IXL_TX_DESC_CMD_L4T_EOFT_TCP;
 	} else if (m->m_pkthdr.csum_flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) {
 		len = sizeof(struct udphdr);
 		cmd |= IXL_TX_DESC_CMD_L4T_EOFT_UDP;
 	} else {
 		len = 0;
+	}
 	cmd |= ((len >> 2) << IXL_TX_DESC_L4LEN_SHIFT);
 	*cmd_txd |= cmd;
 	return 0;
+}
 static void
 ixl_tx_common_locked(struct ifnet *ifp, struct ixl_tx_ring *txr,
     bool is_transmit)
+{
 	struct ixl_softc *sc = ifp->if_softc;
 	struct ixl_tx_desc *ring, *txd;
 	struct ixl_tx_map *txm;
 	bus_dmamap_t map;
 	struct mbuf *m;
 	uint64_t cmd, cmd_txd;
 	unsigned int prod, free, last, i;
 	unsigned int mask;
 	int post = 0;
 	KASSERT(mutex_owned(&txr->txr_lock));
 	if (!ISSET(ifp->if_flags, IFF_RUNNING)
 	    || (!is_transmit && ISSET(ifp->if_flags, IFF_OACTIVE))) {
 		if (!is_transmit)
 			IFQ_PURGE(&ifp->if_snd);
 		return;
+	}
 	prod = txr->txr_prod;
 	free = txr->txr_cons;
 	if (free <= prod)
 		free += sc->sc_tx_ring_ndescs;
 	free -= prod;
 	bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem),
 , IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTWRITE);
 	ring = IXL_DMA_KVA(&txr->txr_mem);
 	mask = sc->sc_tx_ring_ndescs - 1;
 	last = prod;
 	cmd = 0;
 	txd = NULL;
 	for (;;) {
 		if (free <= IXL_TX_PKT_DESCS) {
 			if (!is_transmit)
 				SET(ifp->if_flags, IFF_OACTIVE);
 			break;
+		}
 		if (is_transmit)
 			m = pcq_get(txr->txr_intrq);
 		else
 			IFQ_DEQUEUE(&ifp->if_snd, m);
 		if (m == NULL)
 			break;
 		txm = &txr->txr_maps[prod];
 		map = txm->txm_map;
 		if (ixl_load_mbuf(sc->sc_dmat, map, &m, txr) != 0) {
 			if_statinc(ifp, if_oerrors);
 			m_freem(m);
 			continue;
+		}
 		cmd_txd = 0;
 		if (m->m_pkthdr.csum_flags & IXL_CSUM_ALL_OFFLOAD) {
 			ixl_tx_setup_offloads(m, &cmd_txd);
+		}
 		if (vlan_has_tag(m)) {
 			cmd_txd |= (uint64_t)vlan_get_tag(m) <<
 			    IXL_TX_DESC_L2TAG1_SHIFT;
 			cmd_txd |= IXL_TX_DESC_CMD_IL2TAG1;
+		}
 		bus_dmamap_sync(sc->sc_dmat, map, 0,
 		    map->dm_mapsize, BUS_DMASYNC_PREWRITE);
 		for (i = 0; i < (unsigned int)map->dm_nsegs; i++) {
 			txd = &ring[prod];
 			cmd = (uint64_t)map->dm_segs[i].ds_len <<
 			    IXL_TX_DESC_BSIZE_SHIFT;
 			cmd |= IXL_TX_DESC_DTYPE_DATA | IXL_TX_DESC_CMD_ICRC;
 			cmd |= cmd_txd;
 			txd->addr = htole64(map->dm_segs[i].ds_addr);
 			txd->cmd = htole64(cmd);
 			last = prod;
 			prod++;
 			prod &= mask;
+		}
 		cmd |= IXL_TX_DESC_CMD_EOP | IXL_TX_DESC_CMD_RS;
 		txd->cmd = htole64(cmd);
 		txm->txm_m = m;
 		txm->txm_eop = last;
 		bpf_mtap(ifp, m, BPF_D_OUT);
 		free -= i;
 		post = 1;
+	}
 	bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem),
 , IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREWRITE);
 	if (post) {
 		txr->txr_prod = prod;
 		ixl_wr(sc, txr->txr_tail, prod);
+	}
+}
 static int
 ixl_txeof(struct ixl_softc *sc, struct ixl_tx_ring *txr, u_int txlimit)
+{
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	struct ixl_tx_desc *ring, *txd;
 	struct ixl_tx_map *txm;
 	struct mbuf *m;
 	bus_dmamap_t map;
 	unsigned int cons, prod, last;
 	unsigned int mask;
 	uint64_t dtype;
 	int done = 0, more = 0;
 	KASSERT(mutex_owned(&txr->txr_lock));
 	prod = txr->txr_prod;
 	cons = txr->txr_cons;
 	if (cons == prod)
 		return 0;
 	bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem),
 , IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTREAD);
 	ring = IXL_DMA_KVA(&txr->txr_mem);
 	mask = sc->sc_tx_ring_ndescs - 1;
 	net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
 	do {
 		if (txlimit-- <= 0) {
 			more = 1;
 			break;
+		}
 		txm = &txr->txr_maps[cons];
 		last = txm->txm_eop;
 		txd = &ring[last];
 		dtype = txd->cmd & htole64(IXL_TX_DESC_DTYPE_MASK);
 		if (dtype != htole64(IXL_TX_DESC_DTYPE_DONE))
 			break;
 		map = txm->txm_map;
 		bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
 		    BUS_DMASYNC_POSTWRITE);
 		bus_dmamap_unload(sc->sc_dmat, map);
 		m = txm->txm_m;
 		if (m != NULL) {
 			if_statinc_ref(nsr, if_opackets);
 			if_statadd_ref(nsr, if_obytes, m->m_pkthdr.len);
 			if (ISSET(m->m_flags, M_MCAST))
 				if_statinc_ref(nsr, if_omcasts);
 			m_freem(m);
+		}
 		txm->txm_m = NULL;
 		txm->txm_eop = -1;
 		cons = last + 1;
 		cons &= mask;
 		done = 1;
 	} while (cons != prod);
 	IF_STAT_PUTREF(ifp);
 	bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem),
 , IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREREAD);
 	txr->txr_cons = cons;
 	if (done) {
 		softint_schedule(txr->txr_si);
 		if (txr->txr_qid == 0) {
 			CLR(ifp->if_flags, IFF_OACTIVE);
 			if_schedule_deferred_start(ifp);
+		}
+	}
 	return more;
+}
 static void
 ixl_start(struct ifnet *ifp)
+{
 	struct ixl_softc	*sc;
 	struct ixl_tx_ring	*txr;
 	sc = ifp->if_softc;
 	txr = sc->sc_qps[0].qp_txr;
 	mutex_enter(&txr->txr_lock);
 	ixl_tx_common_locked(ifp, txr, false);
 	mutex_exit(&txr->txr_lock);
+}
 static inline unsigned int
 ixl_select_txqueue(struct ixl_softc *sc, struct mbuf *m)
+{
 	u_int cpuid;
 	cpuid = cpu_index(curcpu());
 	return (unsigned int)(cpuid % sc->sc_nqueue_pairs);
+}