FDT support for Cavium OCTEON MIPS SoCs. WIP.diff -r1.17 -r1.18 src/sys/arch/evbmips/cavium/machdep.c
(jmcneill)
--- src/sys/arch/evbmips/cavium/machdep.c 2020/07/13 05:20:45 1.17
+++ src/sys/arch/evbmips/cavium/machdep.c 2020/07/16 11:49:37 1.18
@@ -1,14 +1,14 @@ | @@ -1,14 +1,14 @@ | |||
1 | /* $NetBSD: machdep.c,v 1.17 2020/07/13 05:20:45 simonb Exp $ */ | 1 | /* $NetBSD: machdep.c,v 1.18 2020/07/16 11:49:37 jmcneill Exp $ */ | |
2 | 2 | |||
3 | /* | 3 | /* | |
4 | * Copyright 2001, 2002 Wasabi Systems, Inc. | 4 | * Copyright 2001, 2002 Wasabi Systems, Inc. | |
5 | * All rights reserved. | 5 | * All rights reserved. | |
6 | * | 6 | * | |
7 | * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. | 7 | * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. | |
8 | * | 8 | * | |
9 | * Redistribution and use in source and binary forms, with or without | 9 | * Redistribution and use in source and binary forms, with or without | |
10 | * modification, are permitted provided that the following conditions | 10 | * modification, are permitted provided that the following conditions | |
11 | * are met: | 11 | * are met: | |
12 | * 1. Redistributions of source code must retain the above copyright | 12 | * 1. Redistributions of source code must retain the above copyright | |
13 | * notice, this list of conditions and the following disclaimer. | 13 | * notice, this list of conditions and the following disclaimer. | |
14 | * 2. Redistributions in binary form must reproduce the above copyright | 14 | * 2. Redistributions in binary form must reproduce the above copyright | |
@@ -104,27 +104,27 @@ | @@ -104,27 +104,27 @@ | |||
104 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | 104 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
105 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | 105 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
106 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | 106 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
107 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | 107 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
108 | * SUCH DAMAGE. | 108 | * SUCH DAMAGE. | |
109 | * | 109 | * | |
110 | * @(#)machdep.c 8.3 (Berkeley) 1/12/94 | 110 | * @(#)machdep.c 8.3 (Berkeley) 1/12/94 | |
111 | * from: Utah Hdr: machdep.c 1.63 91/04/24 | 111 | * from: Utah Hdr: machdep.c 1.63 91/04/24 | |
112 | */ | 112 | */ | |
113 | 113 | |||
114 | #include "opt_multiprocessor.h" | 114 | #include "opt_multiprocessor.h" | |
115 | 115 | |||
116 | #include <sys/cdefs.h> | 116 | #include <sys/cdefs.h> | |
117 | __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.17 2020/07/13 05:20:45 simonb Exp $"); | 117 | __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.18 2020/07/16 11:49:37 jmcneill Exp $"); | |
118 | 118 | |||
119 | #include <sys/param.h> | 119 | #include <sys/param.h> | |
120 | #include <sys/systm.h> | 120 | #include <sys/systm.h> | |
121 | #include <sys/kernel.h> | 121 | #include <sys/kernel.h> | |
122 | #include <sys/buf.h> | 122 | #include <sys/buf.h> | |
123 | #include <sys/cpu.h> | 123 | #include <sys/cpu.h> | |
124 | #include <sys/reboot.h> | 124 | #include <sys/reboot.h> | |
125 | #include <sys/mount.h> | 125 | #include <sys/mount.h> | |
126 | #include <sys/kcore.h> | 126 | #include <sys/kcore.h> | |
127 | #include <sys/boot_flag.h> | 127 | #include <sys/boot_flag.h> | |
128 | #include <sys/termios.h> | 128 | #include <sys/termios.h> | |
129 | #include <sys/ksyms.h> | 129 | #include <sys/ksyms.h> | |
130 | 130 | |||
@@ -143,26 +143,28 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v | @@ -143,26 +143,28 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v | |||
143 | #include <machine/locore.h> | 143 | #include <machine/locore.h> | |
144 | 144 | |||
145 | #include <mips/cavium/autoconf.h> | 145 | #include <mips/cavium/autoconf.h> | |
146 | #include <mips/cavium/octeonvar.h> | 146 | #include <mips/cavium/octeonvar.h> | |
147 | #include <mips/cavium/include/iobusvar.h> | 147 | #include <mips/cavium/include/iobusvar.h> | |
148 | #include <mips/cavium/include/bootbusvar.h> | 148 | #include <mips/cavium/include/bootbusvar.h> | |
149 | 149 | |||
150 | #include <mips/cavium/dev/octeon_uartreg.h> | 150 | #include <mips/cavium/dev/octeon_uartreg.h> | |
151 | #include <mips/cavium/dev/octeon_ciureg.h> | 151 | #include <mips/cavium/dev/octeon_ciureg.h> | |
152 | #include <mips/cavium/dev/octeon_gpioreg.h> | 152 | #include <mips/cavium/dev/octeon_gpioreg.h> | |
153 | 153 | |||
154 | #include <evbmips/cavium/octeon_uboot.h> | 154 | #include <evbmips/cavium/octeon_uboot.h> | |
155 | 155 | |||
156 | #include <dev/fdt/fdtvar.h> | |||
157 | ||||
156 | static void mach_init_vector(void); | 158 | static void mach_init_vector(void); | |
157 | static void mach_init_bus_space(void); | 159 | static void mach_init_bus_space(void); | |
158 | static void mach_init_console(void); | 160 | static void mach_init_console(void); | |
159 | static void mach_init_memory(void); | 161 | static void mach_init_memory(void); | |
160 | static void parse_boot_args(void); | 162 | static void parse_boot_args(void); | |
161 | 163 | |||
162 | #include "com.h" | 164 | #include "com.h" | |
163 | #if NCOM > 0 | 165 | #if NCOM > 0 | |
164 | #include <dev/ic/comreg.h> | 166 | #include <dev/ic/comreg.h> | |
165 | #include <dev/ic/comvar.h> | 167 | #include <dev/ic/comvar.h> | |
166 | int comcnrate = 115200; /* XXX should be config option */ | 168 | int comcnrate = 115200; /* XXX should be config option */ | |
167 | #endif /* NCOM > 0 */ | 169 | #endif /* NCOM > 0 */ | |
168 | 170 | |||
@@ -182,26 +184,27 @@ void mach_init(uint64_t, uint64_t, uint6 | @@ -182,26 +184,27 @@ void mach_init(uint64_t, uint64_t, uint6 | |||
182 | struct octeon_config octeon_configuration; | 184 | struct octeon_config octeon_configuration; | |
183 | struct octeon_btdesc octeon_btdesc; | 185 | struct octeon_btdesc octeon_btdesc; | |
184 | struct octeon_btinfo octeon_btinfo; | 186 | struct octeon_btinfo octeon_btinfo; | |
185 | 187 | |||
186 | char octeon_nmi_stack[PAGE_SIZE] __section(".data1") __aligned(PAGE_SIZE); | 188 | char octeon_nmi_stack[PAGE_SIZE] __section(".data1") __aligned(PAGE_SIZE); | |
187 | 189 | |||
188 | /* | 190 | /* | |
189 | * Do all the stuff that locore normally does before calling main(). | 191 | * Do all the stuff that locore normally does before calling main(). | |
190 | */ | 192 | */ | |
191 | void | 193 | void | |
192 | mach_init(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3) | 194 | mach_init(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3) | |
193 | { | 195 | { | |
194 | uint64_t btinfo_paddr; | 196 | uint64_t btinfo_paddr; | |
197 | void *fdt_data; | |||
195 | 198 | |||
196 | /* clear the BSS segment */ | 199 | /* clear the BSS segment */ | |
197 | memset(edata, 0, end - edata); | 200 | memset(edata, 0, end - edata); | |
198 | 201 | |||
199 | cpu_reset_address = octeon_soft_reset; | 202 | cpu_reset_address = octeon_soft_reset; | |
200 | 203 | |||
201 | KASSERT(MIPS_XKPHYS_P(arg3)); | 204 | KASSERT(MIPS_XKPHYS_P(arg3)); | |
202 | btinfo_paddr = mips3_ld(arg3 + OCTEON_BTINFO_PADDR_OFFSET); | 205 | btinfo_paddr = mips3_ld(arg3 + OCTEON_BTINFO_PADDR_OFFSET); | |
203 | 206 | |||
204 | /* XXX KASSERT these addresses? */ | 207 | /* XXX KASSERT these addresses? */ | |
205 | memcpy(&octeon_btdesc, (void *)arg3, sizeof(octeon_btdesc)); | 208 | memcpy(&octeon_btdesc, (void *)arg3, sizeof(octeon_btdesc)); | |
206 | if ((octeon_btdesc.obt_desc_ver == OCTEON_SUPPORTED_DESCRIPTOR_VERSION) && | 209 | if ((octeon_btdesc.obt_desc_ver == OCTEON_SUPPORTED_DESCRIPTOR_VERSION) && | |
207 | (octeon_btdesc.obt_desc_size == sizeof(octeon_btdesc))) { | 210 | (octeon_btdesc.obt_desc_size == sizeof(octeon_btdesc))) { | |
@@ -209,26 +212,33 @@ mach_init(uint64_t arg0, uint64_t arg1, | @@ -209,26 +212,33 @@ mach_init(uint64_t arg0, uint64_t arg1, | |||
209 | octeon_btdesc.obt_boot_info_addr); | 212 | octeon_btdesc.obt_boot_info_addr); | |
210 | } else { | 213 | } else { | |
211 | panic("unknown boot descriptor size %u", | 214 | panic("unknown boot descriptor size %u", | |
212 | octeon_btdesc.obt_desc_size); | 215 | octeon_btdesc.obt_desc_size); | |
213 | } | 216 | } | |
214 | memcpy(&octeon_btinfo, (void *)btinfo_paddr, sizeof(octeon_btinfo)); | 217 | memcpy(&octeon_btinfo, (void *)btinfo_paddr, sizeof(octeon_btinfo)); | |
215 | parse_boot_args(); | 218 | parse_boot_args(); | |
216 | 219 | |||
217 | octeon_cal_timer(octeon_btinfo.obt_eclock_hz); | 220 | octeon_cal_timer(octeon_btinfo.obt_eclock_hz); | |
218 | 221 | |||
219 | cpu_setmodel("Cavium Octeon %s", | 222 | cpu_setmodel("Cavium Octeon %s", | |
220 | octeon_cpu_model(mips_options.mips_cpu_id)); | 223 | octeon_cpu_model(mips_options.mips_cpu_id)); | |
221 | 224 | |||
225 | if (octeon_btinfo.obt_minor_version >= 3 && | |||
226 | octeon_btinfo.obt_fdt_addr != 0) { | |||
227 | fdt_data = (void *)MIPS_PHYS_TO_XKPHYS(CCA_CACHEABLE, | |||
228 | octeon_btinfo.obt_fdt_addr); | |||
229 | fdtbus_init(fdt_data); | |||
230 | } | |||
231 | ||||
222 | mach_init_vector(); | 232 | mach_init_vector(); | |
223 | 233 | |||
224 | uvm_md_init(); | 234 | uvm_md_init(); | |
225 | 235 | |||
226 | mach_init_bus_space(); | 236 | mach_init_bus_space(); | |
227 | 237 | |||
228 | mach_init_console(); | 238 | mach_init_console(); | |
229 | 239 | |||
230 | #ifdef DEBUG | 240 | #ifdef DEBUG | |
231 | /* Show a couple of boot desc/info params for positive feedback */ | 241 | /* Show a couple of boot desc/info params for positive feedback */ | |
232 | printf(">> boot desc eclock = %d\n", octeon_btdesc.obt_eclock); | 242 | printf(">> boot desc eclock = %d\n", octeon_btdesc.obt_eclock); | |
233 | printf(">> boot info board = %d\n", octeon_btinfo.obt_board_type); | 243 | printf(">> boot info board = %d\n", octeon_btinfo.obt_board_type); | |
234 | #endif /* DEBUG */ | 244 | #endif /* DEBUG */ |
--- src/sys/arch/evbmips/conf/OCTEON 2020/07/15 12:15:30 1.1
+++ src/sys/arch/evbmips/conf/OCTEON 2020/07/16 11:49:37 1.2
@@ -1,24 +1,26 @@ | @@ -1,24 +1,26 @@ | |||
1 | # $NetBSD: OCTEON,v 1.1 2020/07/15 12:15:30 simonb Exp $ | 1 | # $NetBSD: OCTEON,v 1.2 2020/07/16 11:49:37 jmcneill Exp $ | |
2 | 2 | |||
3 | include "arch/mips/conf/std.octeon" | 3 | include "arch/mips/conf/std.octeon" | |
4 | include "arch/evbmips/conf/files.octeon" | 4 | include "arch/evbmips/conf/files.octeon" | |
5 | 5 | |||
6 | #options INCLUDE_CONFIG_FILE # embed config file in kernel binary | 6 | #options INCLUDE_CONFIG_FILE # embed config file in kernel binary | |
7 | 7 | |||
8 | #ident "ERLITE-$Revision: 1.1 $" | 8 | #ident "ERLITE-$Revision: 1.2 $" | |
9 | 9 | |||
10 | maxusers 32 | 10 | maxusers 32 | |
11 | 11 | |||
12 | options FDT | |||
13 | ||||
12 | # Options for necessary to use MD | 14 | # Options for necessary to use MD | |
13 | #options MEMORY_DISK_HOOKS | 15 | #options MEMORY_DISK_HOOKS | |
14 | #options MEMORY_DISK_IS_ROOT # force root on memory disk | 16 | #options MEMORY_DISK_IS_ROOT # force root on memory disk | |
15 | #options MEMORY_DISK_SERVER=0 # no userspace memory disk support | 17 | #options MEMORY_DISK_SERVER=0 # no userspace memory disk support | |
16 | #options MEMORY_DISK_ROOT_SIZE=6144 # size of memory disk, in blocks | 18 | #options MEMORY_DISK_ROOT_SIZE=6144 # size of memory disk, in blocks | |
17 | #options MEMORY_DISK_ROOT_SIZE=16384 # size of memory disk, in blocks | 19 | #options MEMORY_DISK_ROOT_SIZE=16384 # size of memory disk, in blocks | |
18 | #options MEMORY_DISK_ROOT_SIZE=7300 | 20 | #options MEMORY_DISK_ROOT_SIZE=7300 | |
19 | 21 | |||
20 | # Size reduction options | 22 | # Size reduction options | |
21 | #options VNODE_OP_NOINLINE | 23 | #options VNODE_OP_NOINLINE | |
22 | #options PIPE_SOCKETPAIR | 24 | #options PIPE_SOCKETPAIR | |
23 | #options SOSEND_NO_LOAN | 25 | #options SOSEND_NO_LOAN | |
24 | 26 | |||
@@ -103,31 +105,37 @@ options MIIVERBOSE # verbose PHY autoco | @@ -103,31 +105,37 @@ options MIIVERBOSE # verbose PHY autoco | |||
103 | 105 | |||
104 | options NFS_BOOT_DHCP | 106 | options NFS_BOOT_DHCP | |
105 | 107 | |||
106 | config netbsd root on ? type ? | 108 | config netbsd root on ? type ? | |
107 | #config netbsd root on cnmac0 type nfs | 109 | #config netbsd root on cnmac0 type nfs | |
108 | 110 | |||
109 | mainbus0 at root | 111 | mainbus0 at root | |
110 | cpunode0 at mainbus? | 112 | cpunode0 at mainbus? | |
111 | cpu* at cpunode? core ? | 113 | cpu* at cpunode? core ? | |
112 | wdog0 at cpunode0 flags 0 # flags 1 will enable it on boot | 114 | wdog0 at cpunode0 flags 0 # flags 1 will enable it on boot | |
113 | 115 | |||
114 | iobus0 at mainbus? | 116 | iobus0 at mainbus? | |
115 | bootbus0 at mainbus? | 117 | bootbus0 at mainbus? | |
118 | simplebus* at fdt? pass 0 | |||
119 | ||||
120 | octintc* at fdt? pass 1 | |||
116 | 121 | |||
117 | com* at iobus? | 122 | com* at iobus? | |
123 | com* at fdt? | |||
118 | 124 | |||
119 | octsmi* at iobus? # MDIO controller | 125 | octsmi* at iobus? # MDIO controller | |
126 | octsmi* at fdt? pass 2 | |||
120 | octpip* at iobus? # PIP packet processing controller | 127 | octpip* at iobus? # PIP packet processing controller | |
128 | octpip* at fdt? pass 3 | |||
121 | 129 | |||
122 | octgmx* at octpip? | 130 | octgmx* at octpip? | |
123 | cnmac* at octgmx? | 131 | cnmac* at octgmx? | |
124 | 132 | |||
125 | octrnm* at iobus? # Random Number Memory (and generator) | 133 | octrnm* at iobus? # Random Number Memory (and generator) | |
126 | 134 | |||
127 | dwctwo* at iobus? | 135 | dwctwo* at iobus? | |
128 | 136 | |||
129 | usb* at dwctwo? | 137 | usb* at dwctwo? | |
130 | 138 | |||
131 | uhub* at usb? | 139 | uhub* at usb? | |
132 | 140 | |||
133 | # USB Mass Storage | 141 | # USB Mass Storage |
--- src/sys/arch/mips/cavium/mainbus.c 2015/04/29 08:32:00 1.1
+++ src/sys/arch/mips/cavium/mainbus.c 2020/07/16 11:49:37 1.2
@@ -1,14 +1,14 @@ | @@ -1,14 +1,14 @@ | |||
1 | /* $NetBSD: mainbus.c,v 1.1 2015/04/29 08:32:00 hikaru Exp $ */ | 1 | /* $NetBSD: mainbus.c,v 1.2 2020/07/16 11:49:37 jmcneill Exp $ */ | |
2 | 2 | |||
3 | /* | 3 | /* | |
4 | * Copyright (c) 2007 | 4 | * Copyright (c) 2007 | |
5 | * Internet Initiative Japan, Inc. All rights reserved. | 5 | * Internet Initiative Japan, Inc. All rights reserved. | |
6 | * | 6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | 7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | 8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | 9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | 10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | 11 | * notice, this list of conditions and the following disclaimer. | |
12 | * 2. Redistributions in binary form must reproduce the above copyright | 12 | * 2. Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in the | 13 | * notice, this list of conditions and the following disclaimer in the | |
14 | * documentation and/or other materials provided with the distribution. | 14 | * documentation and/or other materials provided with the distribution. | |
@@ -17,80 +17,150 @@ | @@ -17,80 +17,150 @@ | |||
17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE | 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE | |
20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | 20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | 21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | 22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | 23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | 24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | 25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
26 | * SUCH DAMAGE. | 26 | * SUCH DAMAGE. | |
27 | */ | 27 | */ | |
28 | 28 | |||
29 | #include <sys/cdefs.h> | 29 | #include <sys/cdefs.h> | |
30 | __KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.1 2015/04/29 08:32:00 hikaru Exp $"); | 30 | __KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.2 2020/07/16 11:49:37 jmcneill Exp $"); | |
31 | ||||
32 | #define _MIPS_BUS_DMA_PRIVATE | |||
31 | 33 | |||
32 | #include <sys/param.h> | 34 | #include <sys/param.h> | |
33 | #include <sys/systm.h> | 35 | #include <sys/systm.h> | |
34 | #include <sys/device.h> | 36 | #include <sys/device.h> | |
37 | #include <sys/bus.h> | |||
35 | 38 | |||
36 | #include <mips/cavium/include/mainbusvar.h> | 39 | #include <mips/cavium/include/mainbusvar.h> | |
37 | 40 | |||
41 | #include <dev/fdt/fdtvar.h> | |||
42 | ||||
38 | static int mainbus_match(device_t, struct cfdata *, void *); | 43 | static int mainbus_match(device_t, struct cfdata *, void *); | |
39 | static void mainbus_attach(device_t, device_t, void *); | 44 | static void mainbus_attach(device_t, device_t, void *); | |
45 | static void mainbus_attach_static(device_t); | |||
46 | static void mainbus_attach_devicetree(device_t); | |||
40 | static int mainbus_submatch(device_t, cfdata_t, const int *, void *); | 47 | static int mainbus_submatch(device_t, cfdata_t, const int *, void *); | |
41 | static int mainbus_print(void *, const char *); | 48 | static int mainbus_print(void *, const char *); | |
42 | 49 | |||
50 | static void simplebus_bus_io_init(bus_space_tag_t, void *); | |||
51 | ||||
43 | CFATTACH_DECL_NEW(mainbus, sizeof(device_t), mainbus_match, mainbus_attach, | 52 | CFATTACH_DECL_NEW(mainbus, sizeof(device_t), mainbus_match, mainbus_attach, | |
44 | NULL, NULL); | 53 | NULL, NULL); | |
45 | 54 | |||
55 | static struct mips_bus_space simplebus_bus_tag; | |||
56 | ||||
57 | static struct mips_bus_dma_tag simplebus_dma_tag = { | |||
58 | ._cookie = NULL, | |||
59 | ._wbase = 0, | |||
60 | ._bounce_alloc_lo = 0, | |||
61 | ._bounce_alloc_hi = 0, | |||
62 | ._dmamap_ops = _BUS_DMAMAP_OPS_INITIALIZER, | |||
63 | ._dmamem_ops = _BUS_DMAMEM_OPS_INITIALIZER, | |||
64 | ._dmatag_ops = _BUS_DMATAG_OPS_INITIALIZER, | |||
65 | }; | |||
66 | ||||
46 | static int | 67 | static int | |
47 | mainbus_match(device_t parent, struct cfdata *match, void *aux) | 68 | mainbus_match(device_t parent, struct cfdata *match, void *aux) | |
48 | { | 69 | { | |
49 | static int once = 0; | 70 | static int once = 0; | |
50 | 71 | |||
51 | if (once != 0) | 72 | if (once != 0) | |
52 | return 0; | 73 | return 0; | |
53 | once = 1; | 74 | once = 1; | |
54 | 75 | |||
55 | return 1; | 76 | return 1; | |
56 | } | 77 | } | |
57 | 78 | |||
58 | static void | 79 | static void | |
59 | mainbus_attach(device_t parent, device_t self, void *aux) | 80 | mainbus_attach(device_t parent, device_t self, void *aux) | |
60 | { | 81 | { | |
61 | int i; | |||
62 | struct mainbus_attach_args aa; | |||
63 | ||||
64 | aprint_normal("\n"); | 82 | aprint_normal("\n"); | |
65 | 83 | |||
84 | if (fdtbus_get_data() != NULL) { | |||
85 | mainbus_attach_devicetree(self); | |||
86 | } else { | |||
87 | mainbus_attach_static(self); | |||
88 | } | |||
89 | } | |||
90 | ||||
91 | static void | |||
92 | mainbus_attach_static(device_t self) | |||
93 | { | |||
94 | struct mainbus_attach_args aa; | |||
95 | int i; | |||
96 | ||||
66 | for (i = 0; i < (int)mainbus_ndevs; i++) { | 97 | for (i = 0; i < (int)mainbus_ndevs; i++) { | |
67 | aa.aa_name = mainbus_devs[i]; | 98 | aa.aa_name = mainbus_devs[i]; | |
68 | (void)config_found_sm_loc(self, "mainbus", NULL, &aa, | 99 | config_found_sm_loc(self, "mainbus", NULL, &aa, | |
69 | mainbus_print, mainbus_submatch); | 100 | mainbus_print, mainbus_submatch); | |
70 | } | 101 | } | |
71 | } | 102 | } | |
72 | 103 | |||
104 | extern struct octeon_config octeon_configuration; | |||
105 | extern void octpow_bootstrap(struct octeon_config *); | |||
106 | extern void octfpa_bootstrap(struct octeon_config *); | |||
107 | ||||
108 | static void | |||
109 | mainbus_attach_devicetree(device_t self) | |||
110 | { | |||
111 | struct mainbus_attach_args aa; | |||
112 | struct fdt_attach_args faa; | |||
113 | ||||
114 | aa.aa_name = "cpunode"; | |||
115 | config_found_sm_loc(self, "mainbus", NULL, &aa, mainbus_print, | |||
116 | mainbus_submatch); | |||
117 | ||||
118 | octpow_bootstrap(&octeon_configuration); | |||
119 | octfpa_bootstrap(&octeon_configuration); | |||
120 | ||||
121 | simplebus_bus_io_init(&simplebus_bus_tag, NULL); | |||
122 | ||||
123 | faa.faa_bst = &simplebus_bus_tag; | |||
124 | faa.faa_a4x_bst = NULL; /* XXX */ | |||
125 | faa.faa_dmat = &simplebus_dma_tag; | |||
126 | faa.faa_name = ""; | |||
127 | faa.faa_phandle = OF_peer(0); | |||
128 | config_found(self, &faa, NULL); | |||
129 | } | |||
130 | ||||
73 | static int | 131 | static int | |
74 | mainbus_submatch(device_t parent, cfdata_t cf, const int *locs, void *aux) | 132 | mainbus_submatch(device_t parent, cfdata_t cf, const int *locs, void *aux) | |
75 | { | 133 | { | |
76 | struct mainbus_attach_args *aa = aux; | 134 | struct mainbus_attach_args *aa = aux; | |
77 | 135 | |||
78 | if (strcmp(cf->cf_name, aa->aa_name) != 0) | 136 | if (strcmp(cf->cf_name, aa->aa_name) != 0) | |
79 | return 0; | 137 | return 0; | |
80 | 138 | |||
81 | return config_match(parent, cf, aux); | 139 | return config_match(parent, cf, aux); | |
82 | } | 140 | } | |
83 | 141 | |||
84 | static int | 142 | static int | |
85 | mainbus_print(void *aux, const char *pnp) | 143 | mainbus_print(void *aux, const char *pnp) | |
86 | { | 144 | { | |
87 | struct mainbus_attach_args *aa = aux; | 145 | struct mainbus_attach_args *aa = aux; | |
88 | 146 | |||
89 | if (pnp != 0) | 147 | if (pnp != 0) | |
90 | return QUIET; | 148 | return QUIET; | |
91 | 149 | |||
92 | if (pnp) | 150 | if (pnp) | |
93 | aprint_normal("%s at %s", aa->aa_name, pnp); | 151 | aprint_normal("%s at %s", aa->aa_name, pnp); | |
94 | 152 | |||
95 | return UNCONF; | 153 | return UNCONF; | |
96 | } | 154 | } | |
155 | ||||
156 | /* ---- bus_space(9) */ | |||
157 | #define CHIP simplebus | |||
158 | #define CHIP_IO | |||
159 | #define CHIP_ACCESS_SIZE 8 | |||
160 | ||||
161 | #define CHIP_W1_BUS_START(v) 0x0000000000000000ULL | |||
162 | #define CHIP_W1_BUS_END(v) 0x7fffffffffffffffULL | |||
163 | #define CHIP_W1_SYS_START(v) 0x8000000000000000ULL | |||
164 | #define CHIP_W1_SYS_END(v) 0xffffffffffffffffULL | |||
165 | ||||
166 | #include <mips/mips/bus_space_alignstride_chipdep.c> |
/* $NetBSD: octeon_intc.c,v 1.1 2020/07/16 11:49:37 jmcneill Exp $ */
/*-
* Copyright (c) 2020 Jared D. McNeill <jmcneill@invisible.ca>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: octeon_intc.c,v 1.1 2020/07/16 11:49:37 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
#include <sys/intr.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/kmem.h>
#include <dev/fdt/fdtvar.h>
#include <arch/mips/cavium/octeonvar.h>
static int octeon_intc_match(device_t, cfdata_t, void *);
static void octeon_intc_attach(device_t, device_t, void *);
static void * octeon_intc_establish(device_t, u_int *, int, int,
int (*)(void *), void *);
static void octeon_intc_disestablish(device_t, void *);
static bool octeon_intc_intrstr(device_t, u_int *, char *, size_t);
struct fdtbus_interrupt_controller_func octeon_intc_funcs = {
.establish = octeon_intc_establish,
.disestablish = octeon_intc_disestablish,
.intrstr = octeon_intc_intrstr
};
enum octeon_intc_type {
OCTEON_INTC_CIU,
};
struct octeon_intc_softc {
device_t sc_dev;
int sc_phandle;
enum octeon_intc_type sc_type;
const char *sc_descr;
};
CFATTACH_DECL_NEW(octintc, sizeof(struct octeon_intc_softc),
octeon_intc_match, octeon_intc_attach, NULL, NULL);
static const struct of_compat_data compat_data[] = {
{ "cavium,octeon-3860-ciu", OCTEON_INTC_CIU },
{ NULL }
};
static int
octeon_intc_match(device_t parent, cfdata_t cf, void *aux)
{
struct fdt_attach_args * const faa = aux;
return of_match_compat_data(faa->faa_phandle, compat_data);
}
static void
octeon_intc_attach(device_t parent, device_t self, void *aux)
{
struct octeon_intc_softc * const sc = device_private(self);
struct fdt_attach_args * const faa = aux;
const int phandle = faa->faa_phandle;
int error;
sc->sc_dev = self;
sc->sc_phandle = phandle;
sc->sc_type = of_search_compatible(phandle, compat_data)->data;
switch (sc->sc_type) {
case OCTEON_INTC_CIU:
sc->sc_descr = "CIU";
break;
}
error = fdtbus_register_interrupt_controller(self, phandle,
&octeon_intc_funcs);
if (error != 0) {
aprint_error(": couldn't register with fdtbus: %d\n", error);
return;
}
aprint_naive("\n");
aprint_normal(": %s\n", sc->sc_descr);
}
static void *
octeon_intc_establish(device_t dev, u_int *specifier, int ipl, int flags,
int (*func)(void *), void *arg)
{
struct octeon_intc_softc * const sc = device_private(dev);
/* 1st cell is the controller register (0 or 1) */
/* 2nd cell is the bit within the register (0..63) */
const u_int reg = be32toh(specifier[0]);
const u_int bit = be32toh(specifier[1]);
const u_int irq = (reg * 64) + bit;
if (irq >= NIRQS) {
aprint_error_dev(dev, "%s irq %d (%d, %d) out of range\n",
sc->sc_descr, irq, reg, bit);
return NULL;
}
return octeon_intr_establish(irq, ipl, func, arg);
}
static void
octeon_intc_disestablish(device_t dev, void *ih)
{
octeon_intr_disestablish(ih);
}
static bool
octeon_intc_intrstr(device_t dev, u_int *specifier, char *buf,
size_t buflen)
{
struct octeon_intc_softc * const sc = device_private(dev);
/* 1st cell is the controller register (0 or 1) */
/* 2nd cell is the bit within the register (0..63) */
const u_int reg = be32toh(specifier[0]);
const u_int bit = be32toh(specifier[1]);
const u_int irq = (reg * 64) + bit;
snprintf(buf, buflen, "%s irq %d", sc->sc_descr, irq);
return true;
}
--- src/sys/arch/mips/cavium/dev/octeon_pip.c 2020/06/23 05:18:02 1.8
+++ src/sys/arch/mips/cavium/dev/octeon_pip.c 2020/07/16 11:49:37 1.9
@@ -1,14 +1,14 @@ | @@ -1,14 +1,14 @@ | |||
1 | /* $NetBSD: octeon_pip.c,v 1.8 2020/06/23 05:18:02 simonb Exp $ */ | 1 | /* $NetBSD: octeon_pip.c,v 1.9 2020/07/16 11:49:37 jmcneill Exp $ */ | |
2 | 2 | |||
3 | /* | 3 | /* | |
4 | * Copyright (c) 2007 Internet Initiative Japan, Inc. | 4 | * Copyright (c) 2007 Internet Initiative Japan, Inc. | |
5 | * All rights reserved. | 5 | * All rights reserved. | |
6 | * | 6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | 7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | 8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | 9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | 10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | 11 | * notice, this list of conditions and the following disclaimer. | |
12 | * 2. Redistributions in binary form must reproduce the above copyright | 12 | * 2. Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in the | 13 | * notice, this list of conditions and the following disclaimer in the | |
14 | * documentation and/or other materials provided with the distribution. | 14 | * documentation and/or other materials provided with the distribution. | |
@@ -17,61 +17,79 @@ | @@ -17,61 +17,79 @@ | |||
17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE | 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE | |
20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | 20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | 21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | 22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | 23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | 24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | 25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
26 | * SUCH DAMAGE. | 26 | * SUCH DAMAGE. | |
27 | */ | 27 | */ | |
28 | 28 | |||
29 | #include <sys/cdefs.h> | 29 | #include <sys/cdefs.h> | |
30 | __KERNEL_RCSID(0, "$NetBSD: octeon_pip.c,v 1.8 2020/06/23 05:18:02 simonb Exp $"); | 30 | __KERNEL_RCSID(0, "$NetBSD: octeon_pip.c,v 1.9 2020/07/16 11:49:37 jmcneill Exp $"); | |
31 | 31 | |||
32 | #include <sys/param.h> | 32 | #include <sys/param.h> | |
33 | #include <sys/systm.h> | 33 | #include <sys/systm.h> | |
34 | #include <sys/malloc.h> | 34 | #include <sys/malloc.h> | |
35 | #include <sys/syslog.h> | 35 | #include <sys/syslog.h> | |
36 | #include <sys/time.h> | 36 | #include <sys/time.h> | |
37 | #include <net/if.h> | 37 | #include <net/if.h> | |
38 | 38 | |||
39 | #include <mips/locore.h> | 39 | #include <mips/locore.h> | |
40 | 40 | |||
41 | #include <mips/cavium/octeonvar.h> | 41 | #include <mips/cavium/octeonvar.h> | |
42 | #include <mips/cavium/dev/octeon_gmxreg.h> | 42 | #include <mips/cavium/dev/octeon_gmxreg.h> | |
43 | #include <mips/cavium/dev/octeon_pipreg.h> | 43 | #include <mips/cavium/dev/octeon_pipreg.h> | |
44 | #include <mips/cavium/dev/octeon_pipvar.h> | 44 | #include <mips/cavium/dev/octeon_pipvar.h> | |
45 | #include <mips/cavium/include/iobusvar.h> | 45 | #include <mips/cavium/include/iobusvar.h> | |
46 | 46 | |||
47 | static int octpip_match(device_t, struct cfdata *, void *); | 47 | #include <dev/fdt/fdtvar.h> | |
48 | static void octpip_attach(device_t, device_t, void *); | |||
49 | 48 | |||
50 | CFATTACH_DECL_NEW(octpip, sizeof(struct octpip_softc), | 49 | static int octpip_iobus_match(device_t, struct cfdata *, void *); | |
51 | octpip_match, octpip_attach, NULL, NULL); | 50 | static void octpip_iobus_attach(device_t, device_t, void *); | |
51 | ||||
52 | static int octpip_fdt_match(device_t, struct cfdata *, void *); | |||
53 | static void octpip_fdt_attach(device_t, device_t, void *); | |||
54 | ||||
55 | CFATTACH_DECL_NEW(octpip_iobus, sizeof(struct octpip_softc), | |||
56 | octpip_iobus_match, octpip_iobus_attach, NULL, NULL); | |||
57 | ||||
58 | CFATTACH_DECL_NEW(octpip_fdt, sizeof(struct octpip_softc), | |||
59 | octpip_fdt_match, octpip_fdt_attach, NULL, NULL); | |||
60 | ||||
61 | static const char * compatible[] = { | |||
62 | "cavium,octeon-3860-pip", | |||
63 | NULL | |||
64 | }; | |||
65 | ||||
66 | static const char * pip_interface_compatible[] = { | |||
67 | "cavium,octeon-3860-pip-interface", | |||
68 | NULL | |||
69 | }; | |||
52 | 70 | |||
53 | static int | 71 | static int | |
54 | octpip_match(device_t parent, struct cfdata *cf, void *aux) | 72 | octpip_iobus_match(device_t parent, struct cfdata *cf, void *aux) | |
55 | { | 73 | { | |
56 | struct iobus_attach_args *aa = aux; | 74 | struct iobus_attach_args *aa = aux; | |
57 | 75 | |||
58 | if (strcmp(cf->cf_name, aa->aa_name) != 0) | 76 | if (strcmp(cf->cf_name, aa->aa_name) != 0) | |
59 | return 0; | 77 | return 0; | |
60 | return 1; | 78 | return 1; | |
61 | } | 79 | } | |
62 | 80 | |||
63 | static void | 81 | static void | |
64 | octpip_attach(device_t parent, device_t self, void *aux) | 82 | octpip_iobus_attach(device_t parent, device_t self, void *aux) | |
65 | { | 83 | { | |
66 | struct octpip_softc *sc = device_private(self); | 84 | struct octpip_softc *sc = device_private(self); | |
67 | struct iobus_attach_args *aa = aux; | 85 | struct iobus_attach_args *aa = aux; | |
68 | struct iobus_attach_args gmxaa; | 86 | struct iobus_attach_args gmxaa; | |
69 | struct iobus_unit gmxiu; | 87 | struct iobus_unit gmxiu; | |
70 | int i, ndevs; | 88 | int i, ndevs; | |
71 | 89 | |||
72 | sc->sc_dev = self; | 90 | sc->sc_dev = self; | |
73 | 91 | |||
74 | aprint_normal("\n"); | 92 | aprint_normal("\n"); | |
75 | 93 | |||
76 | /* | 94 | /* | |
77 | * XXX: In a non-FDT world, should allow for the configuration | 95 | * XXX: In a non-FDT world, should allow for the configuration | |
@@ -88,26 +106,80 @@ octpip_attach(device_t parent, device_t | @@ -88,26 +106,80 @@ octpip_attach(device_t parent, device_t | |||
88 | gmxaa.aa_unit = &gmxiu; | 106 | gmxaa.aa_unit = &gmxiu; | |
89 | gmxaa.aa_bust = aa->aa_bust; | 107 | gmxaa.aa_bust = aa->aa_bust; | |
90 | gmxaa.aa_dmat = aa->aa_dmat; | 108 | gmxaa.aa_dmat = aa->aa_dmat; | |
91 | 109 | |||
92 | if (MIPS_PRID_IMPL(mips_options.mips_cpu_id) == MIPS_CN68XX) | 110 | if (MIPS_PRID_IMPL(mips_options.mips_cpu_id) == MIPS_CN68XX) | |
93 | gmxiu.addr = GMX_CN68XX_BASE_PORT(i, 0); | 111 | gmxiu.addr = GMX_CN68XX_BASE_PORT(i, 0); | |
94 | else | 112 | else | |
95 | gmxiu.addr = GMX_BASE_PORT(i, 0); | 113 | gmxiu.addr = GMX_BASE_PORT(i, 0); | |
96 | 114 | |||
97 | config_found(self, &gmxaa, NULL); | 115 | config_found(self, &gmxaa, NULL); | |
98 | } | 116 | } | |
99 | } | 117 | } | |
100 | 118 | |||
119 | static int | |||
120 | octpip_fdt_match(device_t parent, struct cfdata *cf, void *aux) | |||
121 | { | |||
122 | struct fdt_attach_args * const faa = aux; | |||
123 | ||||
124 | return of_match_compatible(faa->faa_phandle, compatible); | |||
125 | } | |||
126 | ||||
127 | static void | |||
128 | octpip_fdt_attach(device_t parent, device_t self, void *aux) | |||
129 | { | |||
130 | struct octpip_softc *sc = device_private(self); | |||
131 | struct fdt_attach_args * const faa = aux; | |||
132 | const int phandle = faa->faa_phandle; | |||
133 | struct iobus_attach_args gmxaa; | |||
134 | struct iobus_unit gmxiu; | |||
135 | bus_addr_t intno; | |||
136 | int child; | |||
137 | ||||
138 | sc->sc_dev = self; | |||
139 | ||||
140 | aprint_normal("\n"); | |||
141 | ||||
142 | for (child = OF_child(phandle); child; child = OF_peer(child)) { | |||
143 | if (!of_match_compatible(child, pip_interface_compatible)) | |||
144 | continue; | |||
145 | ||||
146 | if (fdtbus_get_reg(child, 0, &intno, NULL) != 0) { | |||
147 | aprint_error_dev(self, "couldn't get interface number for %s\n", | |||
148 | fdtbus_get_string(child, "name")); | |||
149 | continue; | |||
150 | } | |||
151 | ||||
152 | memset(&gmxaa, 0, sizeof(gmxaa)); | |||
153 | memset(&gmxiu, 0, sizeof(gmxiu)); | |||
154 | ||||
155 | gmxaa.aa_name = "octgmx"; | |||
156 | gmxaa.aa_unitno = (int)intno; | |||
157 | gmxaa.aa_unit = &gmxiu; | |||
158 | gmxaa.aa_bust = faa->faa_bst; | |||
159 | gmxaa.aa_dmat = faa->faa_dmat; | |||
160 | ||||
161 | if (MIPS_PRID_IMPL(mips_options.mips_cpu_id) == MIPS_CN68XX) | |||
162 | gmxiu.addr = GMX_CN68XX_BASE_PORT(intno, 0); | |||
163 | else | |||
164 | gmxiu.addr = GMX_BASE_PORT(intno, 0); | |||
165 | ||||
166 | config_found(self, &gmxaa, NULL); | |||
167 | ||||
168 | /* XXX only one interface supported by octgmx */ | |||
169 | return; | |||
170 | } | |||
171 | } | |||
172 | ||||
101 | /* XXX */ | 173 | /* XXX */ | |
102 | void | 174 | void | |
103 | octpip_init(struct octpip_attach_args *aa, struct octpip_softc **rsc) | 175 | octpip_init(struct octpip_attach_args *aa, struct octpip_softc **rsc) | |
104 | { | 176 | { | |
105 | struct octpip_softc *sc; | 177 | struct octpip_softc *sc; | |
106 | int status; | 178 | int status; | |
107 | 179 | |||
108 | sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); | 180 | sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); | |
109 | if (sc == NULL) | 181 | if (sc == NULL) | |
110 | panic("can't allocate memory: %s", __func__); | 182 | panic("can't allocate memory: %s", __func__); | |
111 | 183 | |||
112 | sc->sc_port = aa->aa_port; | 184 | sc->sc_port = aa->aa_port; | |
113 | sc->sc_regt = aa->aa_regt; | 185 | sc->sc_regt = aa->aa_regt; |
--- src/sys/arch/mips/cavium/dev/octeon_smi.c 2020/06/23 05:18:02 1.5
+++ src/sys/arch/mips/cavium/dev/octeon_smi.c 2020/07/16 11:49:37 1.6
@@ -1,14 +1,14 @@ | @@ -1,14 +1,14 @@ | |||
1 | /* $NetBSD: octeon_smi.c,v 1.5 2020/06/23 05:18:02 simonb Exp $ */ | 1 | /* $NetBSD: octeon_smi.c,v 1.6 2020/07/16 11:49:37 jmcneill Exp $ */ | |
2 | 2 | |||
3 | /* | 3 | /* | |
4 | * Copyright (c) 2007 Internet Initiative Japan, Inc. | 4 | * Copyright (c) 2007 Internet Initiative Japan, Inc. | |
5 | * All rights reserved. | 5 | * All rights reserved. | |
6 | * | 6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | 7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | 8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | 9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | 10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | 11 | * notice, this list of conditions and the following disclaimer. | |
12 | * 2. Redistributions in binary form must reproduce the above copyright | 12 | * 2. Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in the | 13 | * notice, this list of conditions and the following disclaimer in the | |
14 | * documentation and/or other materials provided with the distribution. | 14 | * documentation and/or other materials provided with the distribution. | |
@@ -17,112 +17,182 @@ | @@ -17,112 +17,182 @@ | |||
17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE | 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE | |
20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | 20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | 21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | 22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | 23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | 24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | 25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
26 | * SUCH DAMAGE. | 26 | * SUCH DAMAGE. | |
27 | */ | 27 | */ | |
28 | 28 | |||
29 | #include <sys/cdefs.h> | 29 | #include <sys/cdefs.h> | |
30 | __KERNEL_RCSID(0, "$NetBSD: octeon_smi.c,v 1.5 2020/06/23 05:18:02 simonb Exp $"); | 30 | __KERNEL_RCSID(0, "$NetBSD: octeon_smi.c,v 1.6 2020/07/16 11:49:37 jmcneill Exp $"); | |
31 | 31 | |||
32 | #include <sys/param.h> | 32 | #include <sys/param.h> | |
33 | #include <sys/systm.h> | 33 | #include <sys/systm.h> | |
34 | #include <sys/bus.h> | 34 | #include <sys/bus.h> | |
35 | #include <sys/device.h> | 35 | #include <sys/device.h> | |
36 | #include <sys/malloc.h> | 36 | #include <sys/malloc.h> | |
37 | #include <sys/mbuf.h> | 37 | #include <sys/mbuf.h> | |
38 | #include <sys/queue.h> | |||
39 | #include <sys/kmem.h> | |||
38 | 40 | |||
39 | #include <mips/locore.h> | 41 | #include <mips/locore.h> | |
40 | #include <mips/cavium/octeonvar.h> | 42 | #include <mips/cavium/octeonvar.h> | |
41 | #include <mips/cavium/dev/octeon_fpareg.h> | 43 | #include <mips/cavium/dev/octeon_fpareg.h> | |
42 | #include <mips/cavium/dev/octeon_fpavar.h> | 44 | #include <mips/cavium/dev/octeon_fpavar.h> | |
43 | #include <mips/cavium/dev/octeon_pipreg.h> | 45 | #include <mips/cavium/dev/octeon_pipreg.h> | |
44 | #include <mips/cavium/dev/octeon_smireg.h> | 46 | #include <mips/cavium/dev/octeon_smireg.h> | |
45 | #include <mips/cavium/dev/octeon_smivar.h> | 47 | #include <mips/cavium/dev/octeon_smivar.h> | |
46 | #include <mips/cavium/include/iobusvar.h> | 48 | #include <mips/cavium/include/iobusvar.h> | |
47 | 49 | |||
50 | #include <dev/fdt/fdtvar.h> | |||
51 | ||||
48 | /* | 52 | /* | |
49 | * System Management Interface | 53 | * System Management Interface | |
50 | * | 54 | * | |
51 | * | 55 | * | |
52 | * CN30XX - 1 SMI interface | 56 | * CN30XX - 1 SMI interface | |
53 | * CN31XX - 1 SMI interface | 57 | * CN31XX - 1 SMI interface | |
54 | * CN38XX - 1 SMI interface | 58 | * CN38XX - 1 SMI interface | |
55 | * CN50XX - 1 SMI interface | 59 | * CN50XX - 1 SMI interface | |
56 | * CN52XX - 2 SMI interfaces | 60 | * CN52XX - 2 SMI interfaces | |
57 | * CN56XX - 2 SMI interfaces | 61 | * CN56XX - 2 SMI interfaces | |
58 | * CN58XX - 1 SMI interface | 62 | * CN58XX - 1 SMI interface | |
59 | * CN61XX - 2 SMI interfaces | 63 | * CN61XX - 2 SMI interfaces | |
60 | * CN63XX - 2 SMI interfaces | 64 | * CN63XX - 2 SMI interfaces | |
61 | * CN66XX - 2 SMI interfaces | 65 | * CN66XX - 2 SMI interfaces | |
62 | * CN68XX - 4 SMI interfaces | 66 | * CN68XX - 4 SMI interfaces | |
63 | * CN70XX - 2 SMI interfaces | 67 | * CN70XX - 2 SMI interfaces | |
64 | * CN73XX - 2 SMI interfaces | 68 | * CN73XX - 2 SMI interfaces | |
65 | * CN78XX - 4 SMI interfaces | 69 | * CN78XX - 4 SMI interfaces | |
66 | * CNF71XX - 2 SMI interfaces | 70 | * CNF71XX - 2 SMI interfaces | |
67 | * CNF75XX - 2 SMI interfaces | 71 | * CNF75XX - 2 SMI interfaces | |
68 | */ | 72 | */ | |
69 | 73 | |||
70 | static int octsmi_match(device_t, struct cfdata *, void *); | 74 | static int octsmi_iobus_match(device_t, struct cfdata *, void *); | |
71 | static void octsmi_attach(device_t, device_t, void *); | 75 | static void octsmi_iobus_attach(device_t, device_t, void *); | |
76 | ||||
77 | static int octsmi_fdt_match(device_t, struct cfdata *, void *); | |||
78 | static void octsmi_fdt_attach(device_t, device_t, void *); | |||
79 | ||||
80 | static void octsmi_attach_common(struct octsmi_softc *, int); | |||
72 | 81 | |||
73 | struct octsmi_softc *smi_list; /* XXX up to 4 SMIs on CN68XX,CN78XX */ | 82 | struct octsmi_instance { | |
83 | struct octsmi_softc * sc; | |||
84 | int phandle; | |||
85 | TAILQ_ENTRY(octsmi_instance) next; | |||
86 | }; | |||
87 | ||||
88 | static TAILQ_HEAD(, octsmi_instance) octsmi_instances = | |||
89 | TAILQ_HEAD_INITIALIZER(octsmi_instances); | |||
74 | 90 | |||
75 | #define _SMI_RD8(sc, off) \ | 91 | #define _SMI_RD8(sc, off) \ | |
76 | bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off)) | 92 | bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off)) | |
77 | #define _SMI_WR8(sc, off, v) \ | 93 | #define _SMI_WR8(sc, off, v) \ | |
78 | bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v)) | 94 | bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v)) | |
79 | 95 | |||
80 | CFATTACH_DECL_NEW(octsmi, sizeof(struct octsmi_softc), | 96 | CFATTACH_DECL_NEW(octsmi_iobus, sizeof(struct octsmi_softc), | |
81 | octsmi_match, octsmi_attach, NULL, NULL); | 97 | octsmi_iobus_match, octsmi_iobus_attach, NULL, NULL); | |
98 | ||||
99 | CFATTACH_DECL_NEW(octsmi_fdt, sizeof(struct octsmi_softc), | |||
100 | octsmi_fdt_match, octsmi_fdt_attach, NULL, NULL); | |||
101 | ||||
102 | static const char * compatible[] = { | |||
103 | "cavium,octeon-3860-mdio", | |||
104 | NULL | |||
105 | }; | |||
82 | 106 | |||
83 | static int | 107 | static int | |
84 | octsmi_match(device_t parent, struct cfdata *cf, void *aux) | 108 | octsmi_iobus_match(device_t parent, struct cfdata *cf, void *aux) | |
85 | { | 109 | { | |
86 | struct iobus_attach_args *aa = aux; | 110 | struct iobus_attach_args *aa = aux; | |
87 | 111 | |||
88 | if (strcmp(cf->cf_name, aa->aa_name) != 0) | 112 | if (strcmp(cf->cf_name, aa->aa_name) != 0) | |
89 | return 0; | 113 | return 0; | |
90 | if (aa->aa_unitno < SMI_NUNITS) | 114 | if (aa->aa_unitno < SMI_NUNITS) | |
91 | return 1; | 115 | return 1; | |
92 | else | 116 | else | |
93 | return 0; | 117 | return 0; | |
94 | } | 118 | } | |
95 | 119 | |||
96 | static void | 120 | static void | |
97 | octsmi_attach(device_t parent, device_t self, void *aux) | 121 | octsmi_iobus_attach(device_t parent, device_t self, void *aux) | |
98 | { | 122 | { | |
99 | struct octsmi_softc *sc = device_private(self); | 123 | struct octsmi_softc *sc = device_private(self); | |
100 | struct iobus_attach_args *aa = aux; | 124 | struct iobus_attach_args *aa = aux; | |
101 | int status; | 125 | int status; | |
102 | 126 | |||
103 | sc->sc_dev = self; | 127 | sc->sc_dev = self; | |
104 | sc->sc_regt = aa->aa_bust; | 128 | sc->sc_regt = aa->aa_bust; | |
105 | 129 | |||
106 | aprint_normal("\n"); | 130 | aprint_normal("\n"); | |
107 | 131 | |||
108 | status = bus_space_map(sc->sc_regt, aa->aa_unit->addr, SMI_SIZE, 0, | 132 | status = bus_space_map(sc->sc_regt, aa->aa_unit->addr, SMI_SIZE, 0, | |
109 | &sc->sc_regh); | 133 | &sc->sc_regh); | |
110 | if (status != 0) { | 134 | if (status != 0) { | |
111 | aprint_error_dev(self, "could not map registers\n"); | 135 | aprint_error_dev(self, "could not map registers\n"); | |
112 | return; | 136 | return; | |
113 | } | 137 | } | |
114 | 138 | |||
115 | smi_list = sc; | 139 | octsmi_attach_common(sc, 0); | |
140 | } | |||
141 | ||||
142 | static int | |||
143 | octsmi_fdt_match(device_t parent, struct cfdata *cf, void *aux) | |||
144 | { | |||
145 | struct fdt_attach_args * const faa = aux; | |||
146 | ||||
147 | return of_match_compatible(faa->faa_phandle, compatible); | |||
148 | } | |||
149 | ||||
150 | static void | |||
151 | octsmi_fdt_attach(device_t parent, device_t self, void *aux) | |||
152 | { | |||
153 | struct octsmi_softc *sc = device_private(self); | |||
154 | struct fdt_attach_args * const faa = aux; | |||
155 | const int phandle = faa->faa_phandle; | |||
156 | bus_addr_t addr; | |||
157 | bus_size_t size; | |||
158 | ||||
159 | if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { | |||
160 | aprint_error(": couldn't get registers\n"); | |||
161 | return; | |||
162 | } | |||
163 | ||||
164 | sc->sc_dev = self; | |||
165 | sc->sc_regt = faa->faa_bst; | |||
166 | ||||
167 | if (bus_space_map(sc->sc_regt, addr, size, 0, &sc->sc_regh) != 0) { | |||
168 | aprint_error(": couldn't map registers\n"); | |||
169 | return; | |||
170 | } | |||
171 | ||||
172 | aprint_normal("\n"); | |||
173 | ||||
174 | octsmi_attach_common(sc, phandle); | |||
175 | } | |||
176 | ||||
177 | static void | |||
178 | octsmi_attach_common(struct octsmi_softc *sc, int phandle) | |||
179 | { | |||
180 | struct octsmi_instance *oi; | |||
181 | ||||
182 | oi = kmem_alloc(sizeof(*oi), KM_SLEEP); | |||
183 | oi->sc = sc; | |||
184 | oi->phandle = phandle; | |||
185 | TAILQ_INSERT_TAIL(&octsmi_instances, oi, next); | |||
116 | 186 | |||
117 | const uint64_t magic_value = | 187 | const uint64_t magic_value = | |
118 | SMI_CLK_PREAMBLE | | 188 | SMI_CLK_PREAMBLE | | |
119 | __SHIFTIN(0x4, SMI_CLK_SAMPLE) | /* XXX magic 0x4 */ | 189 | __SHIFTIN(0x4, SMI_CLK_SAMPLE) | /* XXX magic 0x4 */ | |
120 | __SHIFTIN(0x64, SMI_CLK_PHASE); /* XXX magic 0x64 */ | 190 | __SHIFTIN(0x64, SMI_CLK_PHASE); /* XXX magic 0x64 */ | |
121 | _SMI_WR8(sc, SMI_CLK_OFFSET, magic_value); | 191 | _SMI_WR8(sc, SMI_CLK_OFFSET, magic_value); | |
122 | _SMI_WR8(sc, SMI_EN_OFFSET, SMI_EN_EN); | 192 | _SMI_WR8(sc, SMI_EN_OFFSET, SMI_EN_EN); | |
123 | } | 193 | } | |
124 | 194 | |||
125 | int | 195 | int | |
126 | octsmi_read(struct octsmi_softc *sc, int phy_addr, int reg, uint16_t *val) | 196 | octsmi_read(struct octsmi_softc *sc, int phy_addr, int reg, uint16_t *val) | |
127 | { | 197 | { | |
128 | uint64_t smi_rd; | 198 | uint64_t smi_rd; | |
@@ -176,20 +246,27 @@ octsmi_write(struct octsmi_softc *sc, in | @@ -176,20 +246,27 @@ octsmi_write(struct octsmi_softc *sc, in | |||
176 | } | 246 | } | |
177 | if (ISSET(smi_wr, SMI_WR_DAT_PENDING)) { | 247 | if (ISSET(smi_wr, SMI_WR_DAT_PENDING)) { | |
178 | /* XXX log */ | 248 | /* XXX log */ | |
179 | printf("ERROR: octsmi_write(0x%x, 0x%x, 0x%hx) timed out.\n", | 249 | printf("ERROR: octsmi_write(0x%x, 0x%x, 0x%hx) timed out.\n", | |
180 | phy_addr, reg, value); | 250 | phy_addr, reg, value); | |
181 | } | 251 | } | |
182 | 252 | |||
183 | return 0; | 253 | return 0; | |
184 | } | 254 | } | |
185 | 255 | |||
186 | struct octsmi_softc * | 256 | struct octsmi_softc * | |
187 | octsmi_lookup(int phandle, int port) | 257 | octsmi_lookup(int phandle, int port) | |
188 | { | 258 | { | |
189 | struct octsmi_softc *smi; | 259 | struct octsmi_instance *oi; | |
190 | 260 | |||
191 | /* XXX deal with more than one SMI ... */ | 261 | #if notyet | |
192 | smi = smi_list; | 262 | TAILQ_FOREACH(oi, &octsmi_instances, list) { | |
263 | if (oi->phandle == phandle) | |||
264 | return oi->sc; | |||
265 | } | |||
193 | 266 | |||
194 | return smi; | 267 | return NULL; | |
268 | #else | |||
269 | oi = TAILQ_FIRST(&octsmi_instances); | |||
270 | return oi == NULL ? NULL : oi->sc; | |||
271 | #endif | |||
195 | } | 272 | } |
--- src/sys/arch/mips/conf/files.octeon 2020/06/24 12:43:40 1.9
+++ src/sys/arch/mips/conf/files.octeon 2020/07/16 11:49:38 1.10
@@ -1,40 +1,47 @@ | @@ -1,40 +1,47 @@ | |||
1 | # $NetBSD: files.octeon,v 1.9 2020/06/24 12:43:40 simonb Exp $ | 1 | # $NetBSD: files.octeon,v 1.10 2020/07/16 11:49:38 jmcneill Exp $ | |
2 | 2 | |||
3 | file arch/mips/mips/locore_octeon.S | 3 | file arch/mips/mips/locore_octeon.S | |
4 | file arch/mips/mips/bus_dma.c | 4 | file arch/mips/mips/bus_dma.c | |
5 | file arch/mips/mips/mips3_clock.c | 5 | file arch/mips/mips/mips3_clock.c | |
6 | file arch/mips/mips/mips3_clockintr.c | 6 | file arch/mips/mips/mips3_clockintr.c | |
7 | 7 | |||
8 | file arch/mips/cavium/octeon_dma.c | 8 | file arch/mips/cavium/octeon_dma.c | |
9 | file arch/mips/cavium/octeon_intr.c | 9 | file arch/mips/cavium/octeon_intr.c | |
10 | file arch/mips/cavium/octeon_misc.c | 10 | file arch/mips/cavium/octeon_misc.c | |
11 | 11 | |||
12 | device mainbus {} | 12 | file arch/mips/fdt/fdt_dma_machdep.c | |
13 | ||||
14 | device mainbus {}: fdt | |||
13 | attach mainbus at root | 15 | attach mainbus at root | |
14 | file arch/mips/cavium/mainbus.c mainbus | 16 | file arch/mips/cavium/mainbus.c mainbus | |
15 | file arch/mips/cavium/mainbus_octeon1p.c mainbus | 17 | file arch/mips/cavium/mainbus_octeon1p.c mainbus | |
16 | 18 | |||
17 | device cpunode { [core=-1] } | 19 | device cpunode { [core=-1] } | |
18 | attach cpunode at mainbus | 20 | attach cpunode at mainbus | |
19 | 21 | |||
20 | device cpu {} | 22 | device cpu {} | |
21 | attach cpu at cpunode with cpu_cpunode | 23 | attach cpu at cpunode with cpu_cpunode | |
22 | 24 | |||
23 | device wdog: sysmon_wdog | 25 | device wdog: sysmon_wdog | |
24 | attach wdog at cpunode with wdog_cpunode | 26 | attach wdog at cpunode with wdog_cpunode | |
25 | 27 | |||
26 | file arch/mips/cavium/octeon_cpunode.c cpunode | cpu | wdog needs-flag | 28 | file arch/mips/cavium/octeon_cpunode.c cpunode | cpu | wdog needs-flag | |
27 | 29 | |||
30 | # FDT | |||
31 | device octintc | |||
32 | attach octintc at fdt | |||
33 | file arch/mips/cavium/dev/octeon_intc.c octintc | |||
34 | ||||
28 | # I/O Bus | 35 | # I/O Bus | |
29 | 36 | |||
30 | device iobus {} | 37 | device iobus {} | |
31 | attach iobus at mainbus | 38 | attach iobus at mainbus | |
32 | file arch/mips/cavium/octeon_iobus.c iobus | 39 | file arch/mips/cavium/octeon_iobus.c iobus | |
33 | file arch/mips/cavium/octeon1p_iobus.c iobus | 40 | file arch/mips/cavium/octeon1p_iobus.c iobus | |
34 | file arch/mips/cavium/dev/octeon_fpa.c iobus | 41 | file arch/mips/cavium/dev/octeon_fpa.c iobus | |
35 | file arch/mips/cavium/dev/octeon_pow.c iobus | 42 | file arch/mips/cavium/dev/octeon_pow.c iobus | |
36 | file arch/mips/cavium/dev/octeon_fau.c iobus | 43 | file arch/mips/cavium/dev/octeon_fau.c iobus | |
37 | file arch/mips/cavium/dev/octeon_ipd.c iobus | 44 | file arch/mips/cavium/dev/octeon_ipd.c iobus | |
38 | file arch/mips/cavium/dev/octeon_pko.c iobus | 45 | file arch/mips/cavium/dev/octeon_pko.c iobus | |
39 | file arch/mips/cavium/dev/octeon_asx.c iobus | 46 | file arch/mips/cavium/dev/octeon_asx.c iobus | |
40 | 47 | |||
@@ -60,32 +67,34 @@ file arch/mips/cavium/dev/octeon_mpi.c o | @@ -60,32 +67,34 @@ file arch/mips/cavium/dev/octeon_mpi.c o | |||
60 | device octcib {} | 67 | device octcib {} | |
61 | attach octcib at iobus | 68 | attach octcib at iobus | |
62 | file arch/mips/cavium/dev/octeon_cib.c octcib | 69 | file arch/mips/cavium/dev/octeon_cib.c octcib | |
63 | 70 | |||
64 | device octcit {} | 71 | device octcit {} | |
65 | attach octcit at iobus | 72 | attach octcit at iobus | |
66 | file arch/mips/cavium/dev/octeon_cit.c octcit | 73 | file arch/mips/cavium/dev/octeon_cit.c octcit | |
67 | 74 | |||
68 | device octciu {} | 75 | device octciu {} | |
69 | attach octciu at iobus | 76 | attach octciu at iobus | |
70 | file arch/mips/cavium/dev/octeon_ciu.c octciu | 77 | file arch/mips/cavium/dev/octeon_ciu.c octciu | |
71 | 78 | |||
72 | device octsmi {} | 79 | device octsmi {} | |
73 | attach octsmi at iobus | 80 | attach octsmi at iobus with octsmi_iobus | |
74 | file arch/mips/cavium/dev/octeon_smi.c octsmi | 81 | attach octsmi at fdt with octsmi_fdt | |
82 | file arch/mips/cavium/dev/octeon_smi.c octsmi_iobus | octsmi_fdt | |||
75 | 83 | |||
76 | device octpip {} | 84 | device octpip {} | |
77 | attach octpip at iobus | 85 | attach octpip at iobus with octpip_iobus | |
78 | file arch/mips/cavium/dev/octeon_pip.c octpip | 86 | attach octpip at fdt with octpip_fdt | |
87 | file arch/mips/cavium/dev/octeon_pip.c octpip_iobus | octpip_fdt | |||
79 | 88 | |||
80 | device octgmx {} | 89 | device octgmx {} | |
81 | attach octgmx at octpip | 90 | attach octgmx at octpip | |
82 | file arch/mips/cavium/dev/octeon_gmx.c octgmx | 91 | file arch/mips/cavium/dev/octeon_gmx.c octgmx | |
83 | 92 | |||
84 | # On-chip ethernet device(s) | 93 | # On-chip ethernet device(s) | |
85 | device cnmac: ether, ifnet, arp, mii | 94 | device cnmac: ether, ifnet, arp, mii | |
86 | attach cnmac at octgmx | 95 | attach cnmac at octgmx | |
87 | file arch/mips/cavium/dev/if_cnmac.c cnmac | 96 | file arch/mips/cavium/dev/if_cnmac.c cnmac | |
88 | 97 | |||
89 | # CN3xxx/CN5xxx USB | 98 | # CN3xxx/CN5xxx USB | |
90 | attach dwctwo at iobus with octdwctwo | 99 | attach dwctwo at iobus with octdwctwo | |
91 | file arch/mips/cavium/dev/octeon_dwctwo.c octdwctwo | 100 | file arch/mips/cavium/dev/octeon_dwctwo.c octdwctwo |
/* $NetBSD: fdt_dma_machdep.c,v 1.1 2020/07/16 11:49:38 jmcneill Exp $ */
/*-
* Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: fdt_dma_machdep.c,v 1.1 2020/07/16 11:49:38 jmcneill Exp $");
#define _MIPS_BUS_DMA_PRIVATE
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/kmem.h>
#include <dev/fdt/fdtvar.h>
static struct mips_bus_dma_tag fdtbus_dma_tag = {
._cookie = NULL,
._wbase = 0,
._bounce_alloc_lo = 0,
._bounce_alloc_hi = 0,
._dmamap_ops = _BUS_DMAMAP_OPS_INITIALIZER,
._dmamem_ops = _BUS_DMAMEM_OPS_INITIALIZER,
._dmatag_ops = _BUS_DMATAG_OPS_INITIALIZER,
};
bus_dma_tag_t
fdtbus_dma_tag_create(int phandle, const struct fdt_dma_range *ranges,
u_int nranges)
{
bus_dma_tag_t newtag;
bus_addr_t min_addr, max_addr;
int error;
if (nranges == 0)
return &fdtbus_dma_tag;
KASSERT(nranges == 1);
KASSERT(ranges[0].dr_sysbase == ranges[0].dr_busbase);
min_addr = ranges[0].dr_sysbase;
max_addr = min_addr + ranges[0].dr_len - 1;
error = bus_dmatag_subregion(&fdtbus_dma_tag, min_addr, max_addr,
&newtag, 0);
KASSERT(error == 0);
return newtag;
}