 @@ -1,38 +1,38 @@
-/* $NetBSD: piixpm.c,v 1.54 2019/07/13 09:24:17 msaitoh Exp $ */
+/* $NetBSD: piixpm.c,v 1.54.2.1 2020/07/16 12:39:11 martin Exp $ */
 /*	$OpenBSD: piixpm.c,v 1.39 2013/10/01 20:06:02 sf Exp $	*/
 /*
  * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 /*
  * Intel PIIX and compatible Power Management controller driver.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.54 2019/07/13 09:24:17 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.54.2.1 2020/07/16 12:39:11 martin Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/mutex.h>
 #include <sys/proc.h>
 #include <sys/bus.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 @@ -60,42 +60,46 @@ __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1
 	    ((PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_ATI_SB600_SMB) &&	      \
 		((sc)->sc_rev >= 0x40)))
 #define PIIXPM_IS_HUDSON(sc)						      \
 	((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) &&			      \
 	    (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_HUDSON_SMB))
 #define PIIXPM_IS_KERNCZ(sc)						      \
 	((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) &&			      \
 	    (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_KERNCZ_SMB))
 #define PIIXPM_IS_FCHGRP(sc)	(PIIXPM_IS_HUDSON(sc) || PIIXPM_IS_KERNCZ(sc))
 #define PIIX_SB800_TIMEOUT 500
 struct piixpm_smbus {
 	int			sda;
 	int			sda_save;
 	struct			piixpm_softc *softc;
 };
 struct piixpm_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_iot;
 #define	sc_pm_iot sc_iot
 #define sc_smb_iot sc_iot
 	bus_space_handle_t	sc_pm_ioh;
 	bus_space_handle_t	sc_sb800_ioh;
 	bus_space_handle_t	sc_smb_ioh;
 	void *			sc_smb_ih;
 	int			sc_poll;
 	bool			sc_sb800_selen; /* Use SMBUS0SEL */
 	pci_chipset_tag_t	sc_pc;
 	pcitag_t		sc_pcitag;
 	pcireg_t		sc_id;
 	pcireg_t		sc_rev;
 	int			sc_numbusses;
 	device_t		sc_i2c_device[4];
 	struct piixpm_smbus	sc_busses[4];
 	struct i2c_controller	sc_i2c_tags[4];
 	kmutex_t		sc_i2c_mutex;
 	struct {
 @@ -109,28 +113,28 @@ struct piixpm_softc {
 	pcireg_t		sc_devact[2];
 };
 static int	piixpm_match(device_t, cfdata_t, void *);
 static void	piixpm_attach(device_t, device_t, void *);
 static int	piixpm_rescan(device_t, const char *, const int *);
 static void	piixpm_chdet(device_t, device_t);
 static bool	piixpm_suspend(device_t, const pmf_qual_t *);
 static bool	piixpm_resume(device_t, const pmf_qual_t *);
 static int	piixpm_sb800_init(struct piixpm_softc *);
 static void	piixpm_csb5_reset(void *);
-static int	piixpm_i2c_acquire_bus(void *, int);
+static int	piixpm_i2c_sb800_acquire_bus(void *, int);
-static void	piixpm_i2c_release_bus(void *, int);
+static void	piixpm_i2c_sb800_release_bus(void *, int);
 static int	piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *,
     size_t, void *, size_t, int);
 static int	piixpm_intr(void *);
 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc),
     piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0);
 static int
 piixpm_match(device_t parent, cfdata_t match, void *aux)
+{
 	struct pci_attach_args *pa;
 @@ -221,35 +225,30 @@ piixpm_attach(device_t parent, device_t
 	/*
 	 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M.
 	 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20
 	 * in the "Specification update" (document #297738).
 	 */
 	acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, PIIX_PM_PMTMR,
 	    (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0);
 nopowermanagement:
 	/* SB800 rev 0x40+, AMD HUDSON and newer need special initialization */
 	if (PIIXPM_IS_FCHGRP(sc) || PIIXPM_IS_SB800GRP(sc)) {
 		if (piixpm_sb800_init(sc) == 0) {
 			sc->sc_numbusses = 4;
 			/* Read configuration */
-			conf = pci_conf_read(pa->pa_pc, pa->pa_tag,
+			conf = bus_space_read_1(sc->sc_iot,
-			    SB800_SMB_HOSTC);
+			    sc->sc_smb_ioh, SB800_SMB_HOSTC);
-			DPRINTF(("%s: conf 0x%08x\n", device_xname(self),
+			usesmi = ((conf & SB800_SMB_HOSTC_IRQ) == 0);
 				conf));
 			usesmi = conf & SB800_SMB_HOSTC_SMI;
 			goto setintr;
+		}
 		aprint_normal_dev(self, "SMBus initialization failed\n");
 		return;
+	}
 	/* Read configuration */
 	conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC);
 	DPRINTF(("%s: conf 0x%08x\n", device_xname(self), conf));
 	if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) {
 		aprint_normal_dev(self, "SMBus disabled\n");
 		return;
 @@ -318,37 +317,44 @@ piixpm_iicbus_print(void *aux, const cha
 static int
 piixpm_rescan(device_t self, const char *ifattr, const int *flags)
+{
 	struct piixpm_softc *sc = device_private(self);
 	struct i2cbus_attach_args iba;
 	int i;
 	if (!ifattr_match(ifattr, "i2cbus"))
 		return 0;
 	/* Attach I2C bus */
 	for (i = 0; i < sc->sc_numbusses; i++) {
 		struct i2c_controller *tag = &sc->sc_i2c_tags[i];
 		if (sc->sc_i2c_device[i])
 			continue;
 		sc->sc_busses[i].sda = i;
 		sc->sc_busses[i].softc = sc;
-		sc->sc_i2c_tags[i].ic_cookie = &sc->sc_busses[i];
+		tag->ic_cookie = &sc->sc_busses[i];
-		sc->sc_i2c_tags[i].ic_acquire_bus = piixpm_i2c_acquire_bus;
+		if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_FCHGRP(sc)) {
-		sc->sc_i2c_tags[i].ic_release_bus = piixpm_i2c_release_bus;
+			tag->ic_acquire_bus = piixpm_i2c_sb800_acquire_bus;
-		sc->sc_i2c_tags[i].ic_exec = piixpm_i2c_exec;
+			tag->ic_release_bus = piixpm_i2c_sb800_release_bus;
 		} else {
 			tag->ic_acquire_bus = NULL;
 			tag->ic_release_bus = NULL;
+		}
 		tag->ic_exec = piixpm_i2c_exec;
 		memset(&iba, 0, sizeof(iba));
 		iba.iba_type = I2C_TYPE_SMBUS;
-		iba.iba_tag = &sc->sc_i2c_tags[i];
+		iba.iba_tag = tag;
 		sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba,
 		    piixpm_iicbus_print);
+	}
 	return 0;
+}
 static void
 piixpm_chdet(device_t self, device_t child)
+{
 	struct piixpm_softc *sc = device_private(self);
 	int i;
 @@ -391,68 +397,77 @@ piixpm_resume(device_t dv, const pmf_qua
  * Extract SMBus base address from SB800 Power Management (PM) registers.
  * The PM registers can be accessed either through indirect I/O (CD6/CD7) or
  * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only
  * called once it uses indirect I/O for simplicity.
  */
 static int
 piixpm_sb800_init(struct piixpm_softc *sc)
+{
 	bus_space_tag_t iot = sc->sc_iot;
 	bus_space_handle_t ioh;	/* indirect I/O handle */
 	uint16_t val, base_addr;
 	bool enabled;
 	if (PIIXPM_IS_KERNCZ(sc) ||
 	    (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f)))
 		sc->sc_numbusses = 2;
 	else
 		sc->sc_numbusses = 4;
 	/* Fetch SMB base address */
 	if (bus_space_map(iot,
 	    SB800_INDIRECTIO_BASE, SB800_INDIRECTIO_SIZE, 0, &ioh)) {
 		device_printf(sc->sc_dev, "couldn't map indirect I/O space\n");
 		return EBUSY;
+	}
 	if (PIIXPM_IS_FCHGRP(sc)) {
 		bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
 		    AMDFCH41_PM_DECODE_EN0);
 		val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA);
 		enabled = val & AMDFCH41_SMBUS_EN;
 		if (!enabled)
 			return ENOENT;
 		bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
 		    AMDFCH41_PM_DECODE_EN1);
 		val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8;
 		base_addr = val;
 	} else {
 		uint8_t data;
 		bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
 		    SB800_PM_SMBUS0EN_LO);
 		val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA);
 		enabled = val & SB800_PM_SMBUS0EN_ENABLE;
 		if (!enabled)
 			return ENOENT;
 		bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
 		    SB800_PM_SMBUS0EN_HI);
 		val |= bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8;
 		base_addr = val & SB800_PM_SMBUS0EN_BADDR;
 		bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
 		    SB800_PM_SMBUS0SELEN);
-		bus_space_write_1(iot, ioh, SB800_INDIRECTIO_DATA,
+		data = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA);
-		    SB800_PM_SMBUS0EN_ENABLE);
+		if ((data & SB800_PM_USE_SMBUS0SEL) != 0)
 			sc->sc_sb800_selen = true;
+	}
 	sc->sc_sb800_ioh = ioh;
 	aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr);
 	if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr),
-	    PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
+	    SB800_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
 		aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n");
 		return EBUSY;
+	}
 	return 0;
+}
 static void
 piixpm_csb5_reset(void *arg)
+{
 	struct piixpm_softc *sc = arg;
 	pcireg_t base, hostc, pmbase;
 @@ -462,71 +477,125 @@ piixpm_csb5_reset(void *arg)
 	pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE);
 	pmbase |= PIIX_PM_BASE_CSB5_RESET;
 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase);
 	pmbase &= ~PIIX_PM_BASE_CSB5_RESET;
 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase);
 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base);
 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc);
 	(void) tsleep(&sc, PRIBIO, "csb5reset", hz/2);
+}
 static int
-piixpm_i2c_acquire_bus(void *cookie, int flags)
+piixpm_i2c_sb800_acquire_bus(void *cookie, int flags)
+{
 	struct piixpm_smbus *smbus = cookie;
 	struct piixpm_softc *sc = smbus->softc;
 	uint8_t sctl, old_sda, index, mask, reg;
 	int i;
 	if (!cold)
 		mutex_enter(&sc->sc_i2c_mutex);
-	if (PIIXPM_IS_KERNCZ(sc)) {
+	sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC);
-		bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
+	for (i = 0; i < PIIX_SB800_TIMEOUT; i++) {
-		    SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX);
+		/* Try to acquire the host semaphore */
-		bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
+		sctl &= ~PIIX_SMB_SC_SEMMASK;
-		    SB800_INDIRECTIO_DATA, smbus->sda << 3);
+		bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC,
-	} else if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_HUDSON(sc)) {
+		    sctl | PIIX_SMB_SC_HOSTSEM);
 		bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
-		    SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL);
+		sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh,
 		    PIIX_SMB_SC);
 		if ((sctl & PIIX_SMB_SC_HOSTSEM) != 0)
 			break;
 		delay(1000);
+	}
 	if (i >= PIIX_SB800_TIMEOUT) {
 		device_printf(sc->sc_dev,
 		    "Failed to acquire the host semaphore\n");
 		return -1;
+	}
 	if (PIIXPM_IS_KERNCZ(sc) ||
 	    (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) {
 		index = AMDFCH41_PM_PORT_INDEX;
 		mask = AMDFCH41_SMBUS_PORTMASK;
 	} else if (sc->sc_sb800_selen) {
 		index = SB800_PM_SMBUS0SEL;
 		mask = SB800_PM_SMBUS0_MASK_E;
 	} else {
 		index = SB800_PM_SMBUS0EN_LO;
 		mask = SB800_PM_SMBUS0_MASK_C;
+	}
 	bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
 	    SB800_INDIRECTIO_INDEX, index);
 	reg = bus_space_read_1(sc->sc_iot, sc->sc_sb800_ioh,
 	    SB800_INDIRECTIO_DATA);
 	old_sda = __SHIFTOUT(reg, mask);
 	if (smbus->sda != old_sda) {
 		reg &= ~mask;
 		reg |= __SHIFTIN(smbus->sda, mask);
 		bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
-		    SB800_INDIRECTIO_DATA, smbus->sda << 1);
+		    SB800_INDIRECTIO_DATA, reg);
+	}
 	/* Save the old port number */
 	smbus->sda_save = old_sda;
 	return 0;
+}
 static void
-piixpm_i2c_release_bus(void *cookie, int flags)
+piixpm_i2c_sb800_release_bus(void *cookie, int flags)
+{
 	struct piixpm_smbus *smbus = cookie;
 	struct piixpm_softc *sc = smbus->softc;
 	uint8_t sctl, index, mask, reg;
-	if (PIIXPM_IS_KERNCZ(sc)) {
+	if (PIIXPM_IS_KERNCZ(sc) ||
-		bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
+	    (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) {
-		    SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX);
+		index = AMDFCH41_PM_PORT_INDEX;
-		bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
+		mask = AMDFCH41_SMBUS_PORTMASK;
-		    SB800_INDIRECTIO_DATA, 0);
+	} else if (sc->sc_sb800_selen) {
-	} else if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_HUDSON(sc)) {
+		index = SB800_PM_SMBUS0SEL;
-		/*
+		mask = SB800_PM_SMBUS0_MASK_E;
-		 * HP Microserver hangs after reboot if not set to SDA0.
+	} else {
-		 * Also add shutdown hook?
+		index = SB800_PM_SMBUS0EN_LO;
-		 */
+		mask = SB800_PM_SMBUS0_MASK_C;
 		bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
 		    SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL);
 	bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
 	    SB800_INDIRECTIO_INDEX, index);
 	if (smbus->sda != smbus->sda_save) {
 		/* Restore the port number */
 		reg = bus_space_read_1(sc->sc_iot, sc->sc_sb800_ioh,
 		    SB800_INDIRECTIO_DATA);
 		reg &= ~mask;
 		reg |= __SHIFTIN(smbus->sda_save, mask);
 		bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
-		    SB800_INDIRECTIO_DATA, 0);
+		    SB800_INDIRECTIO_DATA, reg);
+	}
 	/* Relase the host semaphore */
 	sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC);
 	sctl &= ~PIIX_SMB_SC_SEMMASK;
 	bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC,
 	    sctl | PIIX_SMB_SC_CLRHOSTSEM);
 	if (!cold)
 		mutex_exit(&sc->sc_i2c_mutex);
+}
 static int
 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr,
     const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
+{
 	struct piixpm_smbus *smbus = cookie;
 	struct piixpm_softc *sc = smbus->softc;
 	const uint8_t *b;
 	uint8_t ctl = 0, st;
 	int retries;

 @@ -1,14 +1,14 @@
-/* $NetBSD: piixpmreg.h,v 1.8 2019/07/13 09:24:17 msaitoh Exp $ */
+/* $NetBSD: piixpmreg.h,v 1.8.2.1 2020/07/16 12:39:11 martin Exp $ */
 /*	$OpenBSD: piixreg.h,v 1.3 2006/01/03 22:39:03 grange Exp $	*/
 /*-
  * Copyright (c) 2016 Andriy Gapon <avg@FreeBSD.org>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
 @@ -56,27 +56,27 @@
  * Power management registers.
  */
 /* PCI configuration registers */
 #define PIIX_PM_BASE	0x40		/* Power management base address */
 #define PIIX_PM_BASE_CSB5_RESET	0x10		/* CSB5 PM reset */
 #define PIIX_DEVACTA	0x54		/* Device activity A (function 3) */
 #define PIIX_DEVACTB	0x58		/* Device activity B (function 3) */
 #define PIIX_PMREGMISC	0x80		/* Misc. Power management */
 #define PIIX_SMB_BASE	0x90		/* SMBus base address */
 #define PIIX_SMB_HOSTC	0xd0		/* SMBus host configuration */
 #define PIIX_SMB_HOSTC_HSTEN	(1 << 16)	/* enable host controller */
 #define PIIX_SMB_HOSTC_SMI	(0 << 17)	/* SMI */
-#define PIIX_SMB_HOSTC_IRQ	(4 << 17)	/* IRQ */
+#define PIIX_SMB_HOSTC_IRQ	(4 << 17)	/* IRQ 9 */
 #define PIIX_SMB_HOSTC_INTMASK	(7 << 17)
 /* SMBus I/O registers */
 #define PIIX_SMB_HS	0x00		/* host status */
 #define PIIX_SMB_HS_BUSY	(1 << 0)	/* running a command */
 #define PIIX_SMB_HS_INTR	(1 << 1)	/* command completed */
 #define PIIX_SMB_HS_DEVERR	(1 << 2)	/* command error */
 #define PIIX_SMB_HS_BUSERR	(1 << 3)	/* transaction collision */
 #define PIIX_SMB_HS_FAILED	(1 << 4)	/* failed bus transaction */
 #define PIIX_SMB_HS_BITS	"\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED"
 #define PIIX_SMB_HC	0x02		/* host control */
 #define PIIX_SMB_HC_INTREN	(1 << 0)	/* enable interrupts */
 #define PIIX_SMB_HC_KILL	(1 << 1)	/* kill current transaction */
 @@ -85,65 +85,80 @@
 #define PIIX_SMB_HC_CMD_BDATA	(2 << 2)	/* BYTE DATA command */
 #define PIIX_SMB_HC_CMD_WDATA	(3 << 2)	/* WORD DATA command */
 #define PIIX_SMB_HC_CMD_BLOCK	(5 << 2)	/* BLOCK command */
 #define PIIX_SMB_HC_START	(1 << 6)	/* start transaction */
 #define PIIX_SMB_HCMD	0x03		/* host command */
 #define PIIX_SMB_TXSLVA	0x04		/* transmit slave address */
 #define PIIX_SMB_TXSLVA_READ	(1 << 0)	/* read direction */
 #define PIIX_SMB_TXSLVA_ADDR(x)	(((x) & 0x7f) << 1) /* 7-bit address */
 #define PIIX_SMB_HD0	0x05		/* host data 0 */
 #define PIIX_SMB_HD1	0x06		/* host data 1 */
 #define PIIX_SMB_HBDB	0x07		/* host block data byte */
 #define PIIX_SMB_SC	0x08		/* slave control */
 #define PIIX_SMB_SC_ALERTEN	(1 << 3)	/* enable SMBALERT# */
 #define PIIX_SMB_SC_HOSTSEM	(1 << 4)	/* (W1S) HostSemaphore */
 #define PIIX_SMB_SC_CLRHOSTSEM	(1 << 5)	/* (W1C) ClrHostSemaphore */
 #define PIIX_SMB_SC_ECSEM	(1 << 6)	/* (W1S) EcSemaphore */
 #define PIIX_SMB_SC_CLRECSEM	(1 << 7)	/* (W1C) ClrEcSemaphore */
 #define PIIX_SMB_SC_SEMMASK	0xf0		/* Semaphore bits */
 /* Power management I/O registers */
 #define PIIX_PM_PMTMR	0x08		/* power management timer */
 /* Misc */
 #define PIIX_PM_SIZE	0x38		/* Power management I/O space size */
 #define PIIX_SMB_SIZE	0x10		/* SMBus I/O space size */
 /*
  * AMD SB800 and compatible chipset's configuration registers.
  * See SB8xx RRG 2.3.3, etc.
  */
 /* In the I/O area */
 #define SB800_INDIRECTIO_BASE	0xcd6
 #define SB800_INDIRECTIO_SIZE	2
 #define SB800_INDIRECTIO_INDEX	0
 #define SB800_INDIRECTIO_DATA	1
 #define SB800_PM_SMBUS0EN_LO	0x2c
 #define SB800_PM_SMBUS0EN_HI	0x2d
-#define SB800_PM_SMBUS0SEL	0x2e
+#define SB800_PM_SMBUS0EN_ENABLE __BIT(0)     /* Function enable */
-#define SB800_PM_SMBUS0SELEN	0x2f
+#define SB800_PM_SMBUS0_MASK_C	__BITS(2, 1)  /* Port mask (PMIO2C) */
 #define SB800_PM_SMBUS0EN_BADDR	__BITS(15, 5) /* Base address */
 #define SB800_PM_SMBUS0EN_ENABLE 0x0001
-#define SB800_PM_SMBUS0EN_BADDR	0xffe0
+#define SB800_PM_SMBUS0SEL	0x2e
 #define SB800_PM_SMBUS0_MASK_E	__BITS(2, 1)  /* Port mask (PMIO2E) */
 #define SB800_PM_SMBUS0SELEN	0x2f
 #define SB800_PM_USE_SMBUS0SEL	__BIT(0) /*
 					  * If the bit is set, SMBUS0SEL is
 					  * used to select the port.
 					  */
-/* In the PCI config space */
+/* In the SMBus I/O space */
 #define SB800_SMB_HOSTC		0x10	/* I2C bus configuration */
-#define SB800_SMB_HOSTC_SMI	(1 << 0)	/* SMI */
+#define SB800_SMB_HOSTC_IRQ	(1 << 0)	/* 0:SMI 1:IRQ */
 /* Misc */
 #define SB800_SMB_SIZE	0x11		/* SMBus I/O space size */
 /*
  * Newer FCH registers in the PMIO space.
  * See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04.
  */
 #define AMDFCH41_PM_DECODE_EN0		0x00
 #define		AMDFCH41_SMBUS_EN	0x10
 #define		AMDFCH41_WDT_EN		0x80
 #define AMDFCH41_PM_DECODE_EN1		0x01
 #define AMDFCH41_PM_PORT_INDEX		0x02
 #define 	AMDFCH41_SMBUS_PORTMASK	0x18
 #define	AMDFCH41_PM_DECODE_EN3		0x03
 #define		AMDFCH41_WDT_RES_MASK	0x03
 #define		AMDFCH41_WDT_RES_32US	0x00
 #define		AMDFCH41_WDT_RES_10MS	0x01
 #define		AMDFCH41_WDT_RES_100MS	0x02
 #define		AMDFCH41_WDT_RES_1S	0x03
 #define		AMDFCH41_WDT_EN_MASK	0x0c
 #define		AMDFCH41_WDT_ENABLE	0x00
 #define	AMDFCH41_PM_ISA_CTRL		0x04
 #define		AMDFCH41_MMIO_EN	0x02
 #endif	/* !_DEV_PCI_PIIXREG_H_ */