Fri Jul 17 08:06:02 2020 UTC ()
Don't use a reserved value for the USB endian CSR selects and
enable octxhci_uctl_init().  Between these, USB works without
needing a "usb start" from u-boot.

XXX: Note the port power enable goop is still disabled until
we get a GPIO driver.


(simonb)
diff -r1.1 -r1.2 src/sys/arch/mips/cavium/dev/octeon_xhci.c
diff -r1.1 -r1.2 src/sys/arch/mips/cavium/dev/octeon_xhcireg.h
cvs diff -r1.1 -r1.2 src/sys/arch/mips/cavium/dev/octeon_xhci.c (expand / switch to unified diff)

--- src/sys/arch/mips/cavium/dev/octeon_xhci.c 2020/07/16 21:34:52 1.1
+++ src/sys/arch/mips/cavium/dev/octeon_xhci.c 2020/07/17 08:06:02 1.2
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: octeon_xhci.c,v 1.1 2020/07/16 21:34:52 jmcneill Exp $ */ 1/* $NetBSD: octeon_xhci.c,v 1.2 2020/07/17 08:06:02 simonb Exp $ */
2/* $OpenBSD: octxhci.c,v 1.4 2019/09/29 04:32:23 visa Exp $ */ 2/* $OpenBSD: octxhci.c,v 1.4 2019/09/29 04:32:23 visa Exp $ */
3 3
4/* 4/*
5 * Copyright (c) 2017 Visa Hankala 5 * Copyright (c) 2017 Visa Hankala
6 * Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca> 6 * Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca>
7 * 7 *
8 * Permission to use, copy, modify, and distribute this software for any 8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above 9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies. 10 * copyright notice and this permission notice appear in all copies.
11 * 11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -141,27 +141,26 @@ octxhci_attach(device_t parent, device_t @@ -141,27 +141,26 @@ octxhci_attach(device_t parent, device_t
141 } 141 }
142 clock_type_ss = fdtbus_get_string(phandle, "refclk-type-ss"); 142 clock_type_ss = fdtbus_get_string(phandle, "refclk-type-ss");
143 if (clock_type_ss == NULL) { 143 if (clock_type_ss == NULL) {
144 aprint_error(": couldn't get refclk-type-ss property\n"); 144 aprint_error(": couldn't get refclk-type-ss property\n");
145 return; 145 return;
146 } 146 }
147 147
148 clock_sel = 0; 148 clock_sel = 0;
149 if (strcmp(clock_type_ss, "dlmc_ref_clk1") == 0) 149 if (strcmp(clock_type_ss, "dlmc_ref_clk1") == 0)
150 clock_sel |= 1; 150 clock_sel |= 1;
151 if (strcmp(clock_type_hs, "pll_ref_clk") == 0) 151 if (strcmp(clock_type_hs, "pll_ref_clk") == 0)
152 clock_sel |= 2; 152 clock_sel |= 2;
153 153
154 if (0) 
155 octxhci_uctl_init(osc, clock_freq, clock_sel); 154 octxhci_uctl_init(osc, clock_freq, clock_sel);
156 155
157 if (octxhci_dwc3_init(sc) != 0) { 156 if (octxhci_dwc3_init(sc) != 0) {
158 /* Error message has been printed already. */ 157 /* Error message has been printed already. */
159 return; 158 return;
160 } 159 }
161 160
162 if (!fdtbus_intr_str(child, 0, intrstr, sizeof(intrstr))) { 161 if (!fdtbus_intr_str(child, 0, intrstr, sizeof(intrstr))) {
163 aprint_error_dev(self, "failed to decode interrupt\n"); 162 aprint_error_dev(self, "failed to decode interrupt\n");
164 return; 163 return;
165 } 164 }
166 165
167 ih = fdtbus_intr_establish(child, 0, IPL_USB, FDT_INTR_MPSAFE, 166 ih = fdtbus_intr_establish(child, 0, IPL_USB, FDT_INTR_MPSAFE,
@@ -320,28 +319,28 @@ octxhci_uctl_init(struct octxhci_softc * @@ -320,28 +319,28 @@ octxhci_uctl_init(struct octxhci_softc *
320 val |= XCTL_CTL_CSCLK_EN; 319 val |= XCTL_CTL_CSCLK_EN;
321 XCTL_WR_8(sc, XCTL_CTL, val); 320 XCTL_WR_8(sc, XCTL_CTL, val);
322 321
323 /* Take the PHY out of reset. */ 322 /* Take the PHY out of reset. */
324 val = XCTL_RD_8(sc, XCTL_CTL); 323 val = XCTL_RD_8(sc, XCTL_CTL);
325 val &= ~XCTL_CTL_UPHY_RST; 324 val &= ~XCTL_CTL_UPHY_RST;
326 XCTL_WR_8(sc, XCTL_CTL, val); 325 XCTL_WR_8(sc, XCTL_CTL, val);
327 (void)XCTL_RD_8(sc, XCTL_CTL); 326 (void)XCTL_RD_8(sc, XCTL_CTL);
328 327
329 /* Fix endianess. */ 328 /* Fix endianess. */
330 val = XCTL_RD_8(sc, XCTL_SHIM_CFG); 329 val = XCTL_RD_8(sc, XCTL_SHIM_CFG);
331 val &= ~XCTL_SHIM_CFG_CSR_BYTE_SWAP; 330 val &= ~XCTL_SHIM_CFG_CSR_BYTE_SWAP;
332 val &= ~XCTL_SHIM_CFG_DMA_BYTE_SWAP; 331 val &= ~XCTL_SHIM_CFG_DMA_BYTE_SWAP;
333 val |= 3ull << XCTL_SHIM_CFG_CSR_BYTE_SWAP_SHIFT; 332 val |= __SHIFTIN(XCTL_SHIM_ENDIAN_BIG, XCTL_SHIM_CFG_DMA_BYTE_SWAP);
334 val |= 1ull << XCTL_SHIM_CFG_DMA_BYTE_SWAP_SHIFT; 333 val |= __SHIFTIN(XCTL_SHIM_ENDIAN_BIG, XCTL_SHIM_CFG_CSR_BYTE_SWAP);
335 XCTL_WR_8(sc, XCTL_SHIM_CFG, val); 334 XCTL_WR_8(sc, XCTL_SHIM_CFG, val);
336 (void)XCTL_RD_8(sc, XCTL_SHIM_CFG); 335 (void)XCTL_RD_8(sc, XCTL_SHIM_CFG);
337} 336}
338 337
339int 338int
340octxhci_dwc3_init(struct xhci_softc *sc) 339octxhci_dwc3_init(struct xhci_softc *sc)
341{ 340{
342 bus_space_handle_t ioh = sc->sc_ioh; 341 bus_space_handle_t ioh = sc->sc_ioh;
343 uint32_t rev; 342 uint32_t rev;
344 uint32_t val; 343 uint32_t val;
345 344
346 val = bus_space_read_4(sc->sc_iot, ioh, DWC3_GSNPSID); 345 val = bus_space_read_4(sc->sc_iot, ioh, DWC3_GSNPSID);
347 if ((val & 0xffff0000u) != 0x55330000u) { 346 if ((val & 0xffff0000u) != 0x55330000u) {
cvs diff -r1.1 -r1.2 src/sys/arch/mips/cavium/dev/octeon_xhcireg.h (expand / switch to unified diff)

--- src/sys/arch/mips/cavium/dev/octeon_xhcireg.h 2020/07/16 21:34:52 1.1
+++ src/sys/arch/mips/cavium/dev/octeon_xhcireg.h 2020/07/17 08:06:02 1.2
@@ -49,26 +49,30 @@ @@ -49,26 +49,30 @@
49#define XCTL_CTL_UPHY_RST 0x0000000000000004ull 49#define XCTL_CTL_UPHY_RST 0x0000000000000004ull
50#define XCTL_CTL_UAHC_RST 0x0000000000000002ull 50#define XCTL_CTL_UAHC_RST 0x0000000000000002ull
51#define XCTL_CTL_UCTL_RST 0x0000000000000001ull 51#define XCTL_CTL_UCTL_RST 0x0000000000000001ull
52 52
53#define XCTL_HOST_CFG 0xe0 53#define XCTL_HOST_CFG 0xe0
54#define XCTL_HOST_CFG_PPC_EN 0x0000000002000000ull 54#define XCTL_HOST_CFG_PPC_EN 0x0000000002000000ull
55#define XCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN 0x0000000001000000ull 55#define XCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN 0x0000000001000000ull
56 56
57#define XCTL_SHIM_CFG 0xe8 57#define XCTL_SHIM_CFG 0xe8
58#define XCTL_SHIM_CFG_DMA_BYTE_SWAP 0x0000000000000300ull 58#define XCTL_SHIM_CFG_DMA_BYTE_SWAP 0x0000000000000300ull
59#define XCTL_SHIM_CFG_DMA_BYTE_SWAP_SHIFT 8 59#define XCTL_SHIM_CFG_DMA_BYTE_SWAP_SHIFT 8
60#define XCTL_SHIM_CFG_CSR_BYTE_SWAP 0x0000000000000003ull 60#define XCTL_SHIM_CFG_CSR_BYTE_SWAP 0x0000000000000003ull
61#define XCTL_SHIM_CFG_CSR_BYTE_SWAP_SHIFT 0 61#define XCTL_SHIM_CFG_CSR_BYTE_SWAP_SHIFT 0
 62#define XCTL_SHIM_ENDIAN_LITTLE 0 /* A-B-C-D-E-F-G-H -> A-B-C-D-E-F-G-H */
 63#define XCTL_SHIM_ENDIAN_BIG 1 /* A-B-C-D-E-F-G-H -> H-G-F-E-D-C-B-A */
 64#define XCTL_SHIM_ENDIAN_RSVD2 2 /* A-B-C-D-E-F-G-H -> D-C-B-A-H-G-F-E */
 65#define XCTL_SHIM_ENDIAN_RSVD3 3 /* A-B-C-D-E-F-G-H -> E-F-G-H-A-B-C-D */
62 66
63/* 67/*
64 * DWC3 core control registers. 68 * DWC3 core control registers.
65 * These are relative to the xHCI register space. 69 * These are relative to the xHCI register space.
66 */ 70 */
67 71
68#define DWC3_GCTL 0xc110 72#define DWC3_GCTL 0xc110
69#define DWC3_GCTL_PRTCAP_MASK 0x00003000u 73#define DWC3_GCTL_PRTCAP_MASK 0x00003000u
70#define DWC3_GCTL_PRTCAP_HOST 0x00001000u 74#define DWC3_GCTL_PRTCAP_HOST 0x00001000u
71#define DWC3_GCTL_SOFITPSYNC 0x00000400u 75#define DWC3_GCTL_SOFITPSYNC 0x00000400u
72#define DWC3_GCTL_SCALEDOWN_MASK 0x00000030u 76#define DWC3_GCTL_SCALEDOWN_MASK 0x00000030u
73#define DWC3_GCTL_DISSCRAMBLE 0x00000004u 77#define DWC3_GCTL_DISSCRAMBLE 0x00000004u
74#define DWC3_GCTL_DSBLCLKGTNG 0x00000001u 78#define DWC3_GCTL_DSBLCLKGTNG 0x00000001u