| @@ -1,654 +1,665 @@ | | | @@ -1,654 +1,665 @@ |
1 | /* $NetBSD: octeon_intr.c,v 1.16 2020/07/17 17:57:16 jmcneill Exp $ */ | | 1 | /* $NetBSD: octeon_intr.c,v 1.17 2020/07/17 19:40:47 jmcneill Exp $ */ |
2 | /* | | 2 | /* |
3 | * Copyright 2001, 2002 Wasabi Systems, Inc. | | 3 | * Copyright 2001, 2002 Wasabi Systems, Inc. |
4 | * All rights reserved. | | 4 | * All rights reserved. |
5 | * | | 5 | * |
6 | * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. | | 6 | * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. |
7 | * | | 7 | * |
8 | * Redistribution and use in source and binary forms, with or without | | 8 | * Redistribution and use in source and binary forms, with or without |
9 | * modification, are permitted provided that the following conditions | | 9 | * modification, are permitted provided that the following conditions |
10 | * are met: | | 10 | * are met: |
11 | * 1. Redistributions of source code must retain the above copyright | | 11 | * 1. Redistributions of source code must retain the above copyright |
12 | * notice, this list of conditions and the following disclaimer. | | 12 | * notice, this list of conditions and the following disclaimer. |
13 | * 2. Redistributions in binary form must reproduce the above copyright | | 13 | * 2. Redistributions in binary form must reproduce the above copyright |
14 | * notice, this list of conditions and the following disclaimer in the | | 14 | * notice, this list of conditions and the following disclaimer in the |
15 | * documentation and/or other materials provided with the distribution. | | 15 | * documentation and/or other materials provided with the distribution. |
16 | * 3. All advertising materials mentioning features or use of this software | | 16 | * 3. All advertising materials mentioning features or use of this software |
17 | * must display the following acknowledgement: | | 17 | * must display the following acknowledgement: |
18 | * This product includes software developed for the NetBSD Project by | | 18 | * This product includes software developed for the NetBSD Project by |
19 | * Wasabi Systems, Inc. | | 19 | * Wasabi Systems, Inc. |
20 | * 4. The name of Wasabi Systems, Inc. may not be used to endorse | | 20 | * 4. The name of Wasabi Systems, Inc. may not be used to endorse |
21 | * or promote products derived from this software without specific prior | | 21 | * or promote products derived from this software without specific prior |
22 | * written permission. | | 22 | * written permission. |
23 | * | | 23 | * |
24 | * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND | | 24 | * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND |
25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | | 25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
26 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | | 26 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
27 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC | | 27 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC |
28 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 28 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | | 30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | | 31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | | 32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | | 33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
34 | * POSSIBILITY OF SUCH DAMAGE. | | 34 | * POSSIBILITY OF SUCH DAMAGE. |
35 | */ | | 35 | */ |
36 | | | 36 | |
37 | /* | | 37 | /* |
38 | * Platform-specific interrupt support for the MIPS Malta. | | 38 | * Platform-specific interrupt support for the MIPS Malta. |
39 | */ | | 39 | */ |
40 | | | 40 | |
41 | #include "opt_multiprocessor.h" | | 41 | #include "opt_multiprocessor.h" |
42 | | | 42 | |
43 | #include "cpunode.h" | | 43 | #include "cpunode.h" |
44 | #define __INTR_PRIVATE | | 44 | #define __INTR_PRIVATE |
45 | | | 45 | |
46 | #include <sys/cdefs.h> | | 46 | #include <sys/cdefs.h> |
47 | __KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.16 2020/07/17 17:57:16 jmcneill Exp $"); | | 47 | __KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.17 2020/07/17 19:40:47 jmcneill Exp $"); |
48 | | | 48 | |
49 | #include <sys/param.h> | | 49 | #include <sys/param.h> |
50 | #include <sys/cpu.h> | | 50 | #include <sys/cpu.h> |
51 | #include <sys/systm.h> | | 51 | #include <sys/systm.h> |
52 | #include <sys/device.h> | | 52 | #include <sys/device.h> |
53 | #include <sys/intr.h> | | 53 | #include <sys/intr.h> |
54 | #include <sys/kernel.h> | | 54 | #include <sys/kernel.h> |
55 | #include <sys/kmem.h> | | 55 | #include <sys/kmem.h> |
56 | #include <sys/atomic.h> | | 56 | #include <sys/atomic.h> |
57 | | | 57 | |
58 | #include <lib/libkern/libkern.h> | | 58 | #include <lib/libkern/libkern.h> |
59 | | | 59 | |
60 | #include <mips/locore.h> | | 60 | #include <mips/locore.h> |
61 | | | 61 | |
62 | #include <mips/cavium/dev/octeon_ciureg.h> | | 62 | #include <mips/cavium/dev/octeon_ciureg.h> |
63 | #include <mips/cavium/octeonvar.h> | | 63 | #include <mips/cavium/octeonvar.h> |
64 | | | 64 | |
65 | /* | | 65 | /* |
66 | * This is a mask of bits to clear in the SR when we go to a | | 66 | * This is a mask of bits to clear in the SR when we go to a |
67 | * given hardware interrupt priority level. | | 67 | * given hardware interrupt priority level. |
68 | */ | | 68 | */ |
69 | static const struct ipl_sr_map octeon_ipl_sr_map = { | | 69 | static const struct ipl_sr_map octeon_ipl_sr_map = { |
70 | .sr_bits = { | | 70 | .sr_bits = { |
71 | [IPL_NONE] = 0, | | 71 | [IPL_NONE] = 0, |
72 | [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, | | 72 | [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, |
73 | [IPL_SOFTNET] = MIPS_SOFT_INT_MASK, | | 73 | [IPL_SOFTNET] = MIPS_SOFT_INT_MASK, |
74 | [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0, | | 74 | [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0, |
75 | [IPL_SCHED] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0 | | 75 | [IPL_SCHED] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0 |
76 | | MIPS_INT_MASK_1 | MIPS_INT_MASK_5, | | 76 | | MIPS_INT_MASK_1 | MIPS_INT_MASK_5, |
77 | [IPL_DDB] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0 | | 77 | [IPL_DDB] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0 |
78 | | MIPS_INT_MASK_1 | MIPS_INT_MASK_5, | | 78 | | MIPS_INT_MASK_1 | MIPS_INT_MASK_5, |
79 | [IPL_HIGH] = MIPS_INT_MASK, | | 79 | [IPL_HIGH] = MIPS_INT_MASK, |
80 | }, | | 80 | }, |
81 | }; | | 81 | }; |
82 | | | 82 | |
83 | const char * octeon_intrnames[NIRQS] = { | | 83 | const char * octeon_intrnames[NIRQS] = { |
84 | "workq 0", | | 84 | "workq 0", |
85 | "workq 1", | | 85 | "workq 1", |
86 | "workq 2", | | 86 | "workq 2", |
87 | "workq 3", | | 87 | "workq 3", |
88 | "workq 4", | | 88 | "workq 4", |
89 | "workq 5", | | 89 | "workq 5", |
90 | "workq 6", | | 90 | "workq 6", |
91 | "workq 7", | | 91 | "workq 7", |
92 | "workq 8", | | 92 | "workq 8", |
93 | "workq 9", | | 93 | "workq 9", |
94 | "workq 10", | | 94 | "workq 10", |
95 | "workq 11", | | 95 | "workq 11", |
96 | "workq 12", | | 96 | "workq 12", |
97 | "workq 13", | | 97 | "workq 13", |
98 | "workq 14", | | 98 | "workq 14", |
99 | "workq 15", | | 99 | "workq 15", |
100 | "gpio 0", | | 100 | "gpio 0", |
101 | "gpio 1", | | 101 | "gpio 1", |
102 | "gpio 2", | | 102 | "gpio 2", |
103 | "gpio 3", | | 103 | "gpio 3", |
104 | "gpio 4", | | 104 | "gpio 4", |
105 | "gpio 5", | | 105 | "gpio 5", |
106 | "gpio 6", | | 106 | "gpio 6", |
107 | "gpio 7", | | 107 | "gpio 7", |
108 | "gpio 8", | | 108 | "gpio 8", |
109 | "gpio 9", | | 109 | "gpio 9", |
110 | "gpio 10", | | 110 | "gpio 10", |
111 | "gpio 11", | | 111 | "gpio 11", |
112 | "gpio 12", | | 112 | "gpio 12", |
113 | "gpio 13", | | 113 | "gpio 13", |
114 | "gpio 14", | | 114 | "gpio 14", |
115 | "gpio 15", | | 115 | "gpio 15", |
116 | "mbox 0-15", | | 116 | "mbox 0-15", |
117 | "mbox 16-31", | | 117 | "mbox 16-31", |
118 | "uart 0", | | 118 | "uart 0", |
119 | "uart 1", | | 119 | "uart 1", |
120 | "pci inta", | | 120 | "pci inta", |
121 | "pci intb", | | 121 | "pci intb", |
122 | "pci intc", | | 122 | "pci intc", |
123 | "pci intd", | | 123 | "pci intd", |
124 | "pci msi 0-15", | | 124 | "pci msi 0-15", |
125 | "pci msi 16-31", | | 125 | "pci msi 16-31", |
126 | "pci msi 32-47", | | 126 | "pci msi 32-47", |
127 | "pci msi 48-63", | | 127 | "pci msi 48-63", |
128 | "wdog summary", | | 128 | "wdog summary", |
129 | "twsi", | | 129 | "twsi", |
130 | "rml", | | 130 | "rml", |
131 | "trace", | | 131 | "trace", |
132 | "gmx drop", | | 132 | "gmx drop", |
133 | "reserved", | | 133 | "reserved", |
134 | "ipd drop", | | 134 | "ipd drop", |
135 | "reserved", | | 135 | "reserved", |
136 | "timer 0", | | 136 | "timer 0", |
137 | "timer 1", | | 137 | "timer 1", |
138 | "timer 2", | | 138 | "timer 2", |
139 | "timer 3", | | 139 | "timer 3", |
140 | "usb", | | 140 | "usb", |
141 | "pcm/tdm", | | 141 | "pcm/tdm", |
142 | "mpi/spi", | | 142 | "mpi/spi", |
143 | "reserved", | | 143 | "reserved", |
144 | "reserved", | | 144 | "reserved", |
145 | "reserved", | | 145 | "reserved", |
146 | "reserved", | | 146 | "reserved", |
147 | "reserved", | | 147 | "reserved", |
148 | }; | | 148 | }; |
149 | | | 149 | |
150 | struct octeon_intrhand { | | 150 | struct octeon_intrhand { |
151 | int (*ih_func)(void *); | | 151 | int (*ih_func)(void *); |
152 | void *ih_arg; | | 152 | void *ih_arg; |
153 | int ih_irq; | | 153 | int ih_irq; |
154 | int ih_ipl; | | 154 | int ih_ipl; |
155 | }; | | 155 | }; |
156 | | | 156 | |
157 | #ifdef MULTIPROCESSOR | | 157 | #ifdef MULTIPROCESSOR |
158 | static int octeon_send_ipi(struct cpu_info *, int); | | 158 | static int octeon_send_ipi(struct cpu_info *, int); |
159 | static int octeon_ipi_intr(void *); | | 159 | static int octeon_ipi_intr(void *); |
160 | | | 160 | |
161 | struct octeon_intrhand ipi_intrhands[2] = { | | 161 | struct octeon_intrhand ipi_intrhands[2] = { |
162 | [0] = { | | 162 | [0] = { |
163 | .ih_func = octeon_ipi_intr, | | 163 | .ih_func = octeon_ipi_intr, |
164 | .ih_arg = (void *)(uintptr_t)__BITS(15,0), | | 164 | .ih_arg = (void *)(uintptr_t)__BITS(15,0), |
165 | .ih_irq = CIU_INT_MBOX_15_0, | | 165 | .ih_irq = CIU_INT_MBOX_15_0, |
166 | .ih_ipl = IPL_SCHED, | | 166 | .ih_ipl = IPL_SCHED, |
167 | }, | | 167 | }, |
168 | [1] = { | | 168 | [1] = { |
169 | .ih_func = octeon_ipi_intr, | | 169 | .ih_func = octeon_ipi_intr, |
170 | .ih_arg = (void *)(uintptr_t)__BITS(31,16), | | 170 | .ih_arg = (void *)(uintptr_t)__BITS(31,16), |
171 | .ih_irq = CIU_INT_MBOX_31_16, | | 171 | .ih_irq = CIU_INT_MBOX_31_16, |
172 | .ih_ipl = IPL_HIGH, | | 172 | .ih_ipl = IPL_HIGH, |
173 | }, | | 173 | }, |
174 | }; | | 174 | }; |
| | | 175 | |
| | | 176 | #define OCTEON_IPI_SCHED(n) __BIT((n) + 0) |
| | | 177 | #define OCTEON_IPI_HIGH(n) __BIT((n) + 16) |
| | | 178 | |
| | | 179 | static uint64_t octeon_ipi_mask[NIPIS] = { |
| | | 180 | [IPI_NOP] = OCTEON_IPI_SCHED(IPI_NOP), |
| | | 181 | [IPI_AST] = OCTEON_IPI_SCHED(IPI_AST), |
| | | 182 | [IPI_SHOOTDOWN] = OCTEON_IPI_SCHED(IPI_SHOOTDOWN), |
| | | 183 | [IPI_SYNCICACHE] = OCTEON_IPI_SCHED(IPI_SYNCICACHE), |
| | | 184 | [IPI_KPREEMPT] = OCTEON_IPI_SCHED(IPI_KPREEMPT), |
| | | 185 | [IPI_SUSPEND] = OCTEON_IPI_HIGH(IPI_SUSPEND), |
| | | 186 | [IPI_HALT] = OCTEON_IPI_HIGH(IPI_HALT), |
| | | 187 | [IPI_XCALL] = OCTEON_IPI_HIGH(IPI_XCALL), |
| | | 188 | [IPI_GENERIC] = OCTEON_IPI_HIGH(IPI_GENERIC), |
| | | 189 | [IPI_WDOG] = OCTEON_IPI_HIGH(IPI_WDOG), |
| | | 190 | }; |
175 | #endif | | 191 | #endif |
176 | | | 192 | |
177 | struct octeon_intrhand *octciu_intrs[NIRQS] = { | | 193 | struct octeon_intrhand *octciu_intrs[NIRQS] = { |
178 | #ifdef MULTIPROCESSOR | | 194 | #ifdef MULTIPROCESSOR |
179 | [CIU_INT_MBOX_15_0] = &ipi_intrhands[0], | | 195 | [CIU_INT_MBOX_15_0] = &ipi_intrhands[0], |
180 | [CIU_INT_MBOX_31_16] = &ipi_intrhands[1], | | 196 | [CIU_INT_MBOX_31_16] = &ipi_intrhands[1], |
181 | #endif | | 197 | #endif |
182 | }; | | 198 | }; |
183 | | | 199 | |
184 | kmutex_t octeon_intr_lock; | | 200 | kmutex_t octeon_intr_lock; |
185 | | | 201 | |
186 | #define X(a) MIPS_PHYS_TO_XKPHYS(OCTEON_CCA_NONE, (a)) | | 202 | #define X(a) MIPS_PHYS_TO_XKPHYS(OCTEON_CCA_NONE, (a)) |
187 | | | 203 | |
188 | struct cpu_softc octeon_cpu0_softc = { | | 204 | struct cpu_softc octeon_cpu0_softc = { |
189 | .cpu_ci = &cpu_info_store, | | 205 | .cpu_ci = &cpu_info_store, |
190 | .cpu_int0_sum0 = X(CIU_INT0_SUM0), | | 206 | .cpu_int0_sum0 = X(CIU_INT0_SUM0), |
191 | .cpu_int1_sum0 = X(CIU_INT1_SUM0), | | 207 | .cpu_int1_sum0 = X(CIU_INT1_SUM0), |
192 | .cpu_int2_sum0 = X(CIU_INT4_SUM0), | | 208 | .cpu_int2_sum0 = X(CIU_INT4_SUM0), |
193 | | | 209 | |
194 | .cpu_int_sum1 = X(CIU_INT_SUM1), | | 210 | .cpu_int_sum1 = X(CIU_INT_SUM1), |
195 | | | 211 | |
196 | .cpu_int0_en[0] = X(CIU_INT0_EN0), | | 212 | .cpu_int0_en[0] = X(CIU_INT0_EN0), |
197 | .cpu_int1_en[0] = X(CIU_INT1_EN0), | | 213 | .cpu_int1_en[0] = X(CIU_INT1_EN0), |
198 | .cpu_int2_en[0] = X(CIU_INT4_EN00), | | 214 | .cpu_int2_en[0] = X(CIU_INT4_EN00), |
199 | | | 215 | |
200 | .cpu_int0_en[1] = X(CIU_INT0_EN1), | | 216 | .cpu_int0_en[1] = X(CIU_INT0_EN1), |
201 | .cpu_int1_en[1] = X(CIU_INT1_EN1), | | 217 | .cpu_int1_en[1] = X(CIU_INT1_EN1), |
202 | .cpu_int2_en[1] = X(CIU_INT4_EN01), | | 218 | .cpu_int2_en[1] = X(CIU_INT4_EN01), |
203 | | | 219 | |
204 | .cpu_int32_en = X(CIU_INT32_EN0), | | 220 | .cpu_int32_en = X(CIU_INT32_EN0), |
205 | | | 221 | |
206 | .cpu_wdog = X(CIU_WDOG0), | | 222 | .cpu_wdog = X(CIU_WDOG0), |
207 | .cpu_pp_poke = X(CIU_PP_POKE0), | | 223 | .cpu_pp_poke = X(CIU_PP_POKE0), |
208 | | | 224 | |
209 | #ifdef MULTIPROCESSOR | | 225 | #ifdef MULTIPROCESSOR |
210 | .cpu_mbox_set = X(CIU_MBOX_SET0), | | 226 | .cpu_mbox_set = X(CIU_MBOX_SET0), |
211 | .cpu_mbox_clr = X(CIU_MBOX_CLR0), | | 227 | .cpu_mbox_clr = X(CIU_MBOX_CLR0), |
212 | #endif | | 228 | #endif |
213 | }; | | 229 | }; |
214 | | | 230 | |
215 | #ifdef MULTIPROCESSOR | | 231 | #ifdef MULTIPROCESSOR |
216 | /* XXX limit of two CPUs ... */ | | 232 | /* XXX limit of two CPUs ... */ |
217 | struct cpu_softc octeon_cpu1_softc = { | | 233 | struct cpu_softc octeon_cpu1_softc = { |
218 | .cpu_int0_sum0 = X(CIU_INT2_SUM0), | | 234 | .cpu_int0_sum0 = X(CIU_INT2_SUM0), |
219 | .cpu_int1_sum0 = X(CIU_INT3_SUM0), | | 235 | .cpu_int1_sum0 = X(CIU_INT3_SUM0), |
220 | .cpu_int2_sum0 = X(CIU_INT4_SUM1), | | 236 | .cpu_int2_sum0 = X(CIU_INT4_SUM1), |
221 | | | 237 | |
222 | .cpu_int_sum1 = X(CIU_INT_SUM1), | | 238 | .cpu_int_sum1 = X(CIU_INT_SUM1), |
223 | | | 239 | |
224 | .cpu_int0_en[0] = X(CIU_INT2_EN0), | | 240 | .cpu_int0_en[0] = X(CIU_INT2_EN0), |
225 | .cpu_int1_en[0] = X(CIU_INT3_EN0), | | 241 | .cpu_int1_en[0] = X(CIU_INT3_EN0), |
226 | .cpu_int2_en[0] = X(CIU_INT4_EN10), | | 242 | .cpu_int2_en[0] = X(CIU_INT4_EN10), |
227 | | | 243 | |
228 | .cpu_int0_en[1] = X(CIU_INT2_EN1), | | 244 | .cpu_int0_en[1] = X(CIU_INT2_EN1), |
229 | .cpu_int1_en[1] = X(CIU_INT3_EN1), | | 245 | .cpu_int1_en[1] = X(CIU_INT3_EN1), |
230 | .cpu_int2_en[1] = X(CIU_INT4_EN11), | | 246 | .cpu_int2_en[1] = X(CIU_INT4_EN11), |
231 | | | 247 | |
232 | .cpu_int32_en = X(CIU_INT32_EN1), | | 248 | .cpu_int32_en = X(CIU_INT32_EN1), |
233 | | | 249 | |
234 | .cpu_wdog = X(CIU_WDOG(1)), | | 250 | .cpu_wdog = X(CIU_WDOG(1)), |
235 | .cpu_pp_poke = X(CIU_PP_POKE1), | | 251 | .cpu_pp_poke = X(CIU_PP_POKE1), |
236 | | | 252 | |
237 | .cpu_mbox_set = X(CIU_MBOX_SET1), | | 253 | .cpu_mbox_set = X(CIU_MBOX_SET1), |
238 | .cpu_mbox_clr = X(CIU_MBOX_CLR1), | | 254 | .cpu_mbox_clr = X(CIU_MBOX_CLR1), |
239 | }; | | 255 | }; |
240 | #endif | | 256 | #endif |
241 | | | 257 | |
242 | #ifdef DEBUG | | 258 | #ifdef DEBUG |
243 | static void | | 259 | static void |
244 | octeon_mbox_test(void) | | 260 | octeon_mbox_test(void) |
245 | { | | 261 | { |
246 | const uint64_t mbox_clr0 = X(CIU_MBOX_CLR0); | | 262 | const uint64_t mbox_clr0 = X(CIU_MBOX_CLR0); |
247 | const uint64_t mbox_clr1 = X(CIU_MBOX_CLR1); | | 263 | const uint64_t mbox_clr1 = X(CIU_MBOX_CLR1); |
248 | const uint64_t mbox_set0 = X(CIU_MBOX_SET0); | | 264 | const uint64_t mbox_set0 = X(CIU_MBOX_SET0); |
249 | const uint64_t mbox_set1 = X(CIU_MBOX_SET1); | | 265 | const uint64_t mbox_set1 = X(CIU_MBOX_SET1); |
250 | const uint64_t int_sum0 = X(CIU_INT0_SUM0); | | 266 | const uint64_t int_sum0 = X(CIU_INT0_SUM0); |
251 | const uint64_t int_sum1 = X(CIU_INT2_SUM0); | | 267 | const uint64_t int_sum1 = X(CIU_INT2_SUM0); |
252 | const uint64_t sum_mbox_lo = __BIT(CIU_INT_MBOX_15_0); | | 268 | const uint64_t sum_mbox_lo = __BIT(CIU_INT_MBOX_15_0); |
253 | const uint64_t sum_mbox_hi = __BIT(CIU_INT_MBOX_31_16); | | 269 | const uint64_t sum_mbox_hi = __BIT(CIU_INT_MBOX_31_16); |
254 | | | 270 | |
255 | mips3_sd(mbox_clr0, ~0ULL); | | 271 | mips3_sd(mbox_clr0, ~0ULL); |
256 | mips3_sd(mbox_clr1, ~0ULL); | | 272 | mips3_sd(mbox_clr1, ~0ULL); |
257 | | | 273 | |
258 | uint32_t mbox0 = mips3_ld(mbox_set0); | | 274 | uint32_t mbox0 = mips3_ld(mbox_set0); |
259 | uint32_t mbox1 = mips3_ld(mbox_set1); | | 275 | uint32_t mbox1 = mips3_ld(mbox_set1); |
260 | | | 276 | |
261 | KDASSERTMSG(mbox0 == 0, "mbox0 %#x mbox1 %#x", mbox0, mbox1); | | 277 | KDASSERTMSG(mbox0 == 0, "mbox0 %#x mbox1 %#x", mbox0, mbox1); |
262 | KDASSERTMSG(mbox1 == 0, "mbox0 %#x mbox1 %#x", mbox0, mbox1); | | 278 | KDASSERTMSG(mbox1 == 0, "mbox0 %#x mbox1 %#x", mbox0, mbox1); |
263 | | | 279 | |
264 | mips3_sd(mbox_set0, __BIT(0)); | | 280 | mips3_sd(mbox_set0, __BIT(0)); |
265 | | | 281 | |
266 | mbox0 = mips3_ld(mbox_set0); | | 282 | mbox0 = mips3_ld(mbox_set0); |
267 | mbox1 = mips3_ld(mbox_set1); | | 283 | mbox1 = mips3_ld(mbox_set1); |
268 | | | 284 | |
269 | KDASSERTMSG(mbox0 == 1, "mbox0 %#x mbox1 %#x", mbox0, mbox1); | | 285 | KDASSERTMSG(mbox0 == 1, "mbox0 %#x mbox1 %#x", mbox0, mbox1); |
270 | KDASSERTMSG(mbox1 == 0, "mbox0 %#x mbox1 %#x", mbox0, mbox1); | | 286 | KDASSERTMSG(mbox1 == 0, "mbox0 %#x mbox1 %#x", mbox0, mbox1); |
271 | | | 287 | |
272 | uint64_t sum0 = mips3_ld(int_sum0); | | 288 | uint64_t sum0 = mips3_ld(int_sum0); |
273 | uint64_t sum1 = mips3_ld(int_sum1); | | 289 | uint64_t sum1 = mips3_ld(int_sum1); |
274 | | | 290 | |
275 | KDASSERTMSG((sum0 & sum_mbox_lo) != 0, "sum0 %#"PRIx64, sum0); | | 291 | KDASSERTMSG((sum0 & sum_mbox_lo) != 0, "sum0 %#"PRIx64, sum0); |
276 | KDASSERTMSG((sum0 & sum_mbox_hi) == 0, "sum0 %#"PRIx64, sum0); | | 292 | KDASSERTMSG((sum0 & sum_mbox_hi) == 0, "sum0 %#"PRIx64, sum0); |
277 | | | 293 | |
278 | KDASSERTMSG((sum1 & sum_mbox_lo) == 0, "sum1 %#"PRIx64, sum1); | | 294 | KDASSERTMSG((sum1 & sum_mbox_lo) == 0, "sum1 %#"PRIx64, sum1); |
279 | KDASSERTMSG((sum1 & sum_mbox_hi) == 0, "sum1 %#"PRIx64, sum1); | | 295 | KDASSERTMSG((sum1 & sum_mbox_hi) == 0, "sum1 %#"PRIx64, sum1); |
280 | | | 296 | |
281 | mips3_sd(mbox_clr0, mbox0); | | 297 | mips3_sd(mbox_clr0, mbox0); |
282 | mbox0 = mips3_ld(mbox_set0); | | 298 | mbox0 = mips3_ld(mbox_set0); |
283 | KDASSERTMSG(mbox0 == 0, "mbox0 %#x", mbox0); | | 299 | KDASSERTMSG(mbox0 == 0, "mbox0 %#x", mbox0); |
284 | | | 300 | |
285 | mips3_sd(mbox_set0, __BIT(16)); | | 301 | mips3_sd(mbox_set0, __BIT(16)); |
286 | | | 302 | |
287 | mbox0 = mips3_ld(mbox_set0); | | 303 | mbox0 = mips3_ld(mbox_set0); |
288 | mbox1 = mips3_ld(mbox_set1); | | 304 | mbox1 = mips3_ld(mbox_set1); |
289 | | | 305 | |
290 | KDASSERTMSG(mbox0 == __BIT(16), "mbox0 %#x", mbox0); | | 306 | KDASSERTMSG(mbox0 == __BIT(16), "mbox0 %#x", mbox0); |
291 | KDASSERTMSG(mbox1 == 0, "mbox1 %#x", mbox1); | | 307 | KDASSERTMSG(mbox1 == 0, "mbox1 %#x", mbox1); |
292 | | | 308 | |
293 | sum0 = mips3_ld(int_sum0); | | 309 | sum0 = mips3_ld(int_sum0); |
294 | sum1 = mips3_ld(int_sum1); | | 310 | sum1 = mips3_ld(int_sum1); |
295 | | | 311 | |
296 | KDASSERTMSG((sum0 & sum_mbox_lo) == 0, "sum0 %#"PRIx64, sum0); | | 312 | KDASSERTMSG((sum0 & sum_mbox_lo) == 0, "sum0 %#"PRIx64, sum0); |
297 | KDASSERTMSG((sum0 & sum_mbox_hi) != 0, "sum0 %#"PRIx64, sum0); | | 313 | KDASSERTMSG((sum0 & sum_mbox_hi) != 0, "sum0 %#"PRIx64, sum0); |
298 | | | 314 | |
299 | KDASSERTMSG((sum1 & sum_mbox_lo) == 0, "sum1 %#"PRIx64, sum1); | | 315 | KDASSERTMSG((sum1 & sum_mbox_lo) == 0, "sum1 %#"PRIx64, sum1); |
300 | KDASSERTMSG((sum1 & sum_mbox_hi) == 0, "sum1 %#"PRIx64, sum1); | | 316 | KDASSERTMSG((sum1 & sum_mbox_hi) == 0, "sum1 %#"PRIx64, sum1); |
301 | } | | 317 | } |
302 | #endif | | 318 | #endif |
303 | | | 319 | |
304 | #undef X | | 320 | #undef X |
305 | | | 321 | |
306 | void | | 322 | void |
307 | octeon_intr_init(struct cpu_info *ci) | | 323 | octeon_intr_init(struct cpu_info *ci) |
308 | { | | 324 | { |
309 | #ifdef DIAGNOSTIC | | 325 | #ifdef DIAGNOSTIC |
310 | const int cpunum = cpu_index(ci); | | 326 | const int cpunum = cpu_index(ci); |
311 | #endif | | 327 | #endif |
312 | const char * const xname = cpu_name(ci); | | 328 | const char * const xname = cpu_name(ci); |
313 | struct cpu_softc *cpu = ci->ci_softc; | | 329 | struct cpu_softc *cpu = ci->ci_softc; |
314 | int bank; | | 330 | int bank; |
315 | | | 331 | |
316 | | | 332 | |
317 | if (ci->ci_cpuid == 0) { | | 333 | if (ci->ci_cpuid == 0) { |
318 | KASSERT(ci->ci_softc == &octeon_cpu0_softc); | | 334 | KASSERT(ci->ci_softc == &octeon_cpu0_softc); |
319 | ipl_sr_map = octeon_ipl_sr_map; | | 335 | ipl_sr_map = octeon_ipl_sr_map; |
320 | mutex_init(&octeon_intr_lock, MUTEX_DEFAULT, IPL_HIGH); | | 336 | mutex_init(&octeon_intr_lock, MUTEX_DEFAULT, IPL_HIGH); |
321 | #ifdef MULTIPROCESSOR | | 337 | #ifdef MULTIPROCESSOR |
322 | mips_locoresw.lsw_send_ipi = octeon_send_ipi; | | 338 | mips_locoresw.lsw_send_ipi = octeon_send_ipi; |
323 | #endif | | 339 | #endif |
324 | #ifdef DEBUG | | 340 | #ifdef DEBUG |
325 | octeon_mbox_test(); | | 341 | octeon_mbox_test(); |
326 | #endif | | 342 | #endif |
327 | } else { | | 343 | } else { |
328 | KASSERT(cpunum == 1); | | 344 | KASSERT(cpunum == 1); |
329 | #ifdef MULTIPROCESSOR | | 345 | #ifdef MULTIPROCESSOR |
330 | KASSERT(ci->ci_softc == &octeon_cpu1_softc); | | 346 | KASSERT(ci->ci_softc == &octeon_cpu1_softc); |
331 | #endif | | 347 | #endif |
332 | } | | 348 | } |
333 | | | 349 | |
334 | #ifdef MULTIPROCESSOR | | 350 | #ifdef MULTIPROCESSOR |
335 | // Enable the IPIs | | 351 | // Enable the IPIs |
336 | cpu->cpu_int1_enable[0] |= __BIT(CIU_INT_MBOX_15_0); | | 352 | cpu->cpu_int1_enable[0] |= __BIT(CIU_INT_MBOX_15_0); |
337 | cpu->cpu_int2_enable[0] |= __BIT(CIU_INT_MBOX_31_16); | | 353 | cpu->cpu_int2_enable[0] |= __BIT(CIU_INT_MBOX_31_16); |
338 | #endif | | 354 | #endif |
339 | | | 355 | |
340 | if (ci->ci_dev) { | | 356 | if (ci->ci_dev) { |
341 | for (bank = 0; bank < NBANKS; bank++) { | | 357 | for (bank = 0; bank < NBANKS; bank++) { |
342 | aprint_verbose_dev(ci->ci_dev, | | 358 | aprint_verbose_dev(ci->ci_dev, |
343 | "enabling intr masks %u " | | 359 | "enabling intr masks %u " |
344 | " %#"PRIx64"/%#"PRIx64"/%#"PRIx64"\n", | | 360 | " %#"PRIx64"/%#"PRIx64"/%#"PRIx64"\n", |
345 | bank, | | 361 | bank, |
346 | cpu->cpu_int0_enable[0], | | 362 | cpu->cpu_int0_enable[0], |
347 | cpu->cpu_int1_enable[0], | | 363 | cpu->cpu_int1_enable[0], |
348 | cpu->cpu_int2_enable[0]); | | 364 | cpu->cpu_int2_enable[0]); |
349 | } | | 365 | } |
350 | } | | 366 | } |
351 | | | 367 | |
352 | for (bank = 0; bank < NBANKS; bank++) { | | 368 | for (bank = 0; bank < NBANKS; bank++) { |
353 | mips3_sd(cpu->cpu_int0_en[bank], cpu->cpu_int0_enable[bank]); | | 369 | mips3_sd(cpu->cpu_int0_en[bank], cpu->cpu_int0_enable[bank]); |
354 | mips3_sd(cpu->cpu_int1_en[bank], cpu->cpu_int1_enable[bank]); | | 370 | mips3_sd(cpu->cpu_int1_en[bank], cpu->cpu_int1_enable[bank]); |
355 | mips3_sd(cpu->cpu_int2_en[bank], cpu->cpu_int2_enable[bank]); | | 371 | mips3_sd(cpu->cpu_int2_en[bank], cpu->cpu_int2_enable[bank]); |
356 | } | | 372 | } |
357 | | | 373 | |
358 | mips3_sd(cpu->cpu_int32_en, 0); | | 374 | mips3_sd(cpu->cpu_int32_en, 0); |
359 | | | 375 | |
360 | #ifdef MULTIPROCESSOR | | 376 | #ifdef MULTIPROCESSOR |
361 | mips3_sd(cpu->cpu_mbox_clr, __BITS(31,0)); | | 377 | mips3_sd(cpu->cpu_mbox_clr, __BITS(31,0)); |
362 | #endif | | 378 | #endif |
363 | | | 379 | |
364 | for (int i = 0; i < NIRQS; i++) { | | 380 | for (int i = 0; i < NIRQS; i++) { |
365 | if (octeon_intrnames[i] == NULL) | | 381 | if (octeon_intrnames[i] == NULL) |
366 | octeon_intrnames[i] = kmem_asprintf("irq %d", i); | | 382 | octeon_intrnames[i] = kmem_asprintf("irq %d", i); |
367 | evcnt_attach_dynamic(&cpu->cpu_intr_evs[i], | | 383 | evcnt_attach_dynamic(&cpu->cpu_intr_evs[i], |
368 | EVCNT_TYPE_INTR, NULL, xname, octeon_intrnames[i]); | | 384 | EVCNT_TYPE_INTR, NULL, xname, octeon_intrnames[i]); |
369 | } | | 385 | } |
370 | } | | 386 | } |
371 | | | 387 | |
372 | void | | 388 | void |
373 | octeon_cal_timer(int corefreq) | | 389 | octeon_cal_timer(int corefreq) |
374 | { | | 390 | { |
375 | /* Compute the number of cycles per second. */ | | 391 | /* Compute the number of cycles per second. */ |
376 | curcpu()->ci_cpu_freq = corefreq; | | 392 | curcpu()->ci_cpu_freq = corefreq; |
377 | | | 393 | |
378 | /* Compute the number of ticks for hz. */ | | 394 | /* Compute the number of ticks for hz. */ |
379 | curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz; | | 395 | curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz; |
380 | | | 396 | |
381 | /* Compute the delay divisor and reciprical. */ | | 397 | /* Compute the delay divisor and reciprical. */ |
382 | curcpu()->ci_divisor_delay = | | 398 | curcpu()->ci_divisor_delay = |
383 | ((curcpu()->ci_cpu_freq + 500000) / 1000000); | | 399 | ((curcpu()->ci_cpu_freq + 500000) / 1000000); |
384 | #if 0 | | 400 | #if 0 |
385 | MIPS_SET_CI_RECIPRICAL(curcpu()); | | 401 | MIPS_SET_CI_RECIPRICAL(curcpu()); |
386 | #endif | | 402 | #endif |
387 | | | 403 | |
388 | mips3_cp0_count_write(0); | | 404 | mips3_cp0_count_write(0); |
389 | mips3_cp0_compare_write(0); | | 405 | mips3_cp0_compare_write(0); |
390 | } | | 406 | } |
391 | | | 407 | |
392 | void * | | 408 | void * |
393 | octeon_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) | | 409 | octeon_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) |
394 | { | | 410 | { |
395 | struct octeon_intrhand *ih; | | 411 | struct octeon_intrhand *ih; |
396 | | | 412 | |
397 | if (irq >= NIRQS) | | 413 | if (irq >= NIRQS) |
398 | panic("octeon_intr_establish: bogus IRQ %d", irq); | | 414 | panic("octeon_intr_establish: bogus IRQ %d", irq); |
399 | if (ipl < IPL_VM) | | 415 | if (ipl < IPL_VM) |
400 | panic("octeon_intr_establish: bogus IPL %d", ipl); | | 416 | panic("octeon_intr_establish: bogus IPL %d", ipl); |
401 | | | 417 | |
402 | ih = kmem_zalloc(sizeof(*ih), KM_NOSLEEP); | | 418 | ih = kmem_zalloc(sizeof(*ih), KM_NOSLEEP); |
403 | if (ih == NULL) | | 419 | if (ih == NULL) |
404 | return (NULL); | | 420 | return (NULL); |
405 | | | 421 | |
406 | ih->ih_func = func; | | 422 | ih->ih_func = func; |
407 | ih->ih_arg = arg; | | 423 | ih->ih_arg = arg; |
408 | ih->ih_irq = irq; | | 424 | ih->ih_irq = irq; |
409 | ih->ih_ipl = ipl; | | 425 | ih->ih_ipl = ipl; |
410 | | | 426 | |
411 | mutex_enter(&octeon_intr_lock); | | 427 | mutex_enter(&octeon_intr_lock); |
412 | | | 428 | |
413 | /* | | 429 | /* |
414 | * First, make it known. | | 430 | * First, make it known. |
415 | */ | | 431 | */ |
416 | KASSERTMSG(octciu_intrs[irq] == NULL, "irq %d in use! (%p)", | | 432 | KASSERTMSG(octciu_intrs[irq] == NULL, "irq %d in use! (%p)", |
417 | irq, octciu_intrs[irq]); | | 433 | irq, octciu_intrs[irq]); |
418 | | | 434 | |
419 | octciu_intrs[irq] = ih; | | 435 | octciu_intrs[irq] = ih; |
420 | membar_producer(); | | 436 | membar_producer(); |
421 | | | 437 | |
422 | /* | | 438 | /* |
423 | * Now enable it. | | 439 | * Now enable it. |
424 | */ | | 440 | */ |
425 | const int bank = irq / 64; | | 441 | const int bank = irq / 64; |
426 | const uint64_t irq_mask = __BIT(irq % 64); | | 442 | const uint64_t irq_mask = __BIT(irq % 64); |
427 | struct cpu_softc * const cpu0 = &octeon_cpu0_softc; | | 443 | struct cpu_softc * const cpu0 = &octeon_cpu0_softc; |
428 | #if MULTIPROCESSOR | | 444 | #if MULTIPROCESSOR |
429 | struct cpu_softc * const cpu1 = &octeon_cpu1_softc; | | 445 | struct cpu_softc * const cpu1 = &octeon_cpu1_softc; |
430 | #endif | | 446 | #endif |
431 | | | 447 | |
432 | switch (ipl) { | | 448 | switch (ipl) { |
433 | case IPL_VM: | | 449 | case IPL_VM: |
434 | cpu0->cpu_int0_enable[bank] |= irq_mask; | | 450 | cpu0->cpu_int0_enable[bank] |= irq_mask; |
435 | mips3_sd(cpu0->cpu_int0_en[bank], cpu0->cpu_int0_enable[bank]); | | 451 | mips3_sd(cpu0->cpu_int0_en[bank], cpu0->cpu_int0_enable[bank]); |
436 | break; | | 452 | break; |
437 | | | 453 | |
438 | case IPL_SCHED: | | 454 | case IPL_SCHED: |
439 | cpu0->cpu_int1_enable[bank] |= irq_mask; | | 455 | cpu0->cpu_int1_enable[bank] |= irq_mask; |
440 | mips3_sd(cpu0->cpu_int1_en[bank], cpu0->cpu_int1_enable[bank]); | | 456 | mips3_sd(cpu0->cpu_int1_en[bank], cpu0->cpu_int1_enable[bank]); |
441 | #ifdef MULTIPROCESSOR | | 457 | #ifdef MULTIPROCESSOR |
442 | cpu1->cpu_int1_enable[bank] = cpu0->cpu_int1_enable[bank]; | | 458 | cpu1->cpu_int1_enable[bank] = cpu0->cpu_int1_enable[bank]; |
443 | mips3_sd(cpu1->cpu_int1_en[bank], cpu1->cpu_int1_enable[bank]); | | 459 | mips3_sd(cpu1->cpu_int1_en[bank], cpu1->cpu_int1_enable[bank]); |
444 | #endif | | 460 | #endif |
445 | | | 461 | |
446 | break; | | 462 | break; |
447 | | | 463 | |
448 | case IPL_DDB: | | 464 | case IPL_DDB: |
449 | case IPL_HIGH: | | 465 | case IPL_HIGH: |
450 | cpu0->cpu_int2_enable[bank] |= irq_mask; | | 466 | cpu0->cpu_int2_enable[bank] |= irq_mask; |
451 | mips3_sd(cpu0->cpu_int2_en[bank], cpu0->cpu_int2_enable[bank]); | | 467 | mips3_sd(cpu0->cpu_int2_en[bank], cpu0->cpu_int2_enable[bank]); |
452 | #ifdef MULTIPROCESSOR | | 468 | #ifdef MULTIPROCESSOR |
453 | cpu1->cpu_int2_enable[bank] = cpu0->cpu_int2_enable[bank]; | | 469 | cpu1->cpu_int2_enable[bank] = cpu0->cpu_int2_enable[bank]; |
454 | mips3_sd(cpu1->cpu_int2_en[bank], cpu1->cpu_int2_enable[bank]); | | 470 | mips3_sd(cpu1->cpu_int2_en[bank], cpu1->cpu_int2_enable[bank]); |
455 | #endif | | 471 | #endif |
456 | | | 472 | |
457 | break; | | 473 | break; |
458 | } | | 474 | } |
459 | | | 475 | |
460 | mutex_exit(&octeon_intr_lock); | | 476 | mutex_exit(&octeon_intr_lock); |
461 | | | 477 | |
462 | return ih; | | 478 | return ih; |
463 | } | | 479 | } |
464 | | | 480 | |
465 | void | | 481 | void |
466 | octeon_intr_disestablish(void *cookie) | | 482 | octeon_intr_disestablish(void *cookie) |
467 | { | | 483 | { |
468 | struct octeon_intrhand * const ih = cookie; | | 484 | struct octeon_intrhand * const ih = cookie; |
469 | const int irq = ih->ih_irq & (NIRQS-1); | | 485 | const int irq = ih->ih_irq & (NIRQS-1); |
470 | const int ipl = ih->ih_ipl; | | 486 | const int ipl = ih->ih_ipl; |
471 | | | 487 | |
472 | mutex_enter(&octeon_intr_lock); | | 488 | mutex_enter(&octeon_intr_lock); |
473 | | | 489 | |
474 | /* | | 490 | /* |
475 | * First disable it. | | 491 | * First disable it. |
476 | */ | | 492 | */ |
477 | const int bank = irq / 64; | | 493 | const int bank = irq / 64; |
478 | const uint64_t irq_mask = ~__BIT(irq % 64); | | 494 | const uint64_t irq_mask = ~__BIT(irq % 64); |
479 | struct cpu_softc * const cpu0 = &octeon_cpu0_softc; | | 495 | struct cpu_softc * const cpu0 = &octeon_cpu0_softc; |
480 | #if MULTIPROCESSOR | | 496 | #if MULTIPROCESSOR |
481 | struct cpu_softc * const cpu1 = &octeon_cpu1_softc; | | 497 | struct cpu_softc * const cpu1 = &octeon_cpu1_softc; |
482 | #endif | | 498 | #endif |
483 | | | 499 | |
484 | switch (ipl) { | | 500 | switch (ipl) { |
485 | case IPL_VM: | | 501 | case IPL_VM: |
486 | cpu0->cpu_int0_enable[bank] &= ~irq_mask; | | 502 | cpu0->cpu_int0_enable[bank] &= ~irq_mask; |
487 | mips3_sd(cpu0->cpu_int0_en[bank], cpu0->cpu_int0_enable[bank]); | | 503 | mips3_sd(cpu0->cpu_int0_en[bank], cpu0->cpu_int0_enable[bank]); |
488 | break; | | 504 | break; |
489 | | | 505 | |
490 | case IPL_SCHED: | | 506 | case IPL_SCHED: |
491 | cpu0->cpu_int1_enable[bank] &= ~irq_mask; | | 507 | cpu0->cpu_int1_enable[bank] &= ~irq_mask; |
492 | mips3_sd(cpu0->cpu_int1_en[bank], cpu0->cpu_int1_enable[bank]); | | 508 | mips3_sd(cpu0->cpu_int1_en[bank], cpu0->cpu_int1_enable[bank]); |
493 | #ifdef MULTIPROCESSOR | | 509 | #ifdef MULTIPROCESSOR |
494 | cpu1->cpu_int1_enable[bank] = cpu0->cpu_int1_enable[bank]; | | 510 | cpu1->cpu_int1_enable[bank] = cpu0->cpu_int1_enable[bank]; |
495 | mips3_sd(cpu1->cpu_int1_en[bank], cpu1->cpu_int1_enable[bank]); | | 511 | mips3_sd(cpu1->cpu_int1_en[bank], cpu1->cpu_int1_enable[bank]); |
496 | #endif | | 512 | #endif |
497 | break; | | 513 | break; |
498 | | | 514 | |
499 | case IPL_DDB: | | 515 | case IPL_DDB: |
500 | case IPL_HIGH: | | 516 | case IPL_HIGH: |
501 | cpu0->cpu_int2_enable[bank] &= ~irq_mask; | | 517 | cpu0->cpu_int2_enable[bank] &= ~irq_mask; |
502 | mips3_sd(cpu0->cpu_int2_en[bank], cpu0->cpu_int2_enable[bank]); | | 518 | mips3_sd(cpu0->cpu_int2_en[bank], cpu0->cpu_int2_enable[bank]); |
503 | #ifdef MULTIPROCESSOR | | 519 | #ifdef MULTIPROCESSOR |
504 | cpu1->cpu_int2_enable[bank] = cpu0->cpu_int2_enable[bank]; | | 520 | cpu1->cpu_int2_enable[bank] = cpu0->cpu_int2_enable[bank]; |
505 | mips3_sd(cpu1->cpu_int2_en[bank], cpu1->cpu_int2_enable[bank]); | | 521 | mips3_sd(cpu1->cpu_int2_en[bank], cpu1->cpu_int2_enable[bank]); |
506 | #endif | | 522 | #endif |
507 | break; | | 523 | break; |
508 | } | | 524 | } |
509 | | | 525 | |
510 | /* | | 526 | /* |
511 | * Now remove it since we shouldn't get interrupts for it. | | 527 | * Now remove it since we shouldn't get interrupts for it. |
512 | */ | | 528 | */ |
513 | octciu_intrs[irq] = NULL; | | 529 | octciu_intrs[irq] = NULL; |
514 | | | 530 | |
515 | mutex_exit(&octeon_intr_lock); | | 531 | mutex_exit(&octeon_intr_lock); |
516 | | | 532 | |
517 | kmem_free(ih, sizeof(*ih)); | | 533 | kmem_free(ih, sizeof(*ih)); |
518 | } | | 534 | } |
519 | | | 535 | |
520 | void | | 536 | void |
521 | octeon_iointr(int ipl, vaddr_t pc, uint32_t ipending) | | 537 | octeon_iointr(int ipl, vaddr_t pc, uint32_t ipending) |
522 | { | | 538 | { |
523 | struct cpu_info * const ci = curcpu(); | | 539 | struct cpu_info * const ci = curcpu(); |
524 | struct cpu_softc * const cpu = ci->ci_softc; | | 540 | struct cpu_softc * const cpu = ci->ci_softc; |
525 | int bank; | | 541 | int bank; |
526 | | | 542 | |
527 | KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); | | 543 | KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); |
528 | KASSERT((ipending & ~MIPS_INT_MASK) == 0); | | 544 | KASSERT((ipending & ~MIPS_INT_MASK) == 0); |
529 | KASSERT(ipending & MIPS_HARD_INT_MASK); | | 545 | KASSERT(ipending & MIPS_HARD_INT_MASK); |
530 | uint64_t hwpend[2] = { 0, 0 }; | | 546 | uint64_t hwpend[2] = { 0, 0 }; |
531 | | | 547 | |
532 | const uint64_t sum1 = mips3_ld(cpu->cpu_int_sum1); | | 548 | const uint64_t sum1 = mips3_ld(cpu->cpu_int_sum1); |
533 | | | 549 | |
534 | if (ipending & MIPS_INT_MASK_2) { | | 550 | if (ipending & MIPS_INT_MASK_2) { |
535 | hwpend[0] = mips3_ld(cpu->cpu_int2_sum0) | | 551 | hwpend[0] = mips3_ld(cpu->cpu_int2_sum0) |
536 | & cpu->cpu_int2_enable[0]; | | 552 | & cpu->cpu_int2_enable[0]; |
537 | hwpend[1] = sum1 & cpu->cpu_int2_enable[1]; | | 553 | hwpend[1] = sum1 & cpu->cpu_int2_enable[1]; |
538 | } else if (ipending & MIPS_INT_MASK_1) { | | 554 | } else if (ipending & MIPS_INT_MASK_1) { |
539 | hwpend[0] = mips3_ld(cpu->cpu_int1_sum0) | | 555 | hwpend[0] = mips3_ld(cpu->cpu_int1_sum0) |
540 | & cpu->cpu_int1_enable[0]; | | 556 | & cpu->cpu_int1_enable[0]; |
541 | hwpend[1] = sum1 & cpu->cpu_int1_enable[1]; | | 557 | hwpend[1] = sum1 & cpu->cpu_int1_enable[1]; |
542 | } else if (ipending & MIPS_INT_MASK_0) { | | 558 | } else if (ipending & MIPS_INT_MASK_0) { |
543 | hwpend[0] = mips3_ld(cpu->cpu_int0_sum0) | | 559 | hwpend[0] = mips3_ld(cpu->cpu_int0_sum0) |
544 | & cpu->cpu_int0_enable[0]; | | 560 | & cpu->cpu_int0_enable[0]; |
545 | hwpend[1] = sum1 & cpu->cpu_int0_enable[1]; | | 561 | hwpend[1] = sum1 & cpu->cpu_int0_enable[1]; |
546 | } else { | | 562 | } else { |
547 | panic("octeon_iointr: unexpected ipending %#x", ipending); | | 563 | panic("octeon_iointr: unexpected ipending %#x", ipending); |
548 | } | | 564 | } |
549 | for (bank = 0; bank <= 1; bank++) { | | 565 | for (bank = 0; bank <= 1; bank++) { |
550 | while (hwpend[bank] != 0) { | | 566 | while (hwpend[bank] != 0) { |
551 | const int bit = ffs64(hwpend[bank]) - 1; | | 567 | const int bit = ffs64(hwpend[bank]) - 1; |
552 | const int irq = (bank * 64) + bit; | | 568 | const int irq = (bank * 64) + bit; |
553 | hwpend[bank] &= ~__BIT(bit); | | 569 | hwpend[bank] &= ~__BIT(bit); |
554 | | | 570 | |
555 | struct octeon_intrhand * const ih = octciu_intrs[irq]; | | 571 | struct octeon_intrhand * const ih = octciu_intrs[irq]; |
556 | cpu->cpu_intr_evs[irq].ev_count++; | | 572 | cpu->cpu_intr_evs[irq].ev_count++; |
557 | if (__predict_true(ih != NULL)) { | | 573 | if (__predict_true(ih != NULL)) { |
558 | #ifdef MULTIPROCESSOR | | 574 | #ifdef MULTIPROCESSOR |
559 | if (ipl == IPL_VM) { | | 575 | if (ipl == IPL_VM) { |
560 | KERNEL_LOCK(1, NULL); | | 576 | KERNEL_LOCK(1, NULL); |
561 | #endif | | 577 | #endif |
562 | (*ih->ih_func)(ih->ih_arg); | | 578 | (*ih->ih_func)(ih->ih_arg); |
563 | #ifdef MULTIPROCESSOR | | 579 | #ifdef MULTIPROCESSOR |
564 | KERNEL_UNLOCK_ONE(NULL); | | 580 | KERNEL_UNLOCK_ONE(NULL); |
565 | } else { | | 581 | } else { |
566 | (*ih->ih_func)(ih->ih_arg); | | 582 | (*ih->ih_func)(ih->ih_arg); |
567 | } | | 583 | } |
568 | #endif | | 584 | #endif |
569 | KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); | | 585 | KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); |
570 | } | | 586 | } |
571 | } | | 587 | } |
572 | } | | 588 | } |
573 | KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); | | 589 | KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); |
574 | } | | 590 | } |
575 | | | 591 | |
576 | #ifdef MULTIPROCESSOR | | 592 | #ifdef MULTIPROCESSOR |
577 | __CTASSERT(NIPIS < 16); | | 593 | __CTASSERT(NIPIS < 16); |
578 | | | 594 | |
579 | int | | 595 | int |
580 | octeon_ipi_intr(void *arg) | | 596 | octeon_ipi_intr(void *arg) |
581 | { | | 597 | { |
582 | struct cpu_info * const ci = curcpu(); | | 598 | struct cpu_info * const ci = curcpu(); |
583 | struct cpu_softc * const cpu = ci->ci_softc; | | 599 | struct cpu_softc * const cpu = ci->ci_softc; |
584 | uint32_t ipi_mask = (uintptr_t) arg; | | 600 | uint32_t ipi_mask = (uintptr_t) arg; |
585 | | | 601 | |
586 | KASSERTMSG((ipi_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED, | | 602 | KASSERTMSG((ipi_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED, |
587 | "ipi_mask %#"PRIx32" cpl %d", ipi_mask, ci->ci_cpl); | | 603 | "ipi_mask %#"PRIx32" cpl %d", ipi_mask, ci->ci_cpl); |
588 | | | 604 | |
589 | ipi_mask &= mips3_ld(cpu->cpu_mbox_set); | | 605 | ipi_mask &= mips3_ld(cpu->cpu_mbox_set); |
590 | if (ipi_mask == 0) | | 606 | if (ipi_mask == 0) |
591 | return 0; | | 607 | return 0; |
592 | | | 608 | |
593 | mips3_sd(cpu->cpu_mbox_clr, ipi_mask); | | 609 | mips3_sd(cpu->cpu_mbox_clr, ipi_mask); |
594 | | | 610 | |
595 | ipi_mask |= (ipi_mask >> 16); | | | |
596 | ipi_mask &= __BITS(15,0); | | | |
597 | | | | |
598 | KASSERT(ipi_mask < __BIT(NIPIS)); | | 611 | KASSERT(ipi_mask < __BIT(NIPIS)); |
599 | | | 612 | |
600 | #if NWDOG > 0 | | 613 | #if NWDOG > 0 |
601 | // Handle WDOG requests ourselves. | | 614 | // Handle WDOG requests ourselves. |
602 | if (ipi_mask & __BIT(IPI_WDOG)) { | | 615 | if (ipi_mask & __BIT(IPI_WDOG)) { |
603 | softint_schedule(cpu->cpu_wdog_sih); | | 616 | softint_schedule(cpu->cpu_wdog_sih); |
604 | atomic_and_64(&ci->ci_request_ipis, ~__BIT(IPI_WDOG)); | | 617 | atomic_and_64(&ci->ci_request_ipis, ~__BIT(IPI_WDOG)); |
605 | ipi_mask &= ~__BIT(IPI_WDOG); | | 618 | ipi_mask &= ~__BIT(IPI_WDOG); |
606 | ci->ci_evcnt_per_ipi[IPI_WDOG].ev_count++; | | 619 | ci->ci_evcnt_per_ipi[IPI_WDOG].ev_count++; |
607 | if (__predict_true(ipi_mask == 0)) | | 620 | if (__predict_true(ipi_mask == 0)) |
608 | return 1; | | 621 | return 1; |
609 | } | | 622 | } |
610 | #endif | | 623 | #endif |
611 | | | 624 | |
612 | /* if the request is clear, it was previously processed */ | | 625 | /* if the request is clear, it was previously processed */ |
613 | if ((ci->ci_request_ipis & ipi_mask) == 0) | | 626 | if ((ci->ci_request_ipis & ipi_mask) == 0) |
614 | return 0; | | 627 | return 0; |
615 | | | 628 | |
616 | atomic_or_64(&ci->ci_active_ipis, ipi_mask); | | 629 | atomic_or_64(&ci->ci_active_ipis, ipi_mask); |
617 | atomic_and_64(&ci->ci_request_ipis, ~ipi_mask); | | 630 | atomic_and_64(&ci->ci_request_ipis, ~ipi_mask); |
618 | | | 631 | |
619 | ipi_process(ci, ipi_mask); | | 632 | ipi_process(ci, ipi_mask); |
620 | | | 633 | |
621 | atomic_and_64(&ci->ci_active_ipis, ~ipi_mask); | | 634 | atomic_and_64(&ci->ci_active_ipis, ~ipi_mask); |
622 | | | 635 | |
623 | return 1; | | 636 | return 1; |
624 | } | | 637 | } |
625 | | | 638 | |
626 | int | | 639 | int |
627 | octeon_send_ipi(struct cpu_info *ci, int req) | | 640 | octeon_send_ipi(struct cpu_info *ci, int req) |
628 | { | | 641 | { |
629 | KASSERT(req < NIPIS); | | 642 | KASSERT(req < NIPIS); |
630 | if (ci == NULL) { | | 643 | if (ci == NULL) { |
631 | CPU_INFO_ITERATOR cii; | | 644 | CPU_INFO_ITERATOR cii; |
632 | for (CPU_INFO_FOREACH(cii, ci)) { | | 645 | for (CPU_INFO_FOREACH(cii, ci)) { |
633 | if (ci != curcpu()) { | | 646 | if (ci != curcpu()) { |
634 | octeon_send_ipi(ci, req); | | 647 | octeon_send_ipi(ci, req); |
635 | } | | 648 | } |
636 | } | | 649 | } |
637 | return 0; | | 650 | return 0; |
638 | } | | 651 | } |
639 | KASSERT(cold || ci->ci_softc != NULL); | | 652 | KASSERT(cold || ci->ci_softc != NULL); |
640 | if (ci->ci_softc == NULL) | | 653 | if (ci->ci_softc == NULL) |
641 | return -1; | | 654 | return -1; |
642 | | | 655 | |
643 | struct cpu_softc * const cpu = ci->ci_softc; | | 656 | struct cpu_softc * const cpu = ci->ci_softc; |
644 | uint64_t ipi_mask = __BIT(req); | | 657 | const uint64_t ipi_mask = octeon_ipi_mask[req]; |
645 | | | 658 | |
646 | atomic_or_64(&ci->ci_request_ipis, ipi_mask); | | 659 | atomic_or_64(&ci->ci_request_ipis, ipi_mask); |
647 | if (req == IPI_SUSPEND || req == IPI_WDOG) { | | | |
648 | ipi_mask <<= 16; | | | |
649 | } | | | |
650 | | | 660 | |
651 | mips3_sd(cpu->cpu_mbox_set, ipi_mask); | | 661 | mips3_sd(cpu->cpu_mbox_set, ipi_mask); |
| | | 662 | |
652 | return 0; | | 663 | return 0; |
653 | } | | 664 | } |
654 | #endif /* MULTIPROCESSOR */ | | 665 | #endif /* MULTIPROCESSOR */ |