Sun Jul 19 07:32:43 2020 UTC ()
fix build with clang/llvm.

clang aarch64 assembler doesn't accept optional number of lanes of vector register.
(but ARMARM says that an assembler must accept it)


(ryo)
diff -r1.4 -r1.5 src/sys/crypto/aes/arch/arm/aes_armv8_64.S
cvs diff -r1.4 -r1.5 src/sys/crypto/aes/arch/arm/aes_armv8_64.S (expand / switch to unified diff)

--- src/sys/crypto/aes/arch/arm/aes_armv8_64.S 2020/06/30 23:06:02 1.4
+++ src/sys/crypto/aes/arch/arm/aes_armv8_64.S 2020/07/19 07:32:43 1.5
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: aes_armv8_64.S,v 1.4 2020/06/30 23:06:02 riastradh Exp $ */ 1/* $NetBSD: aes_armv8_64.S,v 1.5 2020/07/19 07:32:43 ryo Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 4 * Copyright (c) 2020 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -228,46 +228,46 @@ ENTRY(aesarmv8_setenckey192) @@ -228,46 +228,46 @@ ENTRY(aesarmv8_setenckey192)
228 eor v5.16b, v5.16b, v3.16b 228 eor v5.16b, v5.16b, v3.16b
229 eor v5.16b, v5.16b, v6.16b 229 eor v5.16b, v5.16b, v6.16b
230 eor v5.16b, v5.16b, v7.16b 230 eor v5.16b, v5.16b, v7.16b
231 231
232 /* 232 /*
233 * At this point, rk is split across v2.4s = (rk[0],rk[1],...) 233 * At this point, rk is split across v2.4s = (rk[0],rk[1],...)
234 * and v5.4s = (rk[2],rk[3],...); nrk is in v5.4s = 234 * and v5.4s = (rk[2],rk[3],...); nrk is in v5.4s =
235 * (...,nrk[0],nrk[1]); and we have yet to compute nrk[2] or 235 * (...,nrk[0],nrk[1]); and we have yet to compute nrk[2] or
236 * nrk[3], which requires rklo[0] and rklo[1] in v2.4s = 236 * nrk[3], which requires rklo[0] and rklo[1] in v2.4s =
237 * (rklo[0],rklo[1],...). 237 * (rklo[0],rklo[1],...).
238 */ 238 */
239 239
240 /* v1.4s := (nrk[0], nrk[1], nrk[1], nrk[1]) */ 240 /* v1.4s := (nrk[0], nrk[1], nrk[1], nrk[1]) */
241 dup v1.4s, v5.4s[3] 241 dup v1.4s, v5.s[3]
242 mov v1.4s[0], v5.4s[2] 242 mov v1.s[0], v5.s[2]
243 243
244 /* 244 /*
245 * v6.4s := (0, 0, rklo[0], rklo[1]) 245 * v6.4s := (0, 0, rklo[0], rklo[1])
246 * v7.4s := (0, 0, 0, rklo[0]) 246 * v7.4s := (0, 0, 0, rklo[0])
247 */ 247 */
248 ext v6.16b, v0.16b, v2.16b, #8 248 ext v6.16b, v0.16b, v2.16b, #8
249 ext v7.16b, v0.16b, v2.16b, #4 249 ext v7.16b, v0.16b, v2.16b, #4
250 250
251 /* v3.4s := (nrk[0], nrk[1], nrk[2], nrk[3]) */ 251 /* v3.4s := (nrk[0], nrk[1], nrk[2], nrk[3]) */
252 eor v3.16b, v1.16b, v6.16b 252 eor v3.16b, v1.16b, v6.16b
253 eor v3.16b, v3.16b, v7.16b 253 eor v3.16b, v3.16b, v7.16b
254 254
255 /* 255 /*
256 * Recall v2.4s = (rk[0], rk[1], xxx, xxx) 256 * Recall v2.4s = (rk[0], rk[1], xxx, xxx)
257 * and v5.4s = (rk[2], rk[3], xxx, xxx). Set 257 * and v5.4s = (rk[2], rk[3], xxx, xxx). Set
258 * v2.4s := (rk[0], rk[1], rk[2], rk[3]) 258 * v2.4s := (rk[0], rk[1], rk[2], rk[3])
259 */ 259 */
260 mov v2.2d[1], v5.2d[0] 260 mov v2.d[1], v5.d[0]
261 261
262 /* store two round keys */ 262 /* store two round keys */
263 stp q2, q3, [x0], #0x20 263 stp q2, q3, [x0], #0x20
264 264
265 /* 265 /*
266 * Live vector registers at this point: 266 * Live vector registers at this point:
267 * 267 *
268 * q0 = zero 268 * q0 = zero
269 * q2 = rk 269 * q2 = rk
270 * q3 = nrk 270 * q3 = nrk
271 * v5.4s = (rk[2], rk[3], nrk[0], nrk[1]) 271 * v5.4s = (rk[2], rk[3], nrk[0], nrk[1])
272 * q16 = unshiftrows_rotword_1 272 * q16 = unshiftrows_rotword_1
273 * q17 = unshiftrows_rotword_3 273 * q17 = unshiftrows_rotword_3
@@ -315,27 +315,27 @@ ENTRY(aesarmv8_setenckey192) @@ -315,27 +315,27 @@ ENTRY(aesarmv8_setenckey192)
315 315
316 subs x2, x2, #3 /* count down three rounds */ 316 subs x2, x2, #3 /* count down three rounds */
317 str q1, [x0], #0x10 /* store third round key */ 317 str q1, [x0], #0x10 /* store third round key */
318 b.eq 2f 318 b.eq 2f
319 319
320 /* 320 /*
321 * v4.4s := (nrk[2], nrk[3], xxx, xxx) 321 * v4.4s := (nrk[2], nrk[3], xxx, xxx)
322 * v5.4s := (0, nrk[2], xxx, xxx) 322 * v5.4s := (0, nrk[2], xxx, xxx)
323 */ 323 */
324 ext v4.16b, v3.16b, v0.16b, #8 324 ext v4.16b, v3.16b, v0.16b, #8
325 ext v5.16b, v0.16b, v4.16b, #12 325 ext v5.16b, v0.16b, v4.16b, #12
326 326
327 /* v2.4s := (nnrk[3], nnrk[3], xxx, xxx) */ 327 /* v2.4s := (nnrk[3], nnrk[3], xxx, xxx) */
328 dup v2.4s, v1.4s[3] 328 dup v2.4s, v1.s[3]
329 329
330 /* 330 /*
331 * v2.4s := (nnnrklo[0] = nnrk[3] ^ nrk[2], 331 * v2.4s := (nnnrklo[0] = nnrk[3] ^ nrk[2],
332 * nnnrklo[1] = nnrk[3] ^ nrk[2] ^ nrk[3], 332 * nnnrklo[1] = nnrk[3] ^ nrk[2] ^ nrk[3],
333 * xxx, xxx) 333 * xxx, xxx)
334 */ 334 */
335 eor v2.16b, v2.16b, v4.16b 335 eor v2.16b, v2.16b, v4.16b
336 eor v2.16b, v2.16b, v5.16b 336 eor v2.16b, v2.16b, v5.16b
337 337
338 b 1b 338 b 1b
339 339
3402: ret 3402: ret
341END(aesarmv8_setenckey192) 341END(aesarmv8_setenckey192)