Sun Jul 19 08:53:24 2020 UTC ()
Reserve space for all CPU cores (incorrect logic).
Reserve a full page for each core, not incorrect 4096 (from skrll@).


(simonb)
diff -r1.19 -r1.20 src/sys/arch/evbmips/cavium/machdep.c
cvs diff -r1.19 -r1.20 src/sys/arch/evbmips/cavium/machdep.c (expand / switch to unified diff)

--- src/sys/arch/evbmips/cavium/machdep.c 2020/07/19 06:31:13 1.19
+++ src/sys/arch/evbmips/cavium/machdep.c 2020/07/19 08:53:24 1.20
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: machdep.c,v 1.19 2020/07/19 06:31:13 simonb Exp $ */ 1/* $NetBSD: machdep.c,v 1.20 2020/07/19 08:53:24 simonb Exp $ */
2 2
3/* 3/*
4 * Copyright 2001, 2002 Wasabi Systems, Inc. 4 * Copyright 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -104,27 +104,27 @@ @@ -104,27 +104,27 @@
104 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 104 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
105 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 105 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
106 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 106 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
107 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 107 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
108 * SUCH DAMAGE. 108 * SUCH DAMAGE.
109 * 109 *
110 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 110 * @(#)machdep.c 8.3 (Berkeley) 1/12/94
111 * from: Utah Hdr: machdep.c 1.63 91/04/24 111 * from: Utah Hdr: machdep.c 1.63 91/04/24
112 */ 112 */
113 113
114#include "opt_multiprocessor.h" 114#include "opt_multiprocessor.h"
115 115
116#include <sys/cdefs.h> 116#include <sys/cdefs.h>
117__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.19 2020/07/19 06:31:13 simonb Exp $"); 117__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.20 2020/07/19 08:53:24 simonb Exp $");
118 118
119#include <sys/param.h> 119#include <sys/param.h>
120#include <sys/systm.h> 120#include <sys/systm.h>
121#include <sys/kernel.h> 121#include <sys/kernel.h>
122#include <sys/buf.h> 122#include <sys/buf.h>
123#include <sys/cpu.h> 123#include <sys/cpu.h>
124#include <sys/reboot.h> 124#include <sys/reboot.h>
125#include <sys/mount.h> 125#include <sys/mount.h>
126#include <sys/kcore.h> 126#include <sys/kcore.h>
127#include <sys/boot_flag.h> 127#include <sys/boot_flag.h>
128#include <sys/termios.h> 128#include <sys/termios.h>
129#include <sys/ksyms.h> 129#include <sys/ksyms.h>
130 130
@@ -361,28 +361,30 @@ mach_init_memory(void) @@ -361,28 +361,30 @@ mach_init_memory(void)
361 361
362 for (i = 0; i < VM_PHYSSEG_MAX && blockaddr != 0; 362 for (i = 0; i < VM_PHYSSEG_MAX && blockaddr != 0;
363 i++, blockaddr = block->bbh_next_block_addr) { 363 i++, blockaddr = block->bbh_next_block_addr) {
364 block = (void *)MIPS_PHYS_TO_XKPHYS(CCA_CACHEABLE, blockaddr); 364 block = (void *)MIPS_PHYS_TO_XKPHYS(CCA_CACHEABLE, blockaddr);
365 365
366 mem_clusters[mem_cluster_cnt].start = blockaddr; 366 mem_clusters[mem_cluster_cnt].start = blockaddr;
367 mem_clusters[mem_cluster_cnt].size = block->bbh_size; 367 mem_clusters[mem_cluster_cnt].size = block->bbh_size;
368 mem_cluster_cnt++; 368 mem_cluster_cnt++;
369 } 369 }
370 370
371 physmem = btoc(octeon_btinfo.obt_dram_size * 1024 * 1024); 371 physmem = btoc(octeon_btinfo.obt_dram_size * 1024 * 1024);
372 372
373#ifdef MULTIPROCESSOR 373#ifdef MULTIPROCESSOR
374 const u_int cores = mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM; 374 const uint64_t fuse = octeon_xkphys_read_8(CIU_FUSE);
375 mem_clusters[0].start = cores * 4096; 375 const int cores = popcount64(fuse);
 376 mem_clusters[0].start += cores * PAGE_SIZE;
 377 mem_clusters[0].size -= cores * PAGE_SIZE;
376#endif 378#endif
377 379
378 /* 380 /*
379 * Load the rest of the available pages into the VM system. 381 * Load the rest of the available pages into the VM system.
380 */ 382 */
381 mips_page_physload(mips_trunc_page(kernel_text), mips_round_page(end), 383 mips_page_physload(mips_trunc_page(kernel_text), mips_round_page(end),
382 mem_clusters, mem_cluster_cnt, NULL, 0); 384 mem_clusters, mem_cluster_cnt, NULL, 0);
383 385
384 /* 386 /*
385 * Initialize error message buffer (at end of core). 387 * Initialize error message buffer (at end of core).
386 */ 388 */
387 mips_init_msgbuf(); 389 mips_init_msgbuf();
388 390