Mon Jul 20 03:24:59 2020 UTC ()
Remove check/limit for only 2 cores.
Use MIPS_EBASE_CPUNUM instead of magic numbers.


(simonb)
diff -r1.10 -r1.11 src/sys/arch/mips/mips/locore_octeon.S
cvs diff -r1.10 -r1.11 src/sys/arch/mips/mips/locore_octeon.S (expand / switch to unified diff)

--- src/sys/arch/mips/mips/locore_octeon.S 2016/07/27 09:32:35 1.10
+++ src/sys/arch/mips/mips/locore_octeon.S 2020/07/20 03:24:59 1.11
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: locore_octeon.S,v 1.10 2016/07/27 09:32:35 skrll Exp $ */ 1/* $NetBSD: locore_octeon.S,v 1.11 2020/07/20 03:24:59 simonb Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 4 * Copyright (c) 2007 Internet Initiative Japan, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -17,37 +17,37 @@ @@ -17,37 +17,37 @@
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE. 26 * SUCH DAMAGE.
27 */ 27 */
28 28
29#include <mips/asm.h> 29#include <mips/asm.h>
30RCSID("$NetBSD: locore_octeon.S,v 1.10 2016/07/27 09:32:35 skrll Exp $") 30RCSID("$NetBSD: locore_octeon.S,v 1.11 2020/07/20 03:24:59 simonb Exp $")
31 31
32#include "cpunode.h" /* for NWDOG */ 32#include "cpunode.h" /* for NWDOG */
33#include "opt_cputype.h" 33#include "opt_cputype.h"
34#include "opt_ddb.h" 34#include "opt_ddb.h"
35#include "opt_multiprocessor.h" 35#include "opt_multiprocessor.h"
36 36
37#include <mips/cpuregs.h> 37#include <mips/cpuregs.h>
38#include <arch/mips/cavium/dev/octeon_corereg.h> 38#include <arch/mips/cavium/dev/octeon_corereg.h>
39 39
40RCSID("$NetBSD: locore_octeon.S,v 1.10 2016/07/27 09:32:35 skrll Exp $") 40RCSID("$NetBSD: locore_octeon.S,v 1.11 2020/07/20 03:24:59 simonb Exp $")
41 41
42#include "assym.h" 42#include "assym.h"
43 43
44#define _CP0_READ64(_cp0) \ 44#define _CP0_READ64(_cp0) \
45 dmfc0 v0, _cp0; \ 45 dmfc0 v0, _cp0; \
46 j ra; \ 46 j ra; \
47 nop 47 nop
48 48
49#define _CP0_WRITE64(_cp0) \ 49#define _CP0_WRITE64(_cp0) \
50 dmtc0 a0, _cp0; \ 50 dmtc0 a0, _cp0; \
51 j ra; \ 51 j ra; \
52 nop 52 nop
53 53
@@ -112,80 +112,71 @@ END(mips_cp0_performance_counter_counter @@ -112,80 +112,71 @@ END(mips_cp0_performance_counter_counter
112LEAF(mips_cp0_performance_counter_counter1_write) 112LEAF(mips_cp0_performance_counter_counter1_write)
113 _CP0_WRITE64(CP0_PCCNT1) 113 _CP0_WRITE64(CP0_PCCNT1)
114END(mips_cp0_performance_counter_counter1_write) 114END(mips_cp0_performance_counter_counter1_write)
115 115
116#ifdef MULTIPROCESSOR 116#ifdef MULTIPROCESSOR
117 117
118NESTED_NOPROFILE(octeon_cpu_spinup, 0, ra) 118NESTED_NOPROFILE(octeon_cpu_spinup, 0, ra)
119 // 119 //
120 // Since the OCTEON cpus doesn't a COP0 OSCONTEXT register, each core 120 // Since the OCTEON cpus doesn't a COP0 OSCONTEXT register, each core
121 // must has its own exception vector page. The exceptions will be 121 // must has its own exception vector page. The exceptions will be
122 // modified to refer to that CPU's cpu_info structure. 122 // modified to refer to that CPU's cpu_info structure.
123 // 123 //
124 mfc0 s1, MIPS_COP_0_EBASE # get EBASE 124 mfc0 s1, MIPS_COP_0_EBASE # get EBASE
125 ext s0, s1, 0, 10 # fetch cpunum (MIPSNNR2) 125 andi s0, s1, MIPS_EBASE_CPUNUM # fetch cpunum
126 ins s1, zero, 0, 10 # clear it (MIPSNNR2) 126 # insert cpunum as exception address base:
127 ins s1, s0, 12, 10 # insert cpunum as exception address 127 ins s1, s0, MIPS_EBASE_EXC_BASE_SHIFT, MIPS_EBASE_CPUNUM_WIDTH
128 ehb 128 ehb
129 mtc0 s1, MIPS_COP_0_EBASE # set EBASE 129 mtc0 s1, MIPS_COP_0_EBASE # set EBASE
130 COP0_SYNC 130 COP0_SYNC
131 131
132 // we only can deal with 2 cores 
133 li v0, 1 
134 beq s0, v0, 2f 
135 nop 
136 // spin if this isn't cpu 1 
1371: wait 
138 b 1b 
139 nop 
140 
141 // Indicate this CPU was started by u-boot 132 // Indicate this CPU was started by u-boot
1422: PTR_LA t0, _C_LABEL(cpus_booted) # get addr for kcpuset 133 PTR_LA t0, _C_LABEL(cpus_booted) # get addr for kcpuset
1433: sync 1341: sync
144 PTR_L a0, (t0) # get kcpuset 135 PTR_L a0, (t0) # get kcpuset
145 beqz a0, 3b # loop until not NULL 136 beqz a0, 1b # loop until not NULL
146 nop 137 nop
147 jal _C_LABEL(kcpuset_atomic_set) 138 jal _C_LABEL(kcpuset_atomic_set)
148 move a1, s0 # pass it our cpu number 139 move a1, s0 # pass it our cpu number
149 140
150 // Wait until cpuid_infos[cpunum] is not NULL. 141 // Wait until cpuid_infos[cpunum] is not NULL.
151 PTR_LA a1, _C_LABEL(cpuid_infos) 142 PTR_LA a1, _C_LABEL(cpuid_infos)
152 dsll v0, s0, PTR_SCALESHIFT # cpunum -> array index 143 dsll v0, s0, PTR_SCALESHIFT # cpunum -> array index
153 PTR_ADD t0, a1, v0 # add to array start 144 PTR_ADD t0, a1, v0 # add to array start
1544: sync 1451: sync
155 PTR_L a1, (t0) # get cpu_info pointer 146 PTR_L a1, (t0) # get cpu_info pointer
156 beqz a1, 4b # loop until non-NULL 147 beqz a1, 1b # loop until non-NULL
157 nop 148 nop
158 149
159 j _C_LABEL(cpu_trampoline) 150 j _C_LABEL(cpu_trampoline)
160 nop 151 nop
161END(octeon_cpu_spinup) 152END(octeon_cpu_spinup)
162#endif /* MULTIPROCESSOR */ 153#endif /* MULTIPROCESSOR */
163 154
164#if NWDOG > 0 || defined(DDB) 155#if NWDOG > 0 || defined(DDB)
165 156
166#define UINT64_C(x) (x) 157#define UINT64_C(x) (x)
167 158
168#include <mips/cavium/dev/octeon_ciureg.h> 159#include <mips/cavium/dev/octeon_ciureg.h>
169 160
170NESTED_NOPROFILE(octeon_reset_vector, 0, ra) 161NESTED_NOPROFILE(octeon_reset_vector, 0, ra)
171 mfc0 k0, MIPS_COP_0_STATUS # get cp0 status 162 mfc0 k0, MIPS_COP_0_STATUS # get cp0 status
172 bbit1 k0, V_MIPS3_SR_SR, 1f # MIPS3_SR_SR 163 bbit1 k0, V_MIPS3_SR_SR, 1f # MIPS3_SR_SR
173 ins k0, zero, V_MIPS_SR_BEV, 1 # clear boot exception vectors 164 ins k0, zero, V_MIPS_SR_BEV, 1 # clear boot exception vectors
174 mtc0 k0, MIPS_COP_0_STATUS # write cp0 status 165 mtc0 k0, MIPS_COP_0_STATUS # write cp0 status
175 ehb # hazard barrier 166 ehb # hazard barrier
176#ifdef MULTIPROCESSOR 167#ifdef MULTIPROCESSOR
177 mfc0 k0, MIPS_COP_0_EBASE # get EBASE 168 mfc0 k0, MIPS_COP_0_EBASE # get EBASE
178 ext k0, k0, 0, 10 # select cpunum 169 andi k0, k0, MIPS_EBASE_CPUNUM # fetch cpunum
179 dsll k0, k0, PTR_SCALESHIFT # cpunum -> array index 170 dsll k0, k0, PTR_SCALESHIFT # cpunum -> array index
180 PTR_LA k1, _C_LABEL(cpuid_infos) 171 PTR_LA k1, _C_LABEL(cpuid_infos)
181 PTR_ADDU k1, k1, k0 # add to array start 172 PTR_ADDU k1, k1, k0 # add to array start
182 PTR_L k0, (k1) # get cpu_info 173 PTR_L k0, (k1) # get cpu_info
183#else 174#else
184 PTR_LA k0, _C_LABEL(cpu_info_store) # get cpu_info 175 PTR_LA k0, _C_LABEL(cpu_info_store) # get cpu_info
185#endif 176#endif
186 j _C_LABEL(mips64r2_kern_nonmaskable_intr) 177 j _C_LABEL(mips64r2_kern_nonmaskable_intr)
187 sd zero, CIU_NMI_OFFSET(k1)# clear NMI 178 sd zero, CIU_NMI_OFFSET(k1)# clear NMI
1881: 1791:
189 li k1, ((MIPS_XKPHYS_START|CIU_BASE) >> 32) # CIU base (MSW) 180 li k1, ((MIPS_XKPHYS_START|CIU_BASE) >> 32) # CIU base (MSW)
190 dsll k1, 32 # shift it place 181 dsll k1, 32 # shift it place
191 ld k0, CIU_FUSE_OFFSET(k1) # get mask of CPUs 182 ld k0, CIU_FUSE_OFFSET(k1) # get mask of CPUs