 @@ -1,14 +1,14 @@
-/*	$NetBSD: octeon_intr.c,v 1.18 2020/07/17 21:59:30 jmcneill Exp $	*/
+/*	$NetBSD: octeon_intr.c,v 1.19 2020/07/20 13:30:41 jmcneill Exp $	*/
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
 @@ -34,27 +34,27 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Platform-specific interrupt support for the MIPS Malta.
  */
 #include "opt_multiprocessor.h"
 #include "cpunode.h"
 #define __INTR_PRIVATE
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.18 2020/07/17 21:59:30 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.19 2020/07/20 13:30:41 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/cpu.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/kernel.h>
 #include <sys/kmem.h>
 #include <sys/atomic.h>
 #include <lib/libkern/libkern.h>
 #include <mips/locore.h>
 @@ -166,27 +166,27 @@ struct octeon_intrhand ipi_intrhands[2]
 		.ih_ipl = IPL_SCHED,
 	},
 	[1] = {
 		.ih_func = octeon_ipi_intr,
 		.ih_arg = (void *)(uintptr_t)__BITS(31,16),
 		.ih_irq = CIU_INT_MBOX_31_16,
 		.ih_ipl = IPL_HIGH,
 	},
 };
 #define	OCTEON_IPI_SCHED(n)	__BIT((n) + 0)
 #define	OCTEON_IPI_HIGH(n)	__BIT((n) + 16)
-static uint64_t octeon_ipi_mask[NIPIS] = {
+static uint32_t octeon_ipi_mbox_mask[NIPIS] = {
 	[IPI_NOP]		= OCTEON_IPI_SCHED(IPI_NOP),
 	[IPI_AST]		= OCTEON_IPI_SCHED(IPI_AST),
 	[IPI_SHOOTDOWN]		= OCTEON_IPI_SCHED(IPI_SHOOTDOWN),
 	[IPI_SYNCICACHE]	= OCTEON_IPI_SCHED(IPI_SYNCICACHE),
 	[IPI_KPREEMPT]		= OCTEON_IPI_SCHED(IPI_KPREEMPT),
 	[IPI_SUSPEND]		= OCTEON_IPI_HIGH(IPI_SUSPEND),
 	[IPI_HALT]		= OCTEON_IPI_HIGH(IPI_HALT),
 	[IPI_XCALL]		= OCTEON_IPI_HIGH(IPI_XCALL),
 	[IPI_GENERIC]		= OCTEON_IPI_HIGH(IPI_GENERIC),
 	[IPI_WDOG]		= OCTEON_IPI_HIGH(IPI_WDOG),
 };
 #endif
 @@ -506,36 +506,41 @@ octeon_iointr(int ipl, vaddr_t pc, uint3
+		}
+	}
 	KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
+}
 #ifdef MULTIPROCESSOR
 __CTASSERT(NIPIS < 16);
 int
 octeon_ipi_intr(void *arg)
+{
 	struct cpu_info * const ci = curcpu();
 	struct cpu_softc * const cpu = ci->ci_softc;
-	uint32_t ipi_mask = (uintptr_t) arg;
+	uint32_t mbox_mask = (uintptr_t) arg;
 	uint32_t ipi_mask;
-	KASSERTMSG((ipi_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED,
+	KASSERTMSG((mbox_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED,
-	    "ipi_mask %#"PRIx32" cpl %d", ipi_mask, ci->ci_cpl);
+	    "mbox_mask %#"PRIx32" cpl %d", mbox_mask, ci->ci_cpl);
-	ipi_mask &= mips3_ld(cpu->cpu_mbox_set);
+	mbox_mask &= mips3_ld(cpu->cpu_mbox_set);
-	if (ipi_mask == 0)
+	if (mbox_mask == 0)
 		return 0;
-	mips3_sd(cpu->cpu_mbox_clr, ipi_mask);
+	mips3_sd(cpu->cpu_mbox_clr, mbox_mask);
 	ipi_mask = mbox_mask;
 	if (ci->ci_cpl >= IPL_SCHED)
 		ipi_mask >>= 16;
 	KASSERT(ipi_mask < __BIT(NIPIS));
 #if NWDOG > 0
 	// Handle WDOG requests ourselves.
 	if (ipi_mask & __BIT(IPI_WDOG)) {
 		softint_schedule(cpu->cpu_wdog_sih);
 		atomic_and_64(&ci->ci_request_ipis, ~__BIT(IPI_WDOG));
 		ipi_mask &= ~__BIT(IPI_WDOG);
 		ci->ci_evcnt_per_ipi[IPI_WDOG].ev_count++;
 		if (__predict_true(ipi_mask == 0))
 			return 1;
+	}
 @@ -563,22 +568,23 @@ octeon_send_ipi(struct cpu_info *ci, int
 		CPU_INFO_ITERATOR cii;
 		for (CPU_INFO_FOREACH(cii, ci)) {
 			if (ci != curcpu()) {
 				octeon_send_ipi(ci, req);
+			}
+		}
 		return 0;
+	}
 	KASSERT(cold || ci->ci_softc != NULL);
 	if (ci->ci_softc == NULL)
 		return -1;
 	struct cpu_softc * const cpu = ci->ci_softc;
-	const uint64_t ipi_mask = octeon_ipi_mask[req];
+	const uint32_t mbox_mask = octeon_ipi_mbox_mask[req];
 	const uint32_t ipi_mask = __BIT(req);
 	atomic_or_64(&ci->ci_request_ipis, ipi_mask);
-	mips3_sd(cpu->cpu_mbox_set, ipi_mask);
+	mips3_sd(cpu->cpu_mbox_set, mbox_mask);
 	return 0;
+}
 #endif	/* MULTIPROCESSOR */