Mon Jul 27 10:59:11 2020 UTC ()
s/MODULE/_MODULE/

spotted by chuq@


(skrll)
diff -r1.15 -r1.16 src/sys/arch/mips/include/cache.h
cvs diff -r1.15 -r1.16 src/sys/arch/mips/include/cache.h (expand / switch to unified diff)

--- src/sys/arch/mips/include/cache.h 2020/07/26 08:08:41 1.15
+++ src/sys/arch/mips/include/cache.h 2020/07/27 10:59:10 1.16
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cache.h,v 1.15 2020/07/26 08:08:41 simonb Exp $ */ 1/* $NetBSD: cache.h,v 1.16 2020/07/27 10:59:10 skrll Exp $ */
2 2
3/* 3/*
4 * Copyright 2001 Wasabi Systems, Inc. 4 * Copyright 2001 Wasabi Systems, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -218,27 +218,27 @@ struct mips_cache_info { @@ -218,27 +218,27 @@ struct mips_cache_info {
218 u_int mci_dcache_align_mask; 218 u_int mci_dcache_align_mask;
219 219
220 u_int mci_cache_prefer_mask; 220 u_int mci_cache_prefer_mask;
221 u_int mci_cache_alias_mask; 221 u_int mci_cache_alias_mask;
222 u_int mci_icache_alias_mask; 222 u_int mci_icache_alias_mask;
223 223
224 bool mci_cache_virtual_alias; 224 bool mci_cache_virtual_alias;
225 bool mci_icache_virtual_alias; 225 bool mci_icache_virtual_alias;
226}; 226};
227 227
228 228
229#if (MIPS1 + MIPS64_RMIXL + MIPS64R2_RMIXL + MIPS64_OCTEON) > 0 && \ 229#if (MIPS1 + MIPS64_RMIXL + MIPS64R2_RMIXL + MIPS64_OCTEON) > 0 && \
230 (MIPS3 + MIPS4) == 0 \ 230 (MIPS3 + MIPS4) == 0 \
231 && !defined(MODULE) 231 && !defined(_MODULE)
232#define MIPS_CACHE_ALIAS_MASK 0 232#define MIPS_CACHE_ALIAS_MASK 0
233#define MIPS_CACHE_VIRTUAL_ALIAS false 233#define MIPS_CACHE_VIRTUAL_ALIAS false
234#else 234#else
235#define MIPS_CACHE_ALIAS_MASK mips_cache_info.mci_cache_alias_mask 235#define MIPS_CACHE_ALIAS_MASK mips_cache_info.mci_cache_alias_mask
236#define MIPS_CACHE_VIRTUAL_ALIAS mips_cache_info.mci_cache_virtual_alias 236#define MIPS_CACHE_VIRTUAL_ALIAS mips_cache_info.mci_cache_virtual_alias
237#endif 237#endif
238#if (MIPS1 + MIPS64_RMIXL + MIPS64_OCTEON) > 0 && \ 238#if (MIPS1 + MIPS64_RMIXL + MIPS64_OCTEON) > 0 && \
239 (MIPS3 + MIPS4) == 0 \ 239 (MIPS3 + MIPS4) == 0 \
240 && !defined(_MODULE) 240 && !defined(_MODULE)
241#define MIPS_ICACHE_ALIAS_MASK 0 241#define MIPS_ICACHE_ALIAS_MASK 0
242#define MIPS_ICACHE_VIRTUAL_ALIAS false 242#define MIPS_ICACHE_VIRTUAL_ALIAS false
243#else 243#else
244#define MIPS_ICACHE_ALIAS_MASK mips_cache_info.mci_icache_alias_mask 244#define MIPS_ICACHE_ALIAS_MASK mips_cache_info.mci_icache_alias_mask