Wed Aug 5 15:40:46 2020 UTC ()
Add new fields here and there.


(maxv)
diff -r1.170 -r1.171 src/sys/arch/x86/include/specialreg.h
cvs diff -r1.170 -r1.171 src/sys/arch/x86/include/specialreg.h (expand / switch to unified diff)

--- src/sys/arch/x86/include/specialreg.h 2020/07/20 05:50:55 1.170
+++ src/sys/arch/x86/include/specialreg.h 2020/08/05 15:40:46 1.171
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: specialreg.h,v 1.170 2020/07/20 05:50:55 maxv Exp $ */ 1/* $NetBSD: specialreg.h,v 1.171 2020/08/05 15:40:46 maxv Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. 4 * Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -99,77 +99,81 @@ @@ -99,77 +99,81 @@
99 */ 99 */
100#define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 100#define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */
101#define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 101#define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */
102#define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 */ 102#define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 */
103#define CR4_DE 0x00000008 /* debugging extension */ 103#define CR4_DE 0x00000008 /* debugging extension */
104#define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 104#define CR4_PSE 0x00000010 /* large (4MB) page size enable */
105#define CR4_PAE 0x00000020 /* physical address extension enable */ 105#define CR4_PAE 0x00000020 /* physical address extension enable */
106#define CR4_MCE 0x00000040 /* machine check enable */ 106#define CR4_MCE 0x00000040 /* machine check enable */
107#define CR4_PGE 0x00000080 /* page global enable */ 107#define CR4_PGE 0x00000080 /* page global enable */
108#define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 108#define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */
109#define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 109#define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */
110#define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 110#define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
111#define CR4_UMIP 0x00000800 /* user-mode instruction prevention */ 111#define CR4_UMIP 0x00000800 /* user-mode instruction prevention */
 112#define CR4_LA57 0x00001000 /* 57-bit linear addresses */
112#define CR4_VMXE 0x00002000 /* enable VMX operations */ 113#define CR4_VMXE 0x00002000 /* enable VMX operations */
113#define CR4_SMXE 0x00004000 /* enable SMX operations */ 114#define CR4_SMXE 0x00004000 /* enable SMX operations */
114#define CR4_FSGSBASE 0x00010000 /* enable *FSBASE and *GSBASE instructions */ 115#define CR4_FSGSBASE 0x00010000 /* enable *FSBASE and *GSBASE instructions */
115#define CR4_PCIDE 0x00020000 /* enable Process Context IDentifiers */ 116#define CR4_PCIDE 0x00020000 /* enable Process Context IDentifiers */
116#define CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ 117#define CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
117#define CR4_SMEP 0x00100000 /* enable SMEP support */ 118#define CR4_SMEP 0x00100000 /* enable SMEP support */
118#define CR4_SMAP 0x00200000 /* enable SMAP support */ 119#define CR4_SMAP 0x00200000 /* enable SMAP support */
119#define CR4_PKE 0x00400000 /* protection key enable */ 120#define CR4_PKE 0x00400000 /* enable Protection Keys for user pages */
 121#define CR4_CET 0x00800000 /* enable CET */
 122#define CR4_PKS 0x01000000 /* enable Protection Keys for kern pages */
120 123
121/* 124/*
122 * Extended Control Register XCR0 125 * Extended Control Register XCR0
123 */ 126 */
124#define XCR0_X87 0x00000001 /* x87 FPU/MMX state */ 127#define XCR0_X87 0x00000001 /* x87 FPU/MMX state */
125#define XCR0_SSE 0x00000002 /* SSE state */ 128#define XCR0_SSE 0x00000002 /* SSE state */
126#define XCR0_YMM_Hi128 0x00000004 /* AVX-256 (ymmn registers) */ 129#define XCR0_YMM_Hi128 0x00000004 /* AVX-256 (ymmn registers) */
127#define XCR0_BNDREGS 0x00000008 /* Memory protection ext bounds */ 130#define XCR0_BNDREGS 0x00000008 /* Memory protection ext bounds */
128#define XCR0_BNDCSR 0x00000010 /* Memory protection ext state */ 131#define XCR0_BNDCSR 0x00000010 /* Memory protection ext state */
129#define XCR0_Opmask 0x00000020 /* AVX-512 Opmask */ 132#define XCR0_Opmask 0x00000020 /* AVX-512 Opmask */
130#define XCR0_ZMM_Hi256 0x00000040 /* AVX-512 upper 256 bits low regs */ 133#define XCR0_ZMM_Hi256 0x00000040 /* AVX-512 upper 256 bits low regs */
131#define XCR0_Hi16_ZMM 0x00000080 /* AVX-512 512 bits upper registers */ 134#define XCR0_Hi16_ZMM 0x00000080 /* AVX-512 512 bits upper registers */
132#define XCR0_PT 0x00000100 /* Processor Trace state */ 135#define XCR0_PT 0x00000100 /* Processor Trace state */
133#define XCR0_PKRU 0x00000200 /* Protection Key state */ 136#define XCR0_PKRU 0x00000200 /* Protection Key state */
 137#define XCR0_CET_U 0x00000800 /* User CET state */
 138#define XCR0_CET_S 0x00001000 /* Kern CET state */
134#define XCR0_HDC 0x00002000 /* Hardware Duty Cycle state */ 139#define XCR0_HDC 0x00002000 /* Hardware Duty Cycle state */
 140#define XCR0_HWP 0x00010000 /* Hardware P-states */
135 141
136#define XCR0_FLAGS1 "\20" \ 142#define XCR0_FLAGS1 "\20" \
137 "\1" "x87" "\2" "SSE" "\3" "AVX" \ 143 "\1" "x87" "\2" "SSE" "\3" "AVX" \
138 "\4" "BNDREGS" "\5" "BNDCSR" "\6" "Opmask" \ 144 "\4" "BNDREGS" "\5" "BNDCSR" "\6" "Opmask" \
139 "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" "\11" "PT" \ 145 "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" "\11" "PT" \
140 "\12" "PKRU" "\16" "HDC" 146 "\12" "PKRU" "\14" "CET_U" "\15" "CET_S" \
 147 "\16" "HDC" "\21" "HWP"
141 148
142/* 149/*
143 * Known FPU bits, only these get enabled. The save area is sized for all the 150 * Known FPU bits, only these get enabled. The save area is sized for all the
144 * fields below. 151 * fields below.
145 */ 152 */
146#define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \ 153#define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \
147 XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) 154 XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM)
148 155
149/* 156/*
150 * XSAVE component indices. 157 * XSAVE component indices, internal to NetBSD.
151 */ 158 */
152#define XSAVE_X87 0 159#define XSAVE_X87 0
153#define XSAVE_SSE 1 160#define XSAVE_SSE 1
154#define XSAVE_YMM_Hi128 2 161#define XSAVE_YMM_Hi128 2
155#define XSAVE_BNDREGS 3 162#define XSAVE_BNDREGS 3
156#define XSAVE_BNDCSR 4 163#define XSAVE_BNDCSR 4
157#define XSAVE_Opmask 5 164#define XSAVE_Opmask 5
158#define XSAVE_ZMM_Hi256 6 165#define XSAVE_ZMM_Hi256 6
159#define XSAVE_Hi16_ZMM 7 166#define XSAVE_Hi16_ZMM 7
160#define XSAVE_PT 8 
161#define XSAVE_PKRU 9 
162#define XSAVE_HDC 10 
163 167
164/* 168/*
165 * Highest XSAVE component enabled by XCR0_FPU. 169 * Highest XSAVE component enabled by XCR0_FPU.
166 */ 170 */
167#define XSAVE_MAX_COMPONENT XSAVE_Hi16_ZMM 171#define XSAVE_MAX_COMPONENT XSAVE_Hi16_ZMM
168 172
169/* 173/*
170 * CPUID "features" bits 174 * CPUID "features" bits
171 */ 175 */
172 176
173/* Fn00000001 %edx features */ 177/* Fn00000001 %edx features */
174#define CPUID_FPU 0x00000001 /* processor has an FPU? */ 178#define CPUID_FPU 0x00000001 /* processor has an FPU? */
175#define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 179#define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
@@ -438,60 +442,60 @@ @@ -438,60 +442,60 @@
438 "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ 442 "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \
439 "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \ 443 "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \
440 "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ 444 "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \
441 "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL" 445 "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL"
442 446
443/* %ecx */ 447/* %ecx */
444#define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */ 448#define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */
445#define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */ 449#define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */
446#define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */ 450#define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */
447#define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */ 451#define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */
448#define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */ 452#define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */
449#define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */ 453#define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */
450#define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */ 454#define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */
451#define CPUID_SEF_CET_SS __BIT(7) /* CET shadow stack */ 455#define CPUID_SEF_CET_SS __BIT(7) /* CET Shadow Stack */
452#define CPUID_SEF_GFNI __BIT(8) 456#define CPUID_SEF_GFNI __BIT(8)
453#define CPUID_SEF_VAES __BIT(9) 457#define CPUID_SEF_VAES __BIT(9)
454#define CPUID_SEF_VPCLMULQDQ __BIT(10) 458#define CPUID_SEF_VPCLMULQDQ __BIT(10)
455#define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector neural Network Instruction */ 459#define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector neural Network Instruction */
456#define CPUID_SEF_AVX512_BITALG __BIT(12) 460#define CPUID_SEF_AVX512_BITALG __BIT(12)
457#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) 461#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14)
458#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */ 462#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */
459#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */ 463#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */
460#define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */ 464#define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */
461#define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ 465#define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */
462#define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ 466#define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */
463#define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ 467#define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */
464#define CPUID_SEF_PKS __BIT(31) /* Protection Keys */ 468#define CPUID_SEF_PKS __BIT(31) /* Protection Keys for Kern-mode pages */
465 469
466#define CPUID_SEF_FLAGS1 "\177\20" \ 470#define CPUID_SEF_FLAGS1 "\177\20" \
467 "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ 471 "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \
468 "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \ 472 "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \
469 "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ 473 "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
470 "b\14AVX512_BITALG\0" "b\16AVX512_VPOPCNTDQ\0" \ 474 "b\14AVX512_BITALG\0" "b\16AVX512_VPOPCNTDQ\0" \
471 "f\21\5MAWAU\0" \ 475 "f\21\5MAWAU\0" \
472 "b\26RDPID\0" \ 476 "b\26RDPID\0" \
473 "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ 477 "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
474 "b\34MOVDIR64B\0" "b\36SGXLC\0" "b\37PKS\0" 478 "b\34MOVDIR64B\0" "b\36SGXLC\0" "b\37PKS\0"
475 479
476/* %edx */ 480/* %edx */
477#define CPUID_SEF_AVX512_4VNNIW __BIT(2) 481#define CPUID_SEF_AVX512_4VNNIW __BIT(2)
478#define CPUID_SEF_AVX512_4FMAPS __BIT(3) 482#define CPUID_SEF_AVX512_4FMAPS __BIT(3)
479#define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */ 483#define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */
480#define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) 484#define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8)
481#define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ 485#define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */
482#define CPUID_SEF_MD_CLEAR __BIT(10) 486#define CPUID_SEF_MD_CLEAR __BIT(10)
483#define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ 487#define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */
484#define CPUID_SEF_SERIALIZE __BIT(14) 488#define CPUID_SEF_SERIALIZE __BIT(14) /* SERIALIZE instruction */
485#define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */ 489#define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */
486#define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */ 490#define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */
487#define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */ 491#define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */
488#define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ 492#define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */
489#define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ 493#define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */
490#define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */ 494#define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */
491#define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */ 495#define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */
492#define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */ 496#define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */
493#define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */ 497#define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */
494 498
495#define CPUID_SEF_FLAGS2 "\20" \ 499#define CPUID_SEF_FLAGS2 "\20" \
496 "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ 500 "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
497 "\5" "FSREP_MOV" \ 501 "\5" "FSREP_MOV" \