Tue Aug 18 07:41:41 2020 UTC ()
Fix MULTIPROCESSOR build


(skrll)
diff -r1.23 -r1.24 src/sys/arch/mips/cavium/octeon_intr.c
cvs diff -r1.23 -r1.24 src/sys/arch/mips/cavium/octeon_intr.c (expand / switch to unified diff)

--- src/sys/arch/mips/cavium/octeon_intr.c 2020/08/17 21:00:29 1.23
+++ src/sys/arch/mips/cavium/octeon_intr.c 2020/08/18 07:41:41 1.24
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: octeon_intr.c,v 1.23 2020/08/17 21:00:29 jmcneill Exp $ */ 1/* $NetBSD: octeon_intr.c,v 1.24 2020/08/18 07:41:41 skrll Exp $ */
2/* 2/*
3 * Copyright 2001, 2002 Wasabi Systems, Inc. 3 * Copyright 2001, 2002 Wasabi Systems, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 6 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
7 * 7 *
8 * Redistribution and use in source and binary forms, with or without 8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions 9 * modification, are permitted provided that the following conditions
10 * are met: 10 * are met:
11 * 1. Redistributions of source code must retain the above copyright 11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer. 12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright 13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the 14 * notice, this list of conditions and the following disclaimer in the
@@ -34,27 +34,27 @@ @@ -34,27 +34,27 @@
34 * POSSIBILITY OF SUCH DAMAGE. 34 * POSSIBILITY OF SUCH DAMAGE.
35 */ 35 */
36 36
37/* 37/*
38 * Platform-specific interrupt support for the MIPS Malta. 38 * Platform-specific interrupt support for the MIPS Malta.
39 */ 39 */
40 40
41#include "opt_multiprocessor.h" 41#include "opt_multiprocessor.h"
42 42
43#include "cpunode.h" 43#include "cpunode.h"
44#define __INTR_PRIVATE 44#define __INTR_PRIVATE
45 45
46#include <sys/cdefs.h> 46#include <sys/cdefs.h>
47__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.23 2020/08/17 21:00:29 jmcneill Exp $"); 47__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.24 2020/08/18 07:41:41 skrll Exp $");
48 48
49#include <sys/param.h> 49#include <sys/param.h>
50#include <sys/cpu.h> 50#include <sys/cpu.h>
51#include <sys/systm.h> 51#include <sys/systm.h>
52#include <sys/device.h> 52#include <sys/device.h>
53#include <sys/intr.h> 53#include <sys/intr.h>
54#include <sys/kernel.h> 54#include <sys/kernel.h>
55#include <sys/kmem.h> 55#include <sys/kmem.h>
56#include <sys/atomic.h> 56#include <sys/atomic.h>
57 57
58#include <lib/libkern/libkern.h> 58#include <lib/libkern/libkern.h>
59 59
60#include <mips/locore.h> 60#include <mips/locore.h>
@@ -156,27 +156,27 @@ static const char * octeon_intrnames[NIR @@ -156,27 +156,27 @@ static const char * octeon_intrnames[NIR
156}; 156};
157 157
158struct octeon_intrhand { 158struct octeon_intrhand {
159 int (*ih_func)(void *); 159 int (*ih_func)(void *);
160 void *ih_arg; 160 void *ih_arg;
161 int ih_irq; 161 int ih_irq;
162 int ih_ipl; 162 int ih_ipl;
163}; 163};
164 164
165#ifdef MULTIPROCESSOR 165#ifdef MULTIPROCESSOR
166static int octeon_send_ipi(struct cpu_info *, int); 166static int octeon_send_ipi(struct cpu_info *, int);
167static int octeon_ipi_intr(void *); 167static int octeon_ipi_intr(void *);
168 168
169static struct octeon_intrhand ipi_intrhands[1] = { 169static struct octeon_intrhand ipi_intrhands[2] = {
170 [0] = { 170 [0] = {
171 .ih_func = octeon_ipi_intr, 171 .ih_func = octeon_ipi_intr,
172 .ih_arg = (void *)(uintptr_t)__BITS(15,0), 172 .ih_arg = (void *)(uintptr_t)__BITS(15,0),
173 .ih_irq = CIU_INT_MBOX_15_0, 173 .ih_irq = CIU_INT_MBOX_15_0,
174 .ih_ipl = IPL_HIGH, 174 .ih_ipl = IPL_HIGH,
175 }, 175 },
176 [1] = { 176 [1] = {
177 .ih_func = octeon_ipi_intr, 177 .ih_func = octeon_ipi_intr,
178 .ih_arg = (void *)(uintptr_t)__BITS(31,16), 178 .ih_arg = (void *)(uintptr_t)__BITS(31,16),
179 .ih_irq = CIU_INT_MBOX_31_16, 179 .ih_irq = CIU_INT_MBOX_31_16,
180 .ih_ipl = IPL_SCHED, 180 .ih_ipl = IPL_SCHED,
181 }, 181 },
182}; 182};