Wed Aug 26 18:06:54 2020 UTC ()
Pull up following revision(s) (requested by tsutsui in ticket #1060):

	sys/arch/sun3/sun3x/pmap.c: revision 1.117

Make sure pmap_kenter_pa(9) handles uncached mappings properly.

Fixes "cgfour(4) is mis-probed as bwtwo(4)" problem on 3/80
that has been broken since NetBSD 1.6.

Now Xorg 1.20 based Xsun 8bpp color server is confirmed working
on the cgfour(4).

Should be pulled up to netbsd-9.

XXX: all MD PMAP_NC flags should be replaced with MI PMAP_NOCACHE flag.


(martin)
diff -r1.114 -r1.114.20.1 src/sys/arch/sun3/sun3x/pmap.c
cvs diff -r1.114 -r1.114.20.1 src/sys/arch/sun3/sun3x/pmap.c (expand / switch to unified diff)

--- src/sys/arch/sun3/sun3x/pmap.c 2016/12/22 14:47:59 1.114
+++ src/sys/arch/sun3/sun3x/pmap.c 2020/08/26 18:06:54 1.114.20.1
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: pmap.c,v 1.114 2016/12/22 14:47:59 cherry Exp $ */ 1/* $NetBSD: pmap.c,v 1.114.20.1 2020/08/26 18:06:54 martin Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. 4 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jeremy Cooper. 8 * by Jeremy Cooper.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -95,27 +95,27 @@ @@ -95,27 +95,27 @@
95 * affected by the change. These instances are documented in the code at 95 * affected by the change. These instances are documented in the code at
96 * various points. 96 * various points.
97 */ 97 */
98/*** A Note About the Note About the 68851 Address Translation Cache 98/*** A Note About the Note About the 68851 Address Translation Cache
99 * 4 months into this code I discovered that the sun3x does not have 99 * 4 months into this code I discovered that the sun3x does not have
100 * a MC68851 chip. Instead, it has a version of this MMU that is part of the 100 * a MC68851 chip. Instead, it has a version of this MMU that is part of the
101 * the 68030 CPU. 101 * the 68030 CPU.
102 * All though it behaves very similarly to the 68851, it only has 1 task 102 * All though it behaves very similarly to the 68851, it only has 1 task
103 * alias and a 22 entry cache. So sadly (or happily), the first paragraph 103 * alias and a 22 entry cache. So sadly (or happily), the first paragraph
104 * of the previous note does not apply to the sun3x pmap. 104 * of the previous note does not apply to the sun3x pmap.
105 */ 105 */
106 106
107#include <sys/cdefs.h> 107#include <sys/cdefs.h>
108__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.114 2016/12/22 14:47:59 cherry Exp $"); 108__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.114.20.1 2020/08/26 18:06:54 martin Exp $");
109 109
110#include "opt_ddb.h" 110#include "opt_ddb.h"
111#include "opt_pmap_debug.h" 111#include "opt_pmap_debug.h"
112 112
113#include <sys/param.h> 113#include <sys/param.h>
114#include <sys/systm.h> 114#include <sys/systm.h>
115#include <sys/proc.h> 115#include <sys/proc.h>
116#include <sys/malloc.h> 116#include <sys/malloc.h>
117#include <sys/pool.h> 117#include <sys/pool.h>
118#include <sys/queue.h> 118#include <sys/queue.h>
119#include <sys/kcore.h> 119#include <sys/kcore.h>
120#include <sys/atomic.h> 120#include <sys/atomic.h>
121 121
@@ -2135,34 +2135,42 @@ pmap_enter_kernel(vaddr_t va, paddr_t pa @@ -2135,34 +2135,42 @@ pmap_enter_kernel(vaddr_t va, paddr_t pa
2135 * Insert the PTE into the PV system, if need be. 2135 * Insert the PTE into the PV system, if need be.
2136 */ 2136 */
2137 if (insert) { 2137 if (insert) {
2138 pv = pa2pv(pa); 2138 pv = pa2pv(pa);
2139 pvebase[pte_idx].pve_next = pv->pv_idx; 2139 pvebase[pte_idx].pve_next = pv->pv_idx;
2140 pv->pv_idx = pte_idx; 2140 pv->pv_idx = pte_idx;
2141 } 2141 }
2142} 2142}
2143 2143
2144void 2144void
2145pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2145pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
2146{ 2146{
2147 mmu_short_pte_t *pte; 2147 mmu_short_pte_t *pte;
 2148 u_int mapflags;
 2149
 2150 /* XXX: MD PMAP_NC should be replaced by MI PMAP_NOCACHE in flags. */
 2151 mapflags = (pa & ~MMU_PAGE_MASK);
 2152 if ((mapflags & PMAP_NC) != 0)
 2153 flags |= PMAP_NOCACHE;
2148 2154
2149 /* This array is traditionally named "Sysmap" */ 2155 /* This array is traditionally named "Sysmap" */
2150 pte = &kernCbase[(u_long)m68k_btop(va - KERNBASE3X)]; 2156 pte = &kernCbase[(u_long)m68k_btop(va - KERNBASE3X)];
2151 2157
2152 KASSERT(!MMU_VALID_DT(*pte)); 2158 KASSERT(!MMU_VALID_DT(*pte));
2153 pte->attr.raw = MMU_DT_INVALID | MMU_DT_PAGE | (pa & MMU_PAGE_MASK); 2159 pte->attr.raw = MMU_DT_INVALID | MMU_DT_PAGE | (pa & MMU_PAGE_MASK);
2154 if (!(prot & VM_PROT_WRITE)) 2160 if (!(prot & VM_PROT_WRITE))
2155 pte->attr.raw |= MMU_SHORT_PTE_WP; 2161 pte->attr.raw |= MMU_SHORT_PTE_WP;
 2162 if ((flags & PMAP_NOCACHE) != 0)
 2163 pte->attr.raw |= MMU_SHORT_PTE_CI;
2156} 2164}
2157 2165
2158void 2166void
2159pmap_kremove(vaddr_t va, vsize_t len) 2167pmap_kremove(vaddr_t va, vsize_t len)
2160{ 2168{
2161 int idx, eidx; 2169 int idx, eidx;
2162 2170
2163#ifdef PMAP_DEBUG 2171#ifdef PMAP_DEBUG
2164 if ((va & PGOFSET) || (len & PGOFSET)) 2172 if ((va & PGOFSET) || (len & PGOFSET))
2165 panic("pmap_kremove: alignment"); 2173 panic("pmap_kremove: alignment");
2166#endif 2174#endif
2167 2175
2168 idx = m68k_btop(va - KERNBASE3X); 2176 idx = m68k_btop(va - KERNBASE3X);