 @@ -1,14 +1,14 @@
-/* $NetBSD: fp_complete.c,v 1.23 2019/03/25 19:24:30 maxv Exp $ */
+/* $NetBSD: fp_complete.c,v 1.23.4.1 2020/09/02 12:38:07 martin Exp $ */
 /*-
  * Copyright (c) 2001 Ross Harvey
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -25,27 +25,27 @@
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: fp_complete.c,v 1.23 2019/03/25 19:24:30 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fp_complete.c,v 1.23.4.1 2020/09/02 12:38:07 martin Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/proc.h>
 #include <sys/atomic.h>
 #include <sys/evcnt.h>
 #include <machine/cpu.h>
 #include <machine/fpu.h>
 #include <machine/reg.h>
 #include <machine/alpha.h>
 #include <alpha/alpha/db_instruction.h>
 @@ -189,33 +189,33 @@ lds(unsigned int rn, s_float *v, struct
 	alpha_lds(rn, v);
+}
 static inline void
 ldt(unsigned int rn, t_float *v, struct lwp *l)
+{
 	POSTFILTER_SUBNORMAL(l, v);
 	alpha_ldt(rn, v);
+}
 static float64
 compare_lt(float64 a, float64 b)
+{
-	return CMP_RESULT(float64_lt(a, b));
+	return CMP_RESULT(float64_lt_quiet(a, b));
+}
 static float64
 compare_le(float64 a, float64 b)
+{
-	return CMP_RESULT(float64_le(a, b));
+	return CMP_RESULT(float64_le_quiet(a, b));
+}
 static float64
 compare_un(float64 a, float64 b)
+{
 	if (float64_is_nan(a) | float64_is_nan(b)) {
 		if (float64_is_signaling_nan(a) | float64_is_signaling_nan(b))
 			float_set_invalid();
 		return CMP_RESULT(1);
+	}
 	return CMP_RESULT(0);
+}
 @@ -492,27 +492,27 @@ float64_unk(float64 a, float64 b)
  *			 1  1  1  0 . . . cvtXt/g (cvtqt, cvt[dq]g only)
  *			 1  1  1  1 . . . cvtXq/q (cvttq, cvtgq)
  *	   |	       |
  * 15 14 13|12 11 10 09|08 07 06 05	  the twilight zone
  * --------======------============
  *  TRAP   : RND : SRC : FUNCTION  :
  * /s /i /u  x  x  1  0  1  1  0  0 . . . cvtts, /siu only 0, 1, 5, 7
  *  0  1  0  1  0  1  0  1  1  0  0 . . . cvtst   (src == T (!)) 2ac NOT /S
  *  1  1  0  1  0  1  0  1  1  0  0 . . . cvtst/s (src == T (!)) 6ac
  *  x  0  x  x  x  x  0	 1  1  1  1 . . . cvttq/_ (src == T)
  */
 static void
-alpha_fp_interpret(alpha_instruction *pc, struct lwp *l, uint64_t bits)
+alpha_fp_interpret(alpha_instruction *pc, struct lwp *l, uint32_t bits)
+{
 	s_float sfa, sfb, sfc;
 	t_float tfa, tfb, tfc;
 	alpha_instruction inst;
 	inst.bits = bits;
 	switch(inst.generic_format.opcode) {
 	default:
 		/* this "cannot happen" */
 		this_cannot_happen(2, inst.bits);
 		return;
 	case op_any_float:
 		if (inst.float_format.function == op_cvtql_sv ||
 @@ -624,33 +624,35 @@ alpha_fp_complete(u_long a0, u_long a1,
+{
 	int t;
 	int sig;
 	uint64_t op_class;
 	alpha_instruction inst;
 	/* "trigger_pc" is Compaq's term for the earliest faulting op */
 	alpha_instruction *trigger_pc, *usertrap_pc;
 	alpha_instruction *pc, *win_begin, tsw[TSWINSIZE];
 	sig = SIGFPE;
 	pc = (alpha_instruction *)l->l_md.md_tf->tf_regs[FRAME_PC];
 	trigger_pc = pc - 1;	/* for ALPHA_AMASK_PAT case */
 	if (cpu_amask & ALPHA_AMASK_PAT) {
-		if (a0 & 1 || alpha_fp_sync_complete) {
+		/* SWC | INV */
 		if (a0 & 3 || alpha_fp_sync_complete) {
 			sig = alpha_fp_complete_at(trigger_pc, l, ucode);
 			goto done;
+		}
+	}
 	*ucode = a0;
-	if (!(a0 & 1))
+	/* SWC | INV */
 	if (!(a0 & 3))
 		return sig;
 /*
  * At this point we are somewhere in the trap shadow of one or more instruc-
  * tions that have trapped with software completion specified.  We have a mask
  * of the registers written by trapping instructions.
+ *
  * Now step backwards through the trap shadow, clearing bits in the
  * destination write mask until the trigger instruction is found, and
  * interpret this one instruction in SW. If a SIGFPE is not required, back up
  * the PC until just after this instruction and restart. This will execute all
  * trap shadow instructions between the trigger pc and the trap pc twice.
  */
 	trigger_pc = 0;