 @@ -1,1158 +1,1163 @@
-/* $NetBSD: locore.s,v 1.125 2020/06/30 16:20:00 maxv Exp $ */
+/* $NetBSD: locore.s,v 1.126 2020/09/03 02:09:09 thorpej Exp $ */
 /*-
  * Copyright (c) 1999, 2000, 2019 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
  * NASA Ames Research Center.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
  * All rights reserved.
+ *
  * Author: Chris G. Demetriou
+ *
  * Permission to use, copy, modify and distribute this software and
  * its documentation is hereby granted, provided that both the copyright
  * notice and this permission notice appear in all copies of the
  * software, derivative works or modified versions, and any portions
  * thereof, and that both notices appear in supporting documentation.
+ *
  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
  * Carnegie Mellon requests users of this software to return to
+ *
  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  *  School of Computer Science
  *  Carnegie Mellon University
  *  Pittsburgh PA 15213-3890
+ *
  * any improvements or extensions that they make and grant Carnegie the
  * rights to redistribute these changes.
  */
 .stabs	__FILE__,100,0,0,kernel_text
 #include "opt_ddb.h"
 #include "opt_kgdb.h"
 #include "opt_multiprocessor.h"
 #include "opt_lockdebug.h"
 #include "opt_compat_netbsd.h"
 #include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: locore.s,v 1.125 2020/06/30 16:20:00 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: locore.s,v 1.126 2020/09/03 02:09:09 thorpej Exp $");
 #include "assym.h"
 .stabs	__FILE__,132,0,0,kernel_text
 /*
  * Perform actions necessary to switch to a new context.  The
  * hwpcb should be in a0.  Clobbers v0, t0, t8..t11, a0.
  */
 #define	SWITCH_CONTEXT							\
 	/* Make a note of the context we're running on. */		\
 	GET_CURPCB						;	\
 	stq	a0, 0(v0)					;	\
+									\
 	/* Swap in the new context. */					\
 	call_pal PAL_OSF1_swpctx
 	/* don't reorder instructions; paranoia. */
 	.set noreorder
 	.text
 	.macro	bfalse	reg, dst
 	beq	\reg, \dst
 	.endm
 	.macro	btrue	reg, dst
 	bne	\reg, \dst
 	.endm
 /*
  * This is for kvm_mkdb, and should be the address of the beginning
  * of the kernel text segment (not necessarily the same as kernbase).
  */
 	EXPORT(kernel_text)
 .loc	1 __LINE__
 kernel_text:
 /*
  * bootstack: a temporary stack, for booting.
+ *
  * Extends from 'start' down.
  */
 bootstack:
 /*
  * locorestart: Kernel start. This is no longer the actual entry
  * point, although jumping to here (the first kernel address) will
  * in fact work just fine.
+ *
  * Arguments:
  *	a0 is the first free page frame number (PFN)
  *	a1 is the page table base register (PTBR)
  *	a2 is the bootinfo magic number
  *	a3 is the pointer to the bootinfo structure
+ *
  * All arguments are passed to alpha_init().
  */
 IMPORT(prom_mapped, 4)
 NESTED_NOPROFILE(locorestart,1,0,ra,0,0)
 	br	pv,1f
 :	LDGP(pv)
 	/* Switch to the boot stack. */
 	lda	sp,bootstack
 	/* Load KGP with current GP. */
 	mov	a0, s0			/* save pfn */
 	mov	gp, a0
 	call_pal PAL_OSF1_wrkgp		/* clobbers a0, t0, t8-t11 */
 	mov	s0, a0			/* restore pfn */
 	/*
 	 * Call alpha_init() to do pre-main initialization.
 	 * alpha_init() gets the arguments we were called with,
 	 * which are already in a0, a1, a2, a3, and a4.
 	 */
 	CALL(alpha_init)
 	/* Set up the virtual page table pointer. */
 	ldiq	a0, VPTBASE
 	call_pal PAL_OSF1_wrvptptr	/* clobbers a0, t0, t8-t11 */
 	/*
 	 * Switch to lwp0's PCB.
 	 */
 	lda	a0, lwp0
 	ldq	a0, L_MD_PCBPADDR(a0)		/* phys addr of PCB */
 	SWITCH_CONTEXT
 	/* PROM is no longer mapped. */
 	lda	t0, prom_mapped
 	stl	zero, 0(t0)
 	/*
 	 * We've switched to a new page table base, so invalidate the TLB
 	 * and I-stream.  This happens automatically everywhere but here.
 	 */
 	ldiq	a0, -2				/* TBIA */
 	call_pal PAL_OSF1_tbi
 	call_pal PAL_imb
 	/*
 	 * All ready to go!  Call main()!
 	 */
 	CALL(main)
 	/* This should never happen. */
 	PANIC("main() returned",Lmain_returned_pmsg)
 	END(locorestart)
 /**************************************************************************/
 /*
  * Pull in the PROM interface routines; these are needed for
  * prom printf (while bootstrapping), and for determining the
  * boot device, etc.
  */
 #include <alpha/alpha/prom_disp.s>
 /**************************************************************************/
 /*
  * Pull in the PALcode function stubs.
  */
 #include <alpha/alpha/pal.s>
 /**************************************************************************/
 /**************************************************************************/
 #if defined(MULTIPROCESSOR)
 /*
  * Pull in the multiprocssor glue.
  */
 #include <alpha/alpha/multiproc.s>
 #endif /* MULTIPROCESSOR */
 /**************************************************************************/
 /**************************************************************************/
 #if defined(DDB) || defined(KGDB)
 /*
  * Pull in debugger glue.
  */
 #include <alpha/alpha/debug.s>
 #endif /* DDB || KGDB */
 /**************************************************************************/
 /**************************************************************************/
 	.text
 .stabs	__FILE__,132,0,0,backtolocore1	/* done with includes */
 .loc	1 __LINE__
 backtolocore1:
 /**************************************************************************/
 #ifdef COMPAT_16
 /*
  * Signal "trampoline" code.
+ *
  * The kernel arranges for the handler to be invoked directly.  This
  * trampoline is used only to return from the signal.
+ *
  * The stack pointer points to the saved sigcontext.
  */
 NESTED_NOPROFILE(sigcode,0,0,ra,0,0)
 	mov	sp, a0			/* get pointer to sigcontext */
 	CALLSYS_NOERROR(compat_16___sigreturn14)	/* and call sigreturn() with it. */
 	mov	v0, a0			/* if that failed, get error code */
 	CALLSYS_NOERROR(exit)		/* and call exit() with it. */
 XNESTED(esigcode,0)
 	END(sigcode)
 #endif /* COMPAT_16 */
 /**************************************************************************/
 /*
  * exception_return: return from trap, exception, or syscall
  */
 IMPORT(ssir, 8)
 LEAF(exception_return, 1)			/* XXX should be NESTED */
 	br	pv, 1f
 :	LDGP(pv)
 	ldq	s1, (FRAME_PS * 8)(sp)		/* get the saved PS */
 	and	s1, ALPHA_PSL_IPL_MASK, t0	/* look at the saved IPL */
 	bne	t0, 5f				/* != 0: can't do AST or SIR */
 	/* see if we can do an SIR */
 :	ldq	t1, ssir			/* SIR pending? */
 	bne	t1, 6f				/* yes */
 	/* no */
 	and	s1, ALPHA_PSL_USERMODE, t0	/* are we returning to user? */
 	beq	t0, 5f				/* no: just return */
 	/* yes */
 	/* GET_CPUINFO clobbers v0, t0, t8...t11. */
 :	GET_CPUINFO
 	/* check for AST */
 	ldq	t1, CPU_INFO_CURLWP(v0)
 	ldl	t3, L_MD_ASTPENDING(t1)		/* AST pending? */
 	bne	t3, 7f				/* yes */
 	/* no: headed back to user space */
 	/* Enable the FPU based on whether MDLWP_FPACTIVE is set. */
 :	ldq	t2, L_MD_FLAGS(t1)
 	cmplt	t2, zero, a0
 	call_pal PAL_OSF1_wrfen
 	/* restore the registers, and return */
 :	bsr	ra, exception_restore_regs	/* jmp/CALL trashes pv/t12 */
 	ldq	ra,(FRAME_RA*8)(sp)
 	.set noat
 	ldq	at_reg,(FRAME_AT*8)(sp)
 	lda	sp,(FRAME_SW_SIZE*8)(sp)
 	call_pal PAL_OSF1_rti
 	.set at
 	/* NOTREACHED */
 	/* We've got a SIR */
 :	ldiq	a0, ALPHA_PSL_IPL_SOFT
 	call_pal PAL_OSF1_swpipl
 	mov	v0, s2				/* remember old IPL */
 	CALL(softintr_dispatch)
 	/* SIR handled; restore IPL and check again */
 	mov	s2, a0
 	call_pal PAL_OSF1_swpipl
 	br	2b
 	/* We've got an AST */
 :	stl	zero, L_MD_ASTPENDING(t1)	/* no AST pending */
 	ldiq	a0, ALPHA_PSL_IPL_0		/* drop IPL to zero */
 	call_pal PAL_OSF1_swpipl
 	mov	v0, s2				/* remember old IPL */
 	mov	sp, a0				/* only arg is frame */
 	CALL(ast)
 	/* AST handled; restore IPL and check again */
 	mov	s2, a0
 	call_pal PAL_OSF1_swpipl
 	br	3b
 	END(exception_return)
 LEAF(exception_save_regs, 0)
 	stq	v0,(FRAME_V0*8)(sp)
 	stq	a3,(FRAME_A3*8)(sp)
 	stq	a4,(FRAME_A4*8)(sp)
 	stq	a5,(FRAME_A5*8)(sp)
 	stq	s0,(FRAME_S0*8)(sp)
 	stq	s1,(FRAME_S1*8)(sp)
 	stq	s2,(FRAME_S2*8)(sp)
 	stq	s3,(FRAME_S3*8)(sp)
 	stq	s4,(FRAME_S4*8)(sp)
 	stq	s5,(FRAME_S5*8)(sp)
 	stq	s6,(FRAME_S6*8)(sp)
 	stq	t0,(FRAME_T0*8)(sp)
 	stq	t1,(FRAME_T1*8)(sp)
 	stq	t2,(FRAME_T2*8)(sp)
 	stq	t3,(FRAME_T3*8)(sp)
 	stq	t4,(FRAME_T4*8)(sp)
 	stq	t5,(FRAME_T5*8)(sp)
 	stq	t6,(FRAME_T6*8)(sp)
 	stq	t7,(FRAME_T7*8)(sp)
 	stq	t8,(FRAME_T8*8)(sp)
 	stq	t9,(FRAME_T9*8)(sp)
 	stq	t10,(FRAME_T10*8)(sp)
 	stq	t11,(FRAME_T11*8)(sp)
 	stq	t12,(FRAME_T12*8)(sp)
 	RET
 	END(exception_save_regs)
 LEAF(exception_restore_regs, 0)
 	ldq	v0,(FRAME_V0*8)(sp)
 	ldq	a3,(FRAME_A3*8)(sp)
 	ldq	a4,(FRAME_A4*8)(sp)
 	ldq	a5,(FRAME_A5*8)(sp)
 	ldq	s0,(FRAME_S0*8)(sp)
 	ldq	s1,(FRAME_S1*8)(sp)
 	ldq	s2,(FRAME_S2*8)(sp)
 	ldq	s3,(FRAME_S3*8)(sp)
 	ldq	s4,(FRAME_S4*8)(sp)
 	ldq	s5,(FRAME_S5*8)(sp)
 	ldq	s6,(FRAME_S6*8)(sp)
 	ldq	t0,(FRAME_T0*8)(sp)
 	ldq	t1,(FRAME_T1*8)(sp)
 	ldq	t2,(FRAME_T2*8)(sp)
 	ldq	t3,(FRAME_T3*8)(sp)
 	ldq	t4,(FRAME_T4*8)(sp)
 	ldq	t5,(FRAME_T5*8)(sp)
 	ldq	t6,(FRAME_T6*8)(sp)
 	ldq	t7,(FRAME_T7*8)(sp)
 	ldq	t8,(FRAME_T8*8)(sp)
 	ldq	t9,(FRAME_T9*8)(sp)
 	ldq	t10,(FRAME_T10*8)(sp)
 	ldq	t11,(FRAME_T11*8)(sp)
 	ldq	t12,(FRAME_T12*8)(sp)
 	RET
 	END(exception_restore_regs)
 /**************************************************************************/
 /*
  * XentArith:
  * System arithmetic trap entry point.
  */
 	PALVECT(XentArith)		/* setup frame, save registers */
 	/* a0, a1, & a2 already set up */
 	ldiq	a3, ALPHA_KENTRY_ARITH
 	mov	sp, a4			; .loc 1 __LINE__
 	CALL(trap)
 	jmp	zero, exception_return
 	END(XentArith)
 /**************************************************************************/
 /*
  * XentIF:
  * System instruction fault trap entry point.
  */
 	PALVECT(XentIF)			/* setup frame, save registers */
 	/* a0, a1, & a2 already set up */
 	ldiq	a3, ALPHA_KENTRY_IF
 	mov	sp, a4			; .loc 1 __LINE__
 	CALL(trap)
 	jmp	zero, exception_return
 	END(XentIF)
 /**************************************************************************/
 /*
  * XentInt:
  * System interrupt entry point.
  */
 	PALVECT(XentInt)		/* setup frame, save registers */
 	/* a0, a1, & a2 already set up */
 	mov	sp, a3			; .loc 1 __LINE__
 	CALL(interrupt)
 	jmp	zero, exception_return
 	END(XentInt)
 /**************************************************************************/
 /*
  * XentMM:
  * System memory management fault entry point.
  */
 	PALVECT(XentMM)			/* setup frame, save registers */
 	/* a0, a1, & a2 already set up */
 	ldiq	a3, ALPHA_KENTRY_MM
 	mov	sp, a4			; .loc 1 __LINE__
 	CALL(trap)
 	jmp	zero, exception_return
 	END(XentMM)
 /**************************************************************************/
 /*
  * XentSys:
  * System call entry point.
  */
 	ESETUP(XentSys)			; .loc 1 __LINE__
 	stq	v0,(FRAME_V0*8)(sp)		/* in case we need to restart */
 	stq	s0,(FRAME_S0*8)(sp)
 	stq	s1,(FRAME_S1*8)(sp)
 	stq	s2,(FRAME_S2*8)(sp)
 	stq	s3,(FRAME_S3*8)(sp)
 	stq	s4,(FRAME_S4*8)(sp)
 	stq	s5,(FRAME_S5*8)(sp)
 	stq	s6,(FRAME_S6*8)(sp)
 	stq	a0,(FRAME_A0*8)(sp)
 	stq	a1,(FRAME_A1*8)(sp)
 	stq	a2,(FRAME_A2*8)(sp)
 	stq	a3,(FRAME_A3*8)(sp)
 	stq	a4,(FRAME_A4*8)(sp)
 	stq	a5,(FRAME_A5*8)(sp)
 	stq	ra,(FRAME_RA*8)(sp)
 	/* syscall number, passed in v0, is first arg, frame pointer second */
 	mov	v0,a1
 	GET_CURLWP
 	ldq	a0,0(v0)
 	mov	sp,a2			; .loc 1 __LINE__
 	ldq	t11,L_PROC(a0)
 	ldq	t12,P_MD_SYSCALL(t11)
 	CALL((t12))
 	jmp	zero, exception_return
 	END(XentSys)
 /**************************************************************************/
 /*
  * XentUna:
  * System unaligned access entry point.
  */
 LEAF(XentUna, 3)				/* XXX should be NESTED */
 	.set noat
 	lda	sp,-(FRAME_SW_SIZE*8)(sp)
 	stq	at_reg,(FRAME_AT*8)(sp)
 	.set at
 	stq	ra,(FRAME_RA*8)(sp)
 	bsr	ra, exception_save_regs		/* jmp/CALL trashes pv/t12 */
 	/* a0, a1, & a2 already set up */
 	ldiq	a3, ALPHA_KENTRY_UNA
 	mov	sp, a4			; .loc 1 __LINE__
 	CALL(trap)
 	jmp	zero, exception_return
 	END(XentUna)
 /**************************************************************************/
 /*
  * savefpstate: Save a process's floating point state.
+ *
  * Arguments:
  *	a0	'struct fpstate *' to save into
  */
 LEAF(savefpstate, 1)
 	LDGP(pv)
 	/* save all of the FP registers */
 	lda	t1, FPREG_FPR_REGS(a0)	/* get address of FP reg. save area */
 	stt	$f0,   (0 * 8)(t1)	/* save first register, using hw name */
 	stt	$f1,   (1 * 8)(t1)	/* etc. */
 	stt	$f2,   (2 * 8)(t1)
 	stt	$f3,   (3 * 8)(t1)
 	stt	$f4,   (4 * 8)(t1)
 	stt	$f5,   (5 * 8)(t1)
 	stt	$f6,   (6 * 8)(t1)
 	stt	$f7,   (7 * 8)(t1)
 	stt	$f8,   (8 * 8)(t1)
 	stt	$f9,   (9 * 8)(t1)
 	stt	$f10, (10 * 8)(t1)
 	stt	$f11, (11 * 8)(t1)
 	stt	$f12, (12 * 8)(t1)
 	stt	$f13, (13 * 8)(t1)
 	stt	$f14, (14 * 8)(t1)
 	stt	$f15, (15 * 8)(t1)
 	stt	$f16, (16 * 8)(t1)
 	stt	$f17, (17 * 8)(t1)
 	stt	$f18, (18 * 8)(t1)
 	stt	$f19, (19 * 8)(t1)
 	stt	$f20, (20 * 8)(t1)
 	stt	$f21, (21 * 8)(t1)
 	stt	$f22, (22 * 8)(t1)
 	stt	$f23, (23 * 8)(t1)
 	stt	$f24, (24 * 8)(t1)
 	stt	$f25, (25 * 8)(t1)
 	stt	$f26, (26 * 8)(t1)
 	stt	$f27, (27 * 8)(t1)
 	.set noat
 	stt	$f28, (28 * 8)(t1)
 	.set at
 	stt	$f29, (29 * 8)(t1)
 	stt	$f30, (30 * 8)(t1)
 	/*
 	 * Then save the FPCR; note that the necessary 'trapb's are taken
 	 * care of on kernel entry and exit.
 	 */
 	mf_fpcr	ft0
 	stt	ft0, FPREG_FPR_CR(a0)	/* store to FPCR save area */
 	RET
 	END(savefpstate)
 /**************************************************************************/
 /*
  * restorefpstate: Restore a process's floating point state.
+ *
  * Arguments:
  *	a0	'struct fpstate *' to restore from
  */
 LEAF(restorefpstate, 1)
 	LDGP(pv)
 	/*
 	 * Restore the FPCR; note that the necessary 'trapb's are taken care of
 	 * on kernel entry and exit.
 	 */
 	ldt	ft0, FPREG_FPR_CR(a0)	/* load from FPCR save area */
 	mt_fpcr	ft0
 	/* Restore all of the FP registers. */
 	lda	t1, FPREG_FPR_REGS(a0)	/* get address of FP reg. save area */
 	ldt	$f0,   (0 * 8)(t1)	/* restore first reg., using hw name */
 	ldt	$f1,   (1 * 8)(t1)	/* etc. */
 	ldt	$f2,   (2 * 8)(t1)
 	ldt	$f3,   (3 * 8)(t1)
 	ldt	$f4,   (4 * 8)(t1)
 	ldt	$f5,   (5 * 8)(t1)
 	ldt	$f6,   (6 * 8)(t1)
 	ldt	$f7,   (7 * 8)(t1)
 	ldt	$f8,   (8 * 8)(t1)
 	ldt	$f9,   (9 * 8)(t1)
 	ldt	$f10, (10 * 8)(t1)
 	ldt	$f11, (11 * 8)(t1)
 	ldt	$f12, (12 * 8)(t1)
 	ldt	$f13, (13 * 8)(t1)
 	ldt	$f14, (14 * 8)(t1)
 	ldt	$f15, (15 * 8)(t1)
 	ldt	$f16, (16 * 8)(t1)
 	ldt	$f17, (17 * 8)(t1)
 	ldt	$f18, (18 * 8)(t1)
 	ldt	$f19, (19 * 8)(t1)
 	ldt	$f20, (20 * 8)(t1)
 	ldt	$f21, (21 * 8)(t1)
 	ldt	$f22, (22 * 8)(t1)
 	ldt	$f23, (23 * 8)(t1)
 	ldt	$f24, (24 * 8)(t1)
 	ldt	$f25, (25 * 8)(t1)
 	ldt	$f26, (26 * 8)(t1)
 	ldt	$f27, (27 * 8)(t1)
 	ldt	$f28, (28 * 8)(t1)
 	ldt	$f29, (29 * 8)(t1)
 	ldt	$f30, (30 * 8)(t1)
 	RET
 	END(restorefpstate)
 /**************************************************************************/
 /*
  * savectx: save process context, i.e. callee-saved registers
+ *
  * Note that savectx() only works for processes other than curlwp,
  * since cpu_switchto will copy over the info saved here.  (It _can_
  * sanely be used for curlwp iff cpu_switchto won't be called again, e.g.
  * if called from boot().)
+ *
  * Arguments:
  *	a0	'struct pcb *' of the process that needs its context saved
+ *
  * Return:
  *	v0	0.  (note that for child processes, it seems
  *		like savectx() returns 1, because the return address
  *		in the PCB is set to the return address from savectx().)
  */
 LEAF(savectx, 1)
 	br	pv, 1f
 :	LDGP(pv)
 	stq	sp, PCB_HWPCB_KSP(a0)		/* store sp */
 	stq	s0, PCB_CONTEXT+(0 * 8)(a0)	/* store s0 - s6 */
 	stq	s1, PCB_CONTEXT+(1 * 8)(a0)
 	stq	s2, PCB_CONTEXT+(2 * 8)(a0)
 	stq	s3, PCB_CONTEXT+(3 * 8)(a0)
 	stq	s4, PCB_CONTEXT+(4 * 8)(a0)
 	stq	s5, PCB_CONTEXT+(5 * 8)(a0)
 	stq	s6, PCB_CONTEXT+(6 * 8)(a0)
 	stq	ra, PCB_CONTEXT+(7 * 8)(a0)	/* store ra */
 	call_pal PAL_OSF1_rdps			/* NOTE: doesn't kill a0 */
 	stq	v0, PCB_CONTEXT+(8 * 8)(a0)	/* store ps, for ipl */
 	mov	zero, v0
 	RET
 	END(savectx)
 /**************************************************************************/
 /*
  * struct lwp *cpu_switchto(struct lwp *current, struct lwp *next)
  * Switch to the specified next LWP
  * Arguments:
  *	a0	'struct lwp *' of the LWP to switch from
  *	a1	'struct lwp *' of the LWP to switch to
  */
 LEAF(cpu_switchto, 0)
 	LDGP(pv)
 	/*
 	 * do an inline savectx(), to save old context
 	 */
 	ldq	a2, L_PCB(a0)
 	/* NOTE: ksp is stored by the swpctx */
 	stq	s0, PCB_CONTEXT+(0 * 8)(a2)	/* store s0 - s6 */
 	stq	s1, PCB_CONTEXT+(1 * 8)(a2)
 	stq	s2, PCB_CONTEXT+(2 * 8)(a2)
 	stq	s3, PCB_CONTEXT+(3 * 8)(a2)
 	stq	s4, PCB_CONTEXT+(4 * 8)(a2)
 	stq	s5, PCB_CONTEXT+(5 * 8)(a2)
 	stq	s6, PCB_CONTEXT+(6 * 8)(a2)
 	stq	ra, PCB_CONTEXT+(7 * 8)(a2)	/* store ra */
 	mov	a0, s4				/* save old curlwp */
 	mov	a1, s2				/* save new lwp */
 	ldq	a0, L_MD_PCBPADDR(s2)		/* save new pcbpaddr */
 	SWITCH_CONTEXT				/* swap the context */
 	GET_CPUINFO
 	stq	s2, CPU_INFO_CURLWP(v0)		/* curlwp = l */
 	/*
 	 * Now running on the new PCB.
 	 */
 	ldq	s0, L_PCB(s2)
 	/*
 	 * Check for restartable atomic sequences (RAS).
 	 */
 	ldq	a0, L_PROC(s2)			/* first ras_lookup() arg */
 	ldq	t0, P_RASLIST(a0)		/* any RAS entries? */
 	beq	t0, 1f				/* no, skip */
 	ldq	s1, L_MD_TF(s2)			/* s1 = l->l_md.md_tf */
 	ldq	a1, (FRAME_PC*8)(s1)		/* second ras_lookup() arg */
 	CALL(ras_lookup)			/* ras_lookup(p, PC) */
 	addq	v0, 1, t0			/* -1 means "not in ras" */
 	beq	t0, 1f
 	stq	v0, (FRAME_PC*8)(s1)
 :
 	mov	s4, v0				/* return the old lwp */
 	/*
 	 * Restore registers and return.
 	 * NOTE: ksp is restored by the swpctx.
 	 */
 	ldq	s1, PCB_CONTEXT+(1 * 8)(s0)		/* restore s1-s6 */
 	ldq	s2, PCB_CONTEXT+(2 * 8)(s0)
 	ldq	s3, PCB_CONTEXT+(3 * 8)(s0)
 	ldq	s4, PCB_CONTEXT+(4 * 8)(s0)
 	ldq	s5, PCB_CONTEXT+(5 * 8)(s0)
 	ldq	s6, PCB_CONTEXT+(6 * 8)(s0)
 	ldq	ra, PCB_CONTEXT+(7 * 8)(s0)		/* restore ra */
 	ldq	s0, PCB_CONTEXT+(0 * 8)(s0)		/* restore s0 */
 	RET
 	END(cpu_switchto)
 /*
  * lwp_trampoline()
+ *
  * Arrange for a function to be invoked neatly, after a cpu_lwp_fork().
+ *
  * Invokes the function specified by the s0 register with the return
  * address specified by the s1 register and with one argument specified
  * by the s2 register.
  */
 LEAF_NOPROFILE(lwp_trampoline, 0)
 	mov	v0, a0
 	mov	s3, a1
 	CALL(lwp_startup)
 	mov	s0, pv
 	mov	s1, ra
 	mov	s2, a0
 	jmp	zero, (pv)
 	END(lwp_trampoline)
 /**************************************************************************/
 /*
  * XXX XXX XXX: Should be removed?
  */
 LEAF(alpha_copystr, 4)
 	LDGP(pv)
 	mov	a2, t0			/* t0 = i = len */
 	bne	a2, 1f			/* if (len != 0), proceed */
 	ldiq	t1, 1			/* else bail */
 	br	zero, 2f
 :	ldq_u	t1, 0(a0)		/* t1 = *from */
 	extbl	t1, a0, t1
 	ldq_u	t3, 0(a1)		/* set up t2 with quad around *to */
 	insbl	t1, a1, t2
 	mskbl	t3, a1, t3
 	or	t3, t2, t3		/* add *from to quad around *to */
 	stq_u	t3, 0(a1)		/* write out that quad */
 	subl	a2, 1, a2		/* len-- */
 	beq	t1, 2f			/* if (*from == 0), bail out */
 	addq	a1, 1, a1		/* to++ */
 	addq	a0, 1, a0		/* from++ */
 	bne	a2, 1b			/* if (len != 0) copy more */
 :	beq	a3, 3f			/* if (lenp != NULL) */
 	subl	t0, a2, t0		/* *lenp = (i - len) */
 	stq	t0, 0(a3)
 :	beq	t1, 4f			/* *from == '\0'; leave quietly */
 	ldiq	v0, ENAMETOOLONG	/* *from != '\0'; error. */
 	RET
 :	mov	zero, v0		/* return 0. */
 	RET
 	END(alpha_copystr)
 NESTED(copyinstr, 4, 16, ra, IM_RA|IM_S0, 0)
 	LDGP(pv)
 	lda	sp, -16(sp)			/* set up stack frame	     */
 	stq	ra, (16-8)(sp)			/* save ra		     */
 	stq	s0, (16-16)(sp)			/* save s0		     */
 	ldiq	t0, VM_MAX_ADDRESS		/* make sure that src addr   */
 	cmpult	a0, t0, t1			/* is in user space.	     */
 	beq	t1, copyerr_efault		/* if it's not, error out.   */
 	/* Note: GET_CURLWP clobbers v0, t0, t8...t11. */
 	GET_CURLWP
 	mov	v0, s0
 	lda	v0, copyerr			/* set up fault handler.     */
 	.set noat
 	ldq	at_reg, 0(s0)
 	ldq	at_reg, L_PCB(at_reg)
 	stq	v0, PCB_ONFAULT(at_reg)
 	.set at
 	CALL(alpha_copystr)			/* do the copy.		     */
 	.set noat
 	ldq	at_reg, 0(s0)			/* kill the fault handler.   */
 	ldq	at_reg, L_PCB(at_reg)
 	stq	zero, PCB_ONFAULT(at_reg)
 	.set at
 	ldq	ra, (16-8)(sp)			/* restore ra.		     */
 	ldq	s0, (16-16)(sp)			/* restore s0.		     */
 	lda	sp, 16(sp)			/* kill stack frame.	     */
 	RET					/* v0 left over from copystr */
 	END(copyinstr)
 NESTED(copyoutstr, 4, 16, ra, IM_RA|IM_S0, 0)
 	LDGP(pv)
 	lda	sp, -16(sp)			/* set up stack frame	     */
 	stq	ra, (16-8)(sp)			/* save ra		     */
 	stq	s0, (16-16)(sp)			/* save s0		     */
 	ldiq	t0, VM_MAX_ADDRESS		/* make sure that dest addr  */
 	cmpult	a1, t0, t1			/* is in user space.	     */
 	beq	t1, copyerr_efault		/* if it's not, error out.   */
 	/* Note: GET_CURLWP clobbers v0, t0, t8...t11. */
 	GET_CURLWP
 	mov	v0, s0
 	lda	v0, copyerr			/* set up fault handler.     */
 	.set noat
 	ldq	at_reg, 0(s0)
 	ldq	at_reg, L_PCB(at_reg)
 	stq	v0, PCB_ONFAULT(at_reg)
 	.set at
 	CALL(alpha_copystr)			/* do the copy.		     */
 	.set noat
 	ldq	at_reg, 0(s0)			/* kill the fault handler.   */
 	ldq	at_reg, L_PCB(at_reg)
 	stq	zero, PCB_ONFAULT(at_reg)
 	.set at
 	ldq	ra, (16-8)(sp)			/* restore ra.		     */
 	ldq	s0, (16-16)(sp)			/* restore s0.		     */
 	lda	sp, 16(sp)			/* kill stack frame.	     */
 	RET					/* v0 left over from copystr */
 	END(copyoutstr)
 /*
  * kcopy(const void *src, void *dst, size_t len);
+ *
  * Copy len bytes from src to dst, aborting if we encounter a fatal
  * page fault.
+ *
  * kcopy() _must_ save and restore the old fault handler since it is
  * called by uiomove(), which may be in the path of servicing a non-fatal
  * page fault.
  */
 NESTED(kcopy, 3, 32, ra, IM_RA|IM_S0|IM_S1, 0)
 	LDGP(pv)
 	lda	sp, -32(sp)			/* set up stack frame	     */
 	stq	ra, (32-8)(sp)			/* save ra		     */
 	stq	s0, (32-16)(sp)			/* save s0		     */
 	stq	s1, (32-24)(sp)			/* save s1		     */
 	/* Swap a0, a1, for call to memcpy(). */
 	mov	a1, v0
 	mov	a0, a1
 	mov	v0, a0
 	/* Note: GET_CURLWP clobbers v0, t0, t8...t11. */
 	GET_CURLWP
 	ldq	s1, 0(v0)			/* s1 = curlwp		     */
 	lda	v0, kcopyerr			/* set up fault handler.     */
 	.set noat
 	ldq	at_reg, L_PCB(s1)
 	ldq	s0, PCB_ONFAULT(at_reg)	/* save old handler.	     */
 	stq	v0, PCB_ONFAULT(at_reg)
 	.set at
 	CALL(memcpy)				/* do the copy.		     */
 	.set noat
 	ldq	at_reg, L_PCB(s1)		/* restore the old handler.  */
 	stq	s0, PCB_ONFAULT(at_reg)
 	.set at
 	ldq	ra, (32-8)(sp)			/* restore ra.		     */
 	ldq	s0, (32-16)(sp)			/* restore s0.		     */
 	ldq	s1, (32-24)(sp)			/* restore s1.		     */
 	lda	sp, 32(sp)			/* kill stack frame.	     */
 	mov	zero, v0			/* return 0. */
 	RET
 	END(kcopy)
 LEAF(kcopyerr, 0)
 	LDGP(pv)
 	.set noat
 	ldq	at_reg, L_PCB(s1)		/* restore the old handler.  */
 	stq	s0, PCB_ONFAULT(at_reg)
 	.set at
 	ldq	ra, (32-8)(sp)			/* restore ra.		     */
 	ldq	s0, (32-16)(sp)			/* restore s0.		     */
 	ldq	s1, (32-24)(sp)			/* restore s1.		     */
 	lda	sp, 32(sp)			/* kill stack frame.	     */
 	RET
 END(kcopyerr)
 NESTED(copyin, 3, 16, ra, IM_RA|IM_S0, 0)
 	LDGP(pv)
 	lda	sp, -16(sp)			/* set up stack frame	     */
 	stq	ra, (16-8)(sp)			/* save ra		     */
 	stq	s0, (16-16)(sp)			/* save s0		     */
 	ldiq	t0, VM_MAX_ADDRESS		/* make sure that src addr   */
 	cmpult	a0, t0, t1			/* is in user space.	     */
 	beq	t1, copyerr_efault		/* if it's not, error out.   */
 	/* Swap a0, a1, for call to memcpy(). */
 	mov	a1, v0
 	mov	a0, a1
 	mov	v0, a0
 	/* Note: GET_CURLWP clobbers v0, t0, t8...t11. */
 	GET_CURLWP
 	ldq	s0, 0(v0)			/* s0 = curlwp		     */
 	lda	v0, copyerr			/* set up fault handler.     */
 	.set noat
 	ldq	at_reg, L_PCB(s0)
 	stq	v0, PCB_ONFAULT(at_reg)
 	.set at
 	CALL(memcpy)				/* do the copy.		     */
 	.set noat
 	ldq	at_reg, L_PCB(s0)		/* kill the fault handler.   */
 	stq	zero, PCB_ONFAULT(at_reg)
 	.set at
 	ldq	ra, (16-8)(sp)			/* restore ra.		     */
 	ldq	s0, (16-16)(sp)			/* restore s0.		     */
 	lda	sp, 16(sp)			/* kill stack frame.	     */
 	mov	zero, v0			/* return 0. */
 	RET
 	END(copyin)
 NESTED(copyout, 3, 16, ra, IM_RA|IM_S0, 0)
 	LDGP(pv)
 	lda	sp, -16(sp)			/* set up stack frame	     */
 	stq	ra, (16-8)(sp)			/* save ra		     */
 	stq	s0, (16-16)(sp)			/* save s0		     */
 	ldiq	t0, VM_MAX_ADDRESS		/* make sure that dest addr  */
 	cmpult	a1, t0, t1			/* is in user space.	     */
 	beq	t1, copyerr_efault		/* if it's not, error out.   */
 	/* Swap a0, a1, for call to memcpy(). */
 	mov	a1, v0
 	mov	a0, a1
 	mov	v0, a0
 	/* Note: GET_CURLWP clobbers v0, t0, t8...t11. */
 	GET_CURLWP
 	ldq	s0, 0(v0)			/* s0 = curlwp		     */
 	lda	v0, copyerr			/* set up fault handler.     */
 	.set noat
 	ldq	at_reg, L_PCB(s0)
 	stq	v0, PCB_ONFAULT(at_reg)
 	.set at
 	CALL(memcpy)				/* do the copy.		     */
 	.set noat
 	ldq	at_reg, L_PCB(s0)		/* kill the fault handler.   */
 	stq	zero, PCB_ONFAULT(at_reg)
 	.set at
 	ldq	ra, (16-8)(sp)			/* restore ra.		     */
 	ldq	s0, (16-16)(sp)			/* restore s0.		     */
 	lda	sp, 16(sp)			/* kill stack frame.	     */
 	mov	zero, v0			/* return 0. */
 	RET
 	END(copyout)
 LEAF(copyerr_efault, 0)
 	ldiq	v0, EFAULT			/* return EFAULT.	     */
 XLEAF(copyerr, 0)
 	LDGP(pv)
 	ldq	ra, (16-8)(sp)			/* restore ra.		     */
 	ldq	s0, (16-16)(sp)			/* restore s0.		     */
 	lda	sp, 16(sp)			/* kill stack frame.	     */
 	RET
 END(copyerr)
 /**************************************************************************/
 #define	UFETCHSTORE_PROLOGUE						 \
 	br	pv, 1f							;\
 :	LDGP(pv)							;\
 	ldiq	t0, VM_MAX_ADDRESS	/* make sure that addr */	;\
 	cmpult	a0, t0, t1		/* is in user space. */		;\
 	beq	t1, ufetchstoreerr_efault /* if it's not, error out. */
 /* LINTSTUB: int _ufetch_8(const uint8_t *uaddr, uint8_t *valp); */
 LEAF_NOPROFILE(_ufetch_8, 2)
 	UFETCHSTORE_PROLOGUE
 .L_ufetch_8_start:
 	ldq_u	t0, 0(a0)	/* load quad containing byte */
 .L_ufetch_8_end:
 	extbl	t0, a0, a0	/* a0 = extracted byte */
 	ldq_u	t0, 0(a1)	/* load dest quad */
 	insbl	a0, a1, a0	/* a0 = byte in target position */
 	mskbl	t0, a1, t0	/* clear target byte in destination */
 	or	a0, t0, a0	/* or in byte to destionation */
 	stq_u	a0, 0(a1)	/* *a1 = fetched byte! */
 	mov	zero, v0
 	RET
 	END(_ufetch_8)
 /* LINTSTUB: int _ufetch_16(const uint16_t *uaddr, uint16_t *valp); */
 LEAF_NOPROFILE(_ufetch_16, 2)
 	UFETCHSTORE_PROLOGUE
 .L_ufetch_16_start:
 	ldq_u	t0, 0(a0)	/* load quad containing short */
 .L_ufetch_16_end:
 	extwl	t0, a0, a0	/* a0 = extracted short */
 	ldq_u	t0, 0(a1)	/* load dest quad */
 	inswl	a0, a1, a0	/* a0 = short in target position */
 	mskwl	t0, a1, t0	/* clear target short in destination */
 	or	a0, t0, a0	/* or in short to destionation */
 	stq_u	a0, 0(a1)	/* *a1 = fetched short! */
 	mov	zero, v0
 	RET
 	END(_ufetch_16)
 /* LINTSTUB: int _ufetch_32(const uint32_t *uaddr, uint32_t *valp); */
 LEAF_NOPROFILE(_ufetch_32, 2)
 	UFETCHSTORE_PROLOGUE
 .L_ufetch_32_start:
 	ldl	v0, 0(a0)
 .L_ufetch_32_end:
 	stl	v0, 0(a1)
 	mov	zero, v0
 	RET
 	END(_ufetch_32)
 /* LINTSTUB: int _ufetch_64(const uint64_t *uaddr, uint64_t *valp); */
 LEAF_NOPROFILE(_ufetch_64, 2)
 	UFETCHSTORE_PROLOGUE
 .L_ufetch_64_start:
 	ldq	v0, 0(a0)
 .L_ufetch_64_end:
 	stq	v0, 0(a1)
 	mov	zero, v0
 	RET
 	END(_ufetch_64)
 /* LINTSTUB: int _ustore_8(uint8_t *uaddr, uint8_t val); */
 LEAF_NOPROFILE(_ustore_8, 2)
 	UFETCHSTORE_PROLOGUE
 	zap	a1, 0xfe, a1	/* kill arg's high bytes */
 	insbl	a1, a0, a1	/* move it to the right spot */
 .L_ustore_8_start:
 	ldq_u	t0, 0(a0)	/* load quad around byte */
 	mskbl	t0, a0, t0	/* kill the target byte */
 	or	t0, a1, a1	/* put the result together */
 	stq_u	a1, 0(a0)	/* and store it. */
 .L_ustore_8_end:
 	mov	zero, v0
 	RET
 	END(_ustore_8)
 /* LINTSTUB: int _ustore_16(uint16_t *uaddr, uint16_t val); */
 LEAF_NOPROFILE(_ustore_16, 2)
 	UFETCHSTORE_PROLOGUE
 	zap	a1, 0xfc, a1	/* kill arg's high bytes */
 	inswl	a1, a0, a1	/* move it to the right spot */
 .L_ustore_16_start:
 	ldq_u	t0, 0(a0)	/* load quad around short */
 	mskwl	t0, a0, t0	/* kill the target short */
 	or	t0, a1, a1	/* put the result together */
 	stq_u	a1, 0(a0)	/* and store it. */
 .L_ustore_16_end:
 	mov	zero, v0
 	RET
 	END(_ustore_16)
 /* LINTSTUB: int _ustore_32(uint32_t *uaddr, uint32_t val); */
 LEAF_NOPROFILE(_ustore_32, 2)
 	UFETCHSTORE_PROLOGUE
 .L_ustore_32_start:
 	stl	a1, 0(a0)
 .L_ustore_32_end:
 	mov	zero, v0
 	RET
 	END(_ustore_32)
 /* LINTSTUB: int _ustore_64(uint64_t *uaddr, uint64_t val); */
 LEAF_NOPROFILE(_ustore_64, 2)
 	UFETCHSTORE_PROLOGUE
 .L_ustore_64_start:
 	stq	a1, 0(a0)
 .L_ustore_64_end:
 	mov	zero, v0
 	RET
 	END(_ustore_64)
 LEAF_NOPROFILE(ufetchstoreerr_efault, 0)
 	ldiq	v0, EFAULT	/* return EFAULT. */
 XLEAF(ufetchstoreerr, 0)
 	LDGP(pv)
 	RET
 	END(ufetchstoreerr_efault)
 /**************************************************************************/
 /*
  * int _ucas_32(volatile uint32_t *uptr, uint32_t old, uint32_t new,
  *		uint32_t *ret);
  */
 LEAF_NOPROFILE(_ucas_32, 4)
 	UFETCHSTORE_PROLOGUE
 :
 .Lucas_32_start:
 	mov	a2, t2
 	ldl_l	t0, 0(a0)			/* t0 = *uptr */
 	cmpeq	t0, a1, t1			/* does t0 = old? */
 	beq	t1, 1f				/* if not, skip */
 	stl_c	t2, 0(a0)			/* *uptr ~= new */
 .Lucas_32_end:
 	beq	t1, 2f				/* did it work? */
 :
 	stl	t0, 0(a3)			/* *ret = t0 */
 	mov	zero, v0
 	RET
 :
 	br	3b
 END(_ucas_32)
 /*
  * int _ucas_64(volatile uint64_t *uptr, uint64_t old, uint64_t new,
  *		uint64_t *ret);
  */
 LEAF_NOPROFILE(_ucas_64, 4)
 	UFETCHSTORE_PROLOGUE
 :
 .Lucas_64_start:
 	mov	a2, t2
 	ldq_l	t0, 0(a0)			/* t0 = *uptr */
 	cmpeq	t0, a1, t1			/* does t0 = old? */
 	beq	t1, 1f				/* if not, skip */
 	stq_c	t2, 0(a0)			/* *uptr ~= new */
 .Lucas_64_end:
 	beq	t1, 2f				/* did it work? */
 :
 	stq	t0, 0(a3)			/* *ret = t0 */
 	mov	zero, v0
 	RET
 :
 	br	3b
 END(_ucas_64)
 /**************************************************************************/
 /*
  * Fault table of user access functions for trap().
  */
 	.section ".rodata"
 	.globl	onfault_table
 onfault_table:
 	.quad	.L_ufetch_8_start
 	.quad	.L_ufetch_8_end
 	.quad	ufetchstoreerr
 	.quad	.L_ufetch_16_start
 	.quad	.L_ufetch_16_end
 	.quad	ufetchstoreerr
 	.quad	.L_ufetch_32_start
 	.quad	.L_ufetch_32_end
 	.quad	ufetchstoreerr
 	.quad	.L_ufetch_64_start

 @@ -1,1932 +1,1900 @@
-/* $NetBSD: machdep.c,v 1.362 2020/09/02 17:40:23 riastradh Exp $ */
+/* $NetBSD: machdep.c,v 1.363 2020/09/03 02:09:09 thorpej Exp $ */
 /*-
  * Copyright (c) 1998, 1999, 2000, 2019 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
  * NASA Ames Research Center and by Chris G. Demetriou.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
  * All rights reserved.
+ *
  * Author: Chris G. Demetriou
+ *
  * Permission to use, copy, modify and distribute this software and
  * its documentation is hereby granted, provided that both the copyright
  * notice and this permission notice appear in all copies of the
  * software, derivative works or modified versions, and any portions
  * thereof, and that both notices appear in supporting documentation.
+ *
  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
  * Carnegie Mellon requests users of this software to return to
+ *
  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  *  School of Computer Science
  *  Carnegie Mellon University
  *  Pittsburgh PA 15213-3890
+ *
  * any improvements or extensions that they make and grant Carnegie the
  * rights to redistribute these changes.
  */
 #include "opt_ddb.h"
 #include "opt_kgdb.h"
 #include "opt_modular.h"
 #include "opt_multiprocessor.h"
 #include "opt_dec_3000_300.h"
 #include "opt_dec_3000_500.h"
 #include "opt_execfmt.h"
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.362 2020/09/02 17:40:23 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.363 2020/09/03 02:09:09 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/signalvar.h>
 #include <sys/kernel.h>
 #include <sys/cpu.h>
 #include <sys/proc.h>
 #include <sys/ras.h>
 #include <sys/sched.h>
 #include <sys/reboot.h>
 #include <sys/device.h>
 #include <sys/malloc.h>
 #include <sys/module.h>
 #include <sys/mman.h>
 #include <sys/msgbuf.h>
 #include <sys/ioctl.h>
 #include <sys/tty.h>
 #include <sys/exec.h>
 #include <sys/exec_aout.h>		/* for MID_* */
 #include <sys/exec_ecoff.h>
 #include <sys/core.h>
 #include <sys/kcore.h>
 #include <sys/ucontext.h>
 #include <sys/conf.h>
 #include <sys/ksyms.h>
 #include <sys/kauth.h>
 #include <sys/atomic.h>
 #include <sys/cpu.h>
 #include <machine/kcore.h>
 #include <machine/fpu.h>
 #include <sys/mount.h>
 #include <sys/syscallargs.h>
 #include <uvm/uvm.h>
 #include <sys/sysctl.h>
 #include <dev/cons.h>
 #include <dev/mm.h>
 #include <machine/autoconf.h>
 #include <machine/reg.h>
 #include <machine/rpb.h>
 #include <machine/prom.h>
 #include <machine/cpuconf.h>
 #include <machine/ieeefp.h>
 #ifdef DDB
 #include <machine/db_machdep.h>
 #include <ddb/db_access.h>
 #include <ddb/db_sym.h>
 #include <ddb/db_extern.h>
 #include <ddb/db_interface.h>
 #endif
 #ifdef KGDB
 #include <sys/kgdb.h>
 #endif
 #ifdef DEBUG
 #include <machine/sigdebug.h>
 int sigdebug = 0x0;
 int sigpid = 0;
 #endif
 #include <machine/alpha.h>
 #include "ksyms.h"
 struct vm_map *phys_map = NULL;
 void *msgbufaddr;
 int	maxmem;			/* max memory per process */
 int	totalphysmem;		/* total amount of physical memory in system */
 int	resvmem;		/* amount of memory reserved for PROM */
 int	unusedmem;		/* amount of memory for OS that we don't use */
 int	unknownmem;		/* amount of memory with an unknown use */
 int	cputype;		/* system type, from the RPB */
 int	bootdev_debug = 0;	/* patchable, or from DDB */
 /*
  * XXX We need an address to which we can assign things so that they
  * won't be optimized away because we didn't use the value.
  */
 uint32_t no_optimize;
 /* the following is used externally (sysctl_hw) */
 char	machine[] = MACHINE;		/* from <machine/param.h> */
 char	machine_arch[] = MACHINE_ARCH;	/* from <machine/param.h> */
 /* Number of machine cycles per microsecond */
 uint64_t	cycles_per_usec;
 /* number of CPUs in the box.  really! */
 int		ncpus;
 struct bootinfo_kernel bootinfo;
 /* For built-in TCDS */
 #if defined(DEC_3000_300) || defined(DEC_3000_500)
 uint8_t	dec_3000_scsiid[3], dec_3000_scsifast[3];
 #endif
 struct platform platform;
 #if NKSYMS || defined(DDB) || defined(MODULAR)
 /* start and end of kernel symbol table */
 void	*ksym_start, *ksym_end;
 #endif
 /* for cpu_sysctl() */
 int	alpha_unaligned_print = 1;	/* warn about unaligned accesses */
 int	alpha_unaligned_fix = 1;	/* fix up unaligned accesses */
 int	alpha_unaligned_sigbus = 0;	/* don't SIGBUS on fixed-up accesses */
 int	alpha_fp_sync_complete = 0;	/* fp fixup if sync even without /s */
 /*
  * XXX This should be dynamically sized, but we have the chicken-egg problem!
  * XXX it should also be larger than it is, because not all of the mddt
  * XXX clusters end up being used for VM.
  */
 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];	/* low size bits overloaded */
 int	mem_cluster_cnt;
 int	cpu_dump(void);
 int	cpu_dumpsize(void);
 u_long	cpu_dump_mempagecnt(void);
 void	dumpsys(void);
 void	identifycpu(void);
 void	printregs(struct reg *);
 const pcu_ops_t fpu_ops = {
 	.pcu_id = PCU_FPU,
 	.pcu_state_load = fpu_state_load,
 	.pcu_state_save = fpu_state_save,
 	.pcu_state_release = fpu_state_release,
 };
 const pcu_ops_t * const pcu_ops_md_defs[PCU_UNIT_COUNT] = {
 	[PCU_FPU] = &fpu_ops,
 };
 void
 alpha_init(u_long xxx_pfn __unused, u_long ptb, u_long bim, u_long bip,
     u_long biv)
 	/* pfn:		 first free PFN number (no longer used) */
 	/* ptb:		 PFN of current level 1 page table */
 	/* bim:		 bootinfo magic */
 	/* bip:		 bootinfo pointer */
 	/* biv:		 bootinfo version */
+{
 	extern char kernel_text[], _end[];
 	struct mddt *mddtp;
 	struct mddt_cluster *memc;
 	int i, mddtweird;
 	struct pcb *pcb0;
 	vaddr_t kernstart, kernend, v;
 	paddr_t kernstartpfn, kernendpfn, pfn0, pfn1;
 	cpuid_t cpu_id;
 	struct cpu_info *ci;
 	char *p;
 	const char *bootinfo_msg;
 	const struct cpuinit *c;
 	/* NO OUTPUT ALLOWED UNTIL FURTHER NOTICE */
 	/*
 	 * Turn off interrupts (not mchecks) and floating point.
 	 * Make sure the instruction and data streams are consistent.
 	 */
 	(void)alpha_pal_swpipl(ALPHA_PSL_IPL_HIGH);
 	alpha_pal_wrfen(0);
 	ALPHA_TBIA();
 	alpha_pal_imb();
 	/* Initialize the SCB. */
 	scb_init();
 	cpu_id = cpu_number();
 #if defined(MULTIPROCESSOR)
 	/*
 	 * Set our SysValue to the address of our cpu_info structure.
 	 * Secondary processors do this in their spinup trampoline.
 	 */
 	alpha_pal_wrval((u_long)&cpu_info_primary);
 	cpu_info[cpu_id] = &cpu_info_primary;
 #endif
 	ci = curcpu();
 	ci->ci_cpuid = cpu_id;
 	/*
 	 * Get critical system information (if possible, from the
 	 * information provided by the boot program).
 	 */
 	bootinfo_msg = NULL;
 	if (bim == BOOTINFO_MAGIC) {
 		if (biv == 0) {		/* backward compat */
 			biv = *(u_long *)bip;
 			bip += 8;
+		}
 		switch (biv) {
 		case 1: {
 			struct bootinfo_v1 *v1p = (struct bootinfo_v1 *)bip;
 			bootinfo.ssym = v1p->ssym;
 			bootinfo.esym = v1p->esym;
 			/* hwrpb may not be provided by boot block in v1 */
 			if (v1p->hwrpb != NULL) {
 				bootinfo.hwrpb_phys =
 				    ((struct rpb *)v1p->hwrpb)->rpb_phys;
 				bootinfo.hwrpb_size = v1p->hwrpbsize;
 			} else {
 				bootinfo.hwrpb_phys =
 				    ((struct rpb *)HWRPB_ADDR)->rpb_phys;
 				bootinfo.hwrpb_size =
 				    ((struct rpb *)HWRPB_ADDR)->rpb_size;
+			}
 			memcpy(bootinfo.boot_flags, v1p->boot_flags,
 			    uimin(sizeof v1p->boot_flags,
 			      sizeof bootinfo.boot_flags));
 			memcpy(bootinfo.booted_kernel, v1p->booted_kernel,
 			    uimin(sizeof v1p->booted_kernel,
 			      sizeof bootinfo.booted_kernel));
 			/* booted dev not provided in bootinfo */
-			init_prom_interface((struct rpb *)
+			init_prom_interface(ptb, (struct rpb *)
 			    ALPHA_PHYS_TO_K0SEG(bootinfo.hwrpb_phys));
 	        	prom_getenv(PROM_E_BOOTED_DEV, bootinfo.booted_dev,
 			    sizeof bootinfo.booted_dev);
 			break;
+		}
 		default:
 			bootinfo_msg = "unknown bootinfo version";
 			goto nobootinfo;
+		}
 	} else {
 		bootinfo_msg = "boot program did not pass bootinfo";
 nobootinfo:
 		bootinfo.ssym = (u_long)_end;
 		bootinfo.esym = (u_long)_end;
 		bootinfo.hwrpb_phys = ((struct rpb *)HWRPB_ADDR)->rpb_phys;
 		bootinfo.hwrpb_size = ((struct rpb *)HWRPB_ADDR)->rpb_size;
-		init_prom_interface((struct rpb *)HWRPB_ADDR);
+		init_prom_interface(ptb, (struct rpb *)HWRPB_ADDR);
 		prom_getenv(PROM_E_BOOTED_OSFLAGS, bootinfo.boot_flags,
 		    sizeof bootinfo.boot_flags);
 		prom_getenv(PROM_E_BOOTED_FILE, bootinfo.booted_kernel,
 		    sizeof bootinfo.booted_kernel);
 		prom_getenv(PROM_E_BOOTED_DEV, bootinfo.booted_dev,
 		    sizeof bootinfo.booted_dev);
+	}
 	/*
 	 * Initialize the kernel's mapping of the RPB.  It's needed for
 	 * lots of things.
 	 */
 	hwrpb = (struct rpb *)ALPHA_PHYS_TO_K0SEG(bootinfo.hwrpb_phys);
 #if defined(DEC_3000_300) || defined(DEC_3000_500)
 	if (hwrpb->rpb_type == ST_DEC_3000_300 ||
 	    hwrpb->rpb_type == ST_DEC_3000_500) {
 		prom_getenv(PROM_E_SCSIID, dec_3000_scsiid,
 		    sizeof(dec_3000_scsiid));
 		prom_getenv(PROM_E_SCSIFAST, dec_3000_scsifast,
 		    sizeof(dec_3000_scsifast));
+	}
 #endif
 	/*
 	 * Remember how many cycles there are per microsecond,
 	 * so that we can use delay().  Round up, for safety.
 	 */
 	cycles_per_usec = (hwrpb->rpb_cc_freq + 999999) / 1000000;
 	/*
 	 * Initialize the (temporary) bootstrap console interface, so
 	 * we can use printf until the VM system starts being setup.
 	 * The real console is initialized before then.
 	 */
 	init_bootstrap_console();
 	/* OUTPUT NOW ALLOWED */
 	/* delayed from above */
 	if (bootinfo_msg)
 		printf("WARNING: %s (0x%lx, 0x%lx, 0x%lx)\n",
 		    bootinfo_msg, bim, bip, biv);
 	/* Initialize the trap vectors on the primary processor. */
 	trap_init();
 	/*
 	 * Find out this system's page size, and initialize
 	 * PAGE_SIZE-dependent variables.
 	 */
 	if (hwrpb->rpb_page_size != ALPHA_PGBYTES)
 		panic("page size %lu != %d?!", hwrpb->rpb_page_size,
 		    ALPHA_PGBYTES);
 	uvmexp.pagesize = hwrpb->rpb_page_size;
 	uvm_md_init();
 	/*
-	 * Find out what hardware we're on, and do basic initialization.
+	 * cputype has been initialized in init_prom_interface().
 	 * Perform basic platform initialization using this info.
 	 */
-	cputype = hwrpb->rpb_type;
+	KASSERT(prom_interface_initialized);
 	if (cputype < 0) {
 		/*
 		 * At least some white-box systems have SRM which
 		 * reports a systype that's the negative of their
 		 * blue-box counterpart.
 		 */
 		cputype = -cputype;
 	c = platform_lookup(cputype);
 	if (c == NULL) {
 		platform_not_supported();
 		/* NOTREACHED */
+	}
 	(*c->init)();
 	cpu_setmodel("%s", platform.model);
 	/*
 	 * Initialize the real console, so that the bootstrap console is
 	 * no longer necessary.
 	 */
 	(*platform.cons_init)();
 #ifdef DIAGNOSTIC
 	/* Paranoid sanity checking */
 	/* We should always be running on the primary. */
 	assert(hwrpb->rpb_primary_cpu_id == cpu_id);
 	/*
 	 * On single-CPU systypes, the primary should always be CPU 0,
 	 * except on Alpha 8200 systems where the CPU id is related
 	 * to the VID, which is related to the Turbo Laser node id.
 	 */
 	if (cputype != ST_DEC_21000)
 		assert(hwrpb->rpb_primary_cpu_id == 0);
 #endif
 	/* NO MORE FIRMWARE ACCESS ALLOWED */
-#ifdef _PMAP_MAY_USE_PROM_CONSOLE
+	/* XXX Unless prom_uses_prom_console() evaluates to non-zero.) */
 	/*
 	 * XXX (unless _PMAP_MAY_USE_PROM_CONSOLE is defined and
 	 * XXX pmap_uses_prom_console() evaluates to non-zero.)
 	 */
 #endif
 	/*
 	 * Find the beginning and end of the kernel (and leave a
 	 * bit of space before the beginning for the bootstrap
 	 * stack).
 	 */
 	kernstart = trunc_page((vaddr_t)kernel_text) - 2 * PAGE_SIZE;
 #if NKSYMS || defined(DDB) || defined(MODULAR)
 	ksym_start = (void *)bootinfo.ssym;
 	ksym_end   = (void *)bootinfo.esym;
 	kernend = (vaddr_t)round_page((vaddr_t)ksym_end);
 #else
 	kernend = (vaddr_t)round_page((vaddr_t)_end);
 #endif
 	kernstartpfn = atop(ALPHA_K0SEG_TO_PHYS(kernstart));
 	kernendpfn = atop(ALPHA_K0SEG_TO_PHYS(kernend));
 	/*
 	 * Find out how much memory is available, by looking at
 	 * the memory cluster descriptors.  This also tries to do
 	 * its best to detect things things that have never been seen
 	 * before...
 	 */
 	mddtp = (struct mddt *)(((char *)hwrpb) + hwrpb->rpb_memdat_off);
 	/* MDDT SANITY CHECKING */
 	mddtweird = 0;
 	if (mddtp->mddt_cluster_cnt < 2) {
 		mddtweird = 1;
 		printf("WARNING: weird number of mem clusters: %lu\n",
 		    mddtp->mddt_cluster_cnt);
+	}
 #if 0
 	printf("Memory cluster count: %" PRIu64 "\n", mddtp->mddt_cluster_cnt);
 #endif
 	for (i = 0; i < mddtp->mddt_cluster_cnt; i++) {
 		memc = &mddtp->mddt_clusters[i];
 #if 0
 		printf("MEMC %d: pfn 0x%lx cnt 0x%lx usage 0x%lx\n", i,
 		    memc->mddt_pfn, memc->mddt_pg_cnt, memc->mddt_usage);
 #endif
 		totalphysmem += memc->mddt_pg_cnt;
 		if (mem_cluster_cnt < VM_PHYSSEG_MAX) {	/* XXX */
 			mem_clusters[mem_cluster_cnt].start =
 			    ptoa(memc->mddt_pfn);
 			mem_clusters[mem_cluster_cnt].size =
 			    ptoa(memc->mddt_pg_cnt);
 			if (memc->mddt_usage & MDDT_mbz ||
 			    memc->mddt_usage & MDDT_NONVOLATILE || /* XXX */
 			    memc->mddt_usage & MDDT_PALCODE)
 				mem_clusters[mem_cluster_cnt].size |=
 				    PROT_READ;
 			else
 				mem_clusters[mem_cluster_cnt].size |=
 				    PROT_READ | PROT_WRITE | PROT_EXEC;
 			mem_cluster_cnt++;
+		}
 		if (memc->mddt_usage & MDDT_mbz) {
 			mddtweird = 1;
 			printf("WARNING: mem cluster %d has weird "
 			    "usage 0x%lx\n", i, memc->mddt_usage);
 			unknownmem += memc->mddt_pg_cnt;
 			continue;
+		}
 		if (memc->mddt_usage & MDDT_NONVOLATILE) {
 			/* XXX should handle these... */
 			printf("WARNING: skipping non-volatile mem "
 			    "cluster %d\n", i);
 			unusedmem += memc->mddt_pg_cnt;
 			continue;
+		}
 		if (memc->mddt_usage & MDDT_PALCODE) {
 			resvmem += memc->mddt_pg_cnt;
 			continue;
+		}
 		/*
 		 * We have a memory cluster available for system
 		 * software use.  We must determine if this cluster
 		 * holds the kernel.
 		 */
 #ifdef _PMAP_MAY_USE_PROM_CONSOLE
 		/*
 		 * XXX If the kernel uses the PROM console, we only use the
 		 * XXX memory after the kernel in the first system segment,
 		 * XXX to avoid clobbering prom mapping, data, etc.
 		 */
 	    if (!pmap_uses_prom_console() || physmem == 0) {
 #endif /* _PMAP_MAY_USE_PROM_CONSOLE */
 		physmem += memc->mddt_pg_cnt;
 		pfn0 = memc->mddt_pfn;
 		pfn1 = memc->mddt_pfn + memc->mddt_pg_cnt;
 		if (pfn0 <= kernstartpfn && kernendpfn <= pfn1) {
 			/*
 			 * Must compute the location of the kernel
 			 * within the segment.
 			 */
 #if 0
 			printf("Cluster %d contains kernel\n", i);
 #endif
-#ifdef _PMAP_MAY_USE_PROM_CONSOLE
+			if (pfn0 < kernstartpfn && !prom_uses_prom_console()) {
 		    if (!pmap_uses_prom_console()) {
 #endif /* _PMAP_MAY_USE_PROM_CONSOLE */
 			if (pfn0 < kernstartpfn) {
 				/*
 				 * There is a chunk before the kernel.
 				 */
 #if 0
 				printf("Loading chunk before kernel: "
 				    "0x%lx / 0x%lx\n", pfn0, kernstartpfn);
 #endif
 				uvm_page_physload(pfn0, kernstartpfn,
 				    pfn0, kernstartpfn, VM_FREELIST_DEFAULT);
+			}
 #ifdef _PMAP_MAY_USE_PROM_CONSOLE
 #endif /* _PMAP_MAY_USE_PROM_CONSOLE */
 			if (kernendpfn < pfn1) {
 				/*
 				 * There is a chunk after the kernel.
 				 */
 #if 0
 				printf("Loading chunk after kernel: "
 				    "0x%lx / 0x%lx\n", kernendpfn, pfn1);
 #endif
 				uvm_page_physload(kernendpfn, pfn1,
 				    kernendpfn, pfn1, VM_FREELIST_DEFAULT);
+			}
 		} else {
 			/*
 			 * Just load this cluster as one chunk.
 			 */
 #if 0
 			printf("Loading cluster %d: 0x%lx / 0x%lx\n", i,
 			    pfn0, pfn1);
 #endif
 			uvm_page_physload(pfn0, pfn1, pfn0, pfn1,
 			    VM_FREELIST_DEFAULT);
+		}
 #ifdef _PMAP_MAY_USE_PROM_CONSOLE
 #endif /* _PMAP_MAY_USE_PROM_CONSOLE */
+	}
 	/*
 	 * Dump out the MDDT if it looks odd...
 	 */
 	if (mddtweird) {
 		printf("\n");
 		printf("complete memory cluster information:\n");
 		for (i = 0; i < mddtp->mddt_cluster_cnt; i++) {
 			printf("mddt %d:\n", i);
 			printf("\tpfn %lx\n",
 			    mddtp->mddt_clusters[i].mddt_pfn);
 			printf("\tcnt %lx\n",
 			    mddtp->mddt_clusters[i].mddt_pg_cnt);
 			printf("\ttest %lx\n",
 			    mddtp->mddt_clusters[i].mddt_pg_test);
 			printf("\tbva %lx\n",
 			    mddtp->mddt_clusters[i].mddt_v_bitaddr);
 			printf("\tbpa %lx\n",
 			    mddtp->mddt_clusters[i].mddt_p_bitaddr);
 			printf("\tbcksum %lx\n",
 			    mddtp->mddt_clusters[i].mddt_bit_cksum);
 			printf("\tusage %lx\n",
 			    mddtp->mddt_clusters[i].mddt_usage);
+		}
 		printf("\n");
+	}
 	if (totalphysmem == 0)
 		panic("can't happen: system seems to have no memory!");
 	maxmem = physmem;
 #if 0
 	printf("totalphysmem = %d\n", totalphysmem);
 	printf("physmem = %lu\n", physmem);
 	printf("resvmem = %d\n", resvmem);
 	printf("unusedmem = %d\n", unusedmem);
 	printf("unknownmem = %d\n", unknownmem);
 #endif
 	/*
 	 * Initialize error message buffer (at end of core).
 	 */
+	{
 		paddr_t end;
 		vsize_t sz = (vsize_t)round_page(MSGBUFSIZE);
 		vsize_t reqsz = sz;
 		uvm_physseg_t bank;
 		bank = uvm_physseg_get_last();
 		/* shrink so that it'll fit in the last segment */
 		if (uvm_physseg_get_avail_end(bank) - uvm_physseg_get_avail_start(bank) < atop(sz))
 			sz = ptoa(uvm_physseg_get_avail_end(bank) - uvm_physseg_get_avail_start(bank));
 		end = uvm_physseg_get_end(bank);
 		end -= atop(sz);
 		uvm_physseg_unplug(end, atop(sz));
 		msgbufaddr = (void *) ALPHA_PHYS_TO_K0SEG(ptoa(end));
 		initmsgbuf(msgbufaddr, sz);
 		/* warn if the message buffer had to be shrunk */
 		if (sz != reqsz)
 			printf("WARNING: %ld bytes not available for msgbuf "
 			    "in last cluster (%ld used)\n", reqsz, sz);
+	}
 	/*
 	 * NOTE: It is safe to use uvm_pageboot_alloc() before
 	 * pmap_bootstrap() because our pmap_virtual_space()
 	 * returns compile-time constants.
 	 */
 	/*
 	 * Allocate uarea page for lwp0 and set it.
 	 */
 	v = uvm_pageboot_alloc(UPAGES * PAGE_SIZE);
 	uvm_lwp_setuarea(&lwp0, v);
 	/*
 	 * Initialize the virtual memory system, and set the
 	 * page table base register in proc 0's PCB.
 	 */
 	pmap_bootstrap(ALPHA_PHYS_TO_K0SEG(ptb << PGSHIFT),
 	    hwrpb->rpb_max_asn, hwrpb->rpb_pcs_cnt);
 	/*
 	 * Initialize the rest of lwp0's PCB and cache its physical address.
 	 */
 	pcb0 = lwp_getpcb(&lwp0);
 	lwp0.l_md.md_pcbpaddr = (void *)ALPHA_K0SEG_TO_PHYS((vaddr_t)pcb0);
 	/*
 	 * Set the kernel sp, reserving space for an (empty) trapframe,
 	 * and make lwp0's trapframe pointer point to it for sanity.
 	 */
 	pcb0->pcb_hw.apcb_ksp = v + USPACE - sizeof(struct trapframe);
 	lwp0.l_md.md_tf = (struct trapframe *)pcb0->pcb_hw.apcb_ksp;
 	/* Indicate that lwp0 has a CPU. */
 	lwp0.l_cpu = ci;
 	/*
 	 * Look at arguments passed to us and compute boothowto.
 	 */
 	boothowto = RB_SINGLE;
 #ifdef KADB
 	boothowto |= RB_KDB;
 #endif
 	for (p = bootinfo.boot_flags; p && *p != '\0'; p++) {
 		/*
 		 * Note that we'd really like to differentiate case here,
 		 * but the Alpha AXP Architecture Reference Manual
 		 * says that we shouldn't.
 		 */
 		switch (*p) {
 		case 'a': /* autoboot */
 		case 'A':
 			boothowto &= ~RB_SINGLE;
 			break;
 #ifdef DEBUG
 		case 'c': /* crash dump immediately after autoconfig */
 		case 'C':
 			boothowto |= RB_DUMP;
 			break;
 #endif
 #if defined(KGDB) || defined(DDB)
 		case 'd': /* break into the kernel debugger ASAP */
 		case 'D':
 			boothowto |= RB_KDB;
 			break;
 #endif
 		case 'h': /* always halt, never reboot */
 		case 'H':
 			boothowto |= RB_HALT;
 			break;
 #if 0
 		case 'm': /* mini root present in memory */
 		case 'M':
 			boothowto |= RB_MINIROOT;
 			break;
 #endif
 		case 'n': /* askname */
 		case 'N':
 			boothowto |= RB_ASKNAME;
 			break;
 		case 's': /* single-user (default, supported for sanity) */
 		case 'S':
 			boothowto |= RB_SINGLE;
 			break;
 		case 'q': /* quiet boot */
 		case 'Q':
 			boothowto |= AB_QUIET;
 			break;
 		case 'v': /* verbose boot */
 		case 'V':
 			boothowto |= AB_VERBOSE;
 			break;
 		case '-':
 			/*
 			 * Just ignore this.  It's not required, but it's
 			 * common for it to be passed regardless.
 			 */
 			break;
 		default:
 			printf("Unrecognized boot flag '%c'.\n", *p);
 			break;
+		}
+	}
 	/*
 	 * Perform any initial kernel patches based on the running system.
 	 * We may perform more later if we attach additional CPUs.
 	 */
 	alpha_patch(false);
 	/*
 	 * Figure out the number of CPUs in the box, from RPB fields.
 	 * Really.  We mean it.
 	 */
 	for (i = 0; i < hwrpb->rpb_pcs_cnt; i++) {
 		struct pcs *pcsp;
 		pcsp = LOCATE_PCS(hwrpb, i);
 		if ((pcsp->pcs_flags & PCS_PP) != 0)
 			ncpus++;
+	}
 	/*
 	 * Initialize debuggers, and break into them if appropriate.
 	 */
 #if NKSYMS || defined(DDB) || defined(MODULAR)
 	ksyms_addsyms_elf((int)((uint64_t)ksym_end - (uint64_t)ksym_start),
 	    ksym_start, ksym_end);
 #endif
 	if (boothowto & RB_KDB) {
 #if defined(KGDB)
 		kgdb_debug_init = 1;
 		kgdb_connect(1);
 #elif defined(DDB)
 		Debugger();
 #endif
+	}
 #ifdef DIAGNOSTIC
 	/*
 	 * Check our clock frequency, from RPB fields.
 	 */
 	if ((hwrpb->rpb_intr_freq >> 12) != 1024)
 		printf("WARNING: unbelievable rpb_intr_freq: %ld (%d hz)\n",
 			hwrpb->rpb_intr_freq, hz);
 #endif
+}
 #ifdef MODULAR
 /* Push any modules loaded by the boot loader */
 void
 module_init_md(void)
+{
 	/* nada. */
+}
 #endif /* MODULAR */
 void
 consinit(void)
+{
 	/*
 	 * Everything related to console initialization is done
 	 * in alpha_init().
 	 */
-#if defined(DIAGNOSTIC) && defined(_PMAP_MAY_USE_PROM_CONSOLE)
+#if defined(DIAGNOSTIC) && defined(_PROM_MAY_USE_PROM_CONSOLE)
 	printf("consinit: %susing prom console\n",
-	    pmap_uses_prom_console() ? "" : "not ");
+	    prom_uses_prom_console() ? "" : "not ");
 #endif
+}
 void
 cpu_startup(void)
+{
 	extern struct evcnt fpevent_use, fpevent_reuse;
 	vaddr_t minaddr, maxaddr;
 	char pbuf[9];
 #if defined(DEBUG)
 	extern int pmapdebug;
 	int opmapdebug = pmapdebug;
 	pmapdebug = 0;
 #endif
 	/*
 	 * Good {morning,afternoon,evening,night}.
 	 */
 	printf("%s%s", copyright, version);
 	identifycpu();
 	format_bytes(pbuf, sizeof(pbuf), ptoa(totalphysmem));
 	printf("total memory = %s\n", pbuf);
 	format_bytes(pbuf, sizeof(pbuf), ptoa(resvmem));
 	printf("(%s reserved for PROM, ", pbuf);
 	format_bytes(pbuf, sizeof(pbuf), ptoa(physmem));
 	printf("%s used by NetBSD)\n", pbuf);
 	if (unusedmem) {
 		format_bytes(pbuf, sizeof(pbuf), ptoa(unusedmem));
 		printf("WARNING: unused memory = %s\n", pbuf);
+	}
 	if (unknownmem) {
 		format_bytes(pbuf, sizeof(pbuf), ptoa(unknownmem));
 		printf("WARNING: %s of memory with unknown purpose\n", pbuf);
+	}
 	minaddr = 0;
 	/*
 	 * Allocate a submap for physio
 	 */
 	phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
 				   VM_PHYS_SIZE, 0, false, NULL);
 	/*
 	 * No need to allocate an mbuf cluster submap.  Mbuf clusters
 	 * are allocated via the pool allocator, and we use K0SEG to
 	 * map those pages.
 	 */
 #if defined(DEBUG)
 	pmapdebug = opmapdebug;
 #endif
 	format_bytes(pbuf, sizeof(pbuf), ptoa(uvm_availmem(false)));
 	printf("avail memory = %s\n", pbuf);
 #if 0
+	{
 		extern u_long pmap_pages_stolen;
 		format_bytes(pbuf, sizeof(pbuf), pmap_pages_stolen * PAGE_SIZE);
 		printf("stolen memory for VM structures = %s\n", pbuf);
+	}
 #endif
 	/*
 	 * Set up the HWPCB so that it's safe to configure secondary
 	 * CPUs.
 	 */
 	hwrpb_primary_init();
 	/*
 	 * Initialize some trap event counters.
 	 */
 	evcnt_attach_dynamic_nozero(&fpevent_use, EVCNT_TYPE_MISC, NULL,
 	    "FP", "proc use");
 	evcnt_attach_dynamic_nozero(&fpevent_reuse, EVCNT_TYPE_MISC, NULL,
 	    "FP", "proc re-use");
+}
 /*
  * Retrieve the platform name from the DSR.
  */
 const char *
 alpha_dsr_sysname(void)
+{
 	struct dsrdb *dsr;
 	const char *sysname;
 	/*
 	 * DSR does not exist on early HWRPB versions.
 	 */
 	if (hwrpb->rpb_version < HWRPB_DSRDB_MINVERS)
 		return (NULL);
 	dsr = (struct dsrdb *)(((char *)hwrpb) + hwrpb->rpb_dsrdb_off);
 	sysname = (const char *)((char *)dsr + (dsr->dsr_sysname_off +
 	    sizeof(uint64_t)));
 	return (sysname);
+}
 /*
  * Lookup the system specified system variation in the provided table,
  * returning the model string on match.
  */
 const char *
 alpha_variation_name(uint64_t variation, const struct alpha_variation_table *avtp)
+{
 	int i;
 	for (i = 0; avtp[i].avt_model != NULL; i++)
 		if (avtp[i].avt_variation == variation)
 			return (avtp[i].avt_model);
 	return (NULL);
+}
 /*
  * Generate a default platform name based for unknown system variations.
  */
 const char *
 alpha_unknown_sysname(void)
+{
 	static char s[128];		/* safe size */
 	snprintf(s, sizeof(s), "%s family, unknown model variation 0x%lx",
 	    platform.family, hwrpb->rpb_variation & SV_ST_MASK);
 	return ((const char *)s);
+}
 void
 identifycpu(void)
+{
 	const char *s;
 	int i;
 	/*
 	 * print out CPU identification information.
 	 */
 	printf("%s", cpu_getmodel());
 	for(s = cpu_getmodel(); *s; ++s)
 		if(strncasecmp(s, "MHz", 3) == 0)
 			goto skipMHz;
 	printf(", %ldMHz", hwrpb->rpb_cc_freq / 1000000);
 skipMHz:
 	printf(", s/n ");
 	for (i = 0; i < 10; i++)
 		printf("%c", hwrpb->rpb_ssn[i]);
 	printf("\n");
 	printf("%ld byte page size, %d processor%s.\n",
 	    hwrpb->rpb_page_size, ncpus, ncpus == 1 ? "" : "s");
 #if 0
 	/* this isn't defined for any systems that we run on? */
 	printf("serial number 0x%lx 0x%lx\n",
 	    ((long *)hwrpb->rpb_ssn)[0], ((long *)hwrpb->rpb_ssn)[1]);
 	/* and these aren't particularly useful! */
 	printf("variation: 0x%lx, revision 0x%lx\n",
 	    hwrpb->rpb_variation, *(long *)hwrpb->rpb_revision);
 #endif
+}
 int	waittime = -1;
 struct pcb dumppcb;
 void
 cpu_reboot(int howto, char *bootstr)
+{
 #if defined(MULTIPROCESSOR)
 	u_long cpu_id = cpu_number();
 	u_long wait_mask;
 	int i;
 #endif
 	/* If "always halt" was specified as a boot flag, obey. */
 	if ((boothowto & RB_HALT) != 0)
 		howto |= RB_HALT;
 	boothowto = howto;
 	/* If system is cold, just halt. */
 	if (cold) {
 		boothowto |= RB_HALT;
 		goto haltsys;
+	}
 	if ((boothowto & RB_NOSYNC) == 0 && waittime < 0) {
 		waittime = 0;
 		vfs_shutdown();
 		/*
 		 * If we've been adjusting the clock, the todr
 		 * will be out of synch; adjust it now.
 		 */
 		resettodr();
+	}
 	/* Disable interrupts. */
 	splhigh();
 #if defined(MULTIPROCESSOR)
 	/*
 	 * Halt all other CPUs.  If we're not the primary, the
 	 * primary will spin, waiting for us to halt.
 	 */
 	cpu_id = cpu_number();		/* may have changed cpu */
 	wait_mask = (1UL << cpu_id) | (1UL << hwrpb->rpb_primary_cpu_id);
 	alpha_broadcast_ipi(ALPHA_IPI_HALT);
 	/* Ensure any CPUs paused by DDB resume execution so they can halt */
 	cpus_paused = 0;
 	for (i = 0; i < 10000; i++) {
 		alpha_mb();
 		if (cpus_running == wait_mask)
 			break;
 		delay(1000);
+	}
 	alpha_mb();
 	if (cpus_running != wait_mask)
 		printf("WARNING: Unable to halt secondary CPUs (0x%lx)\n",
 		    cpus_running);
 #endif /* MULTIPROCESSOR */
 	/* If rebooting and a dump is requested do it. */
 #if 0
 	if ((boothowto & (RB_DUMP | RB_HALT)) == RB_DUMP)
 #else
 	if (boothowto & RB_DUMP)
 #endif
 		dumpsys();
 haltsys:
 	/* run any shutdown hooks */
 	doshutdownhooks();
 	pmf_system_shutdown(boothowto);
 #ifdef BOOTKEY
 	printf("hit any key to %s...\n", howto & RB_HALT ? "halt" : "reboot");
 	cnpollc(1);	/* for proper keyboard command handling */
 	cngetc();
 	cnpollc(0);
 	printf("\n");
 #endif
 	/* Finally, powerdown/halt/reboot the system. */
 	if ((boothowto & RB_POWERDOWN) == RB_POWERDOWN &&
 	    platform.powerdown != NULL) {
 		(*platform.powerdown)();
 		printf("WARNING: powerdown failed!\n");
+	}
 	printf("%s\n\n", (boothowto & RB_HALT) ? "halted." : "rebooting...");
 #if defined(MULTIPROCESSOR)
 	if (cpu_id != hwrpb->rpb_primary_cpu_id)
 		cpu_halt();
 	else
 #endif
 		prom_halt(boothowto & RB_HALT);
 	/*NOTREACHED*/
+}
 /*
  * These variables are needed by /sbin/savecore
  */
 uint32_t dumpmag = 0x8fca0101;	/* magic number */
 int 	dumpsize = 0;		/* pages */
 long	dumplo = 0; 		/* blocks */
 /*
  * cpu_dumpsize: calculate size of machine-dependent kernel core dump headers.
  */
 int
 cpu_dumpsize(void)
+{
 	int size;
 	size = ALIGN(sizeof(kcore_seg_t)) + ALIGN(sizeof(cpu_kcore_hdr_t)) +
 	    ALIGN(mem_cluster_cnt * sizeof(phys_ram_seg_t));
 	if (roundup(size, dbtob(1)) != dbtob(1))
 		return -1;
 	return (1);
+}
 /*
  * cpu_dump_mempagecnt: calculate size of RAM (in pages) to be dumped.
  */
 u_long
 cpu_dump_mempagecnt(void)
+{
 	u_long i, n;
 	n = 0;
 	for (i = 0; i < mem_cluster_cnt; i++)
 		n += atop(mem_clusters[i].size);
 	return (n);
+}
 /*
  * cpu_dump: dump machine-dependent kernel core dump headers.
  */
 int
 cpu_dump(void)
+{
 	int (*dump)(dev_t, daddr_t, void *, size_t);
 	char buf[dbtob(1)];
 	kcore_seg_t *segp;
 	cpu_kcore_hdr_t *cpuhdrp;
 	phys_ram_seg_t *memsegp;
 	const struct bdevsw *bdev;
 	int i;
 	bdev = bdevsw_lookup(dumpdev);
 	if (bdev == NULL)
 		return (ENXIO);
 	dump = bdev->d_dump;
 	memset(buf, 0, sizeof buf);
 	segp = (kcore_seg_t *)buf;
 	cpuhdrp = (cpu_kcore_hdr_t *)&buf[ALIGN(sizeof(*segp))];
 	memsegp = (phys_ram_seg_t *)&buf[ ALIGN(sizeof(*segp)) +
 	    ALIGN(sizeof(*cpuhdrp))];
 	/*
 	 * Generate a segment header.
 	 */
 	CORE_SETMAGIC(*segp, KCORE_MAGIC, MID_MACHINE, CORE_CPU);
 	segp->c_size = dbtob(1) - ALIGN(sizeof(*segp));
 	/*
 	 * Add the machine-dependent header info.
 	 */
 	cpuhdrp->lev1map_pa = ALPHA_K0SEG_TO_PHYS((vaddr_t)kernel_lev1map);
 	cpuhdrp->page_size = PAGE_SIZE;
 	cpuhdrp->nmemsegs = mem_cluster_cnt;
 	/*
 	 * Fill in the memory segment descriptors.
 	 */
 	for (i = 0; i < mem_cluster_cnt; i++) {
 		memsegp[i].start = mem_clusters[i].start;
 		memsegp[i].size = mem_clusters[i].size & ~PAGE_MASK;
+	}
 	return (dump(dumpdev, dumplo, (void *)buf, dbtob(1)));
+}
 /*
  * This is called by main to set dumplo and dumpsize.
  * Dumps always skip the first PAGE_SIZE of disk space
  * in case there might be a disk label stored there.
  * If there is extra space, put dump at the end to
  * reduce the chance that swapping trashes it.
  */
 void
 cpu_dumpconf(void)
+{
 	int nblks, dumpblks;	/* size of dump area */
 	if (dumpdev == NODEV)
 		goto bad;
 	nblks = bdev_size(dumpdev);
 	if (nblks <= ctod(1))
 		goto bad;
 	dumpblks = cpu_dumpsize();
 	if (dumpblks < 0)
 		goto bad;
 	dumpblks += ctod(cpu_dump_mempagecnt());
 	/* If dump won't fit (incl. room for possible label), punt. */
 	if (dumpblks > (nblks - ctod(1)))
 		goto bad;
 	/* Put dump at end of partition */
 	dumplo = nblks - dumpblks;
 	/* dumpsize is in page units, and doesn't include headers. */
 	dumpsize = cpu_dump_mempagecnt();
 	return;
 bad:
 	dumpsize = 0;
 	return;
+}
 /*
  * Dump the kernel's image to the swap partition.
  */
 #define	BYTES_PER_DUMP	PAGE_SIZE
 void
 dumpsys(void)
+{
 	const struct bdevsw *bdev;
 	u_long totalbytesleft, bytes, i, n, memcl;
 	u_long maddr;
 	int psize;
 	daddr_t blkno;
 	int (*dump)(dev_t, daddr_t, void *, size_t);
 	int error;
 	/* Save registers. */
 	savectx(&dumppcb);
 	if (dumpdev == NODEV)
 		return;
 	bdev = bdevsw_lookup(dumpdev);
 	if (bdev == NULL || bdev->d_psize == NULL)
 		return;
 	/*
 	 * For dumps during autoconfiguration,
 	 * if dump device has already configured...
 	 */
 	if (dumpsize == 0)
 		cpu_dumpconf();
 	if (dumplo <= 0) {
 		printf("\ndump to dev %u,%u not possible\n",
 		    major(dumpdev), minor(dumpdev));
 		return;
+	}
 	printf("\ndumping to dev %u,%u offset %ld\n",
 	    major(dumpdev), minor(dumpdev), dumplo);
 	psize = bdev_size(dumpdev);
 	printf("dump ");
 	if (psize == -1) {
 		printf("area unavailable\n");
 		return;
+	}
 	/* XXX should purge all outstanding keystrokes. */
 	if ((error = cpu_dump()) != 0)
 		goto err;
 	totalbytesleft = ptoa(cpu_dump_mempagecnt());
 	blkno = dumplo + cpu_dumpsize();
 	dump = bdev->d_dump;
 	error = 0;
 	for (memcl = 0; memcl < mem_cluster_cnt; memcl++) {
 		maddr = mem_clusters[memcl].start;
 		bytes = mem_clusters[memcl].size & ~PAGE_MASK;
 		for (i = 0; i < bytes; i += n, totalbytesleft -= n) {
 			/* Print out how many MBs we to go. */
 			if ((totalbytesleft % (1024*1024)) == 0)
 				printf_nolog("%ld ",
 				    totalbytesleft / (1024 * 1024));
 			/* Limit size for next transfer. */
 			n = bytes - i;
 			if (n > BYTES_PER_DUMP)
 				n =  BYTES_PER_DUMP;
 			error = (*dump)(dumpdev, blkno,
 			    (void *)ALPHA_PHYS_TO_K0SEG(maddr), n);
 			if (error)
 				goto err;
 			maddr += n;
 			blkno += btodb(n);			/* XXX? */
 			/* XXX should look for keystrokes, to cancel. */
+		}
+	}
 err:
 	switch (error) {
 	case ENXIO:
 		printf("device bad\n");
 		break;
 	case EFAULT:
 		printf("device not ready\n");
 		break;
 	case EINVAL:
 		printf("area improper\n");
 		break;
 	case EIO:
 		printf("i/o error\n");
 		break;
 	case EINTR:
 		printf("aborted from console\n");
 		break;
 	case 0:
 		printf("succeeded\n");
 		break;
 	default:
 		printf("error %d\n", error);
 		break;
+	}
 	printf("\n\n");
 	delay(1000);
+}
 void
 frametoreg(const struct trapframe *framep, struct reg *regp)
+{
 	regp->r_regs[R_V0] = framep->tf_regs[FRAME_V0];
 	regp->r_regs[R_T0] = framep->tf_regs[FRAME_T0];
 	regp->r_regs[R_T1] = framep->tf_regs[FRAME_T1];
 	regp->r_regs[R_T2] = framep->tf_regs[FRAME_T2];
 	regp->r_regs[R_T3] = framep->tf_regs[FRAME_T3];
 	regp->r_regs[R_T4] = framep->tf_regs[FRAME_T4];
 	regp->r_regs[R_T5] = framep->tf_regs[FRAME_T5];
 	regp->r_regs[R_T6] = framep->tf_regs[FRAME_T6];
 	regp->r_regs[R_T7] = framep->tf_regs[FRAME_T7];
 	regp->r_regs[R_S0] = framep->tf_regs[FRAME_S0];
 	regp->r_regs[R_S1] = framep->tf_regs[FRAME_S1];
 	regp->r_regs[R_S2] = framep->tf_regs[FRAME_S2];
 	regp->r_regs[R_S3] = framep->tf_regs[FRAME_S3];
 	regp->r_regs[R_S4] = framep->tf_regs[FRAME_S4];
 	regp->r_regs[R_S5] = framep->tf_regs[FRAME_S5];
 	regp->r_regs[R_S6] = framep->tf_regs[FRAME_S6];
 	regp->r_regs[R_A0] = framep->tf_regs[FRAME_A0];
 	regp->r_regs[R_A1] = framep->tf_regs[FRAME_A1];
 	regp->r_regs[R_A2] = framep->tf_regs[FRAME_A2];
 	regp->r_regs[R_A3] = framep->tf_regs[FRAME_A3];
 	regp->r_regs[R_A4] = framep->tf_regs[FRAME_A4];
 	regp->r_regs[R_A5] = framep->tf_regs[FRAME_A5];
 	regp->r_regs[R_T8] = framep->tf_regs[FRAME_T8];
 	regp->r_regs[R_T9] = framep->tf_regs[FRAME_T9];
 	regp->r_regs[R_T10] = framep->tf_regs[FRAME_T10];
 	regp->r_regs[R_T11] = framep->tf_regs[FRAME_T11];
 	regp->r_regs[R_RA] = framep->tf_regs[FRAME_RA];
 	regp->r_regs[R_T12] = framep->tf_regs[FRAME_T12];
 	regp->r_regs[R_AT] = framep->tf_regs[FRAME_AT];
 	regp->r_regs[R_GP] = framep->tf_regs[FRAME_GP];
 	/* regp->r_regs[R_SP] = framep->tf_regs[FRAME_SP]; XXX */
 	regp->r_regs[R_ZERO] = 0;
+}
 void
 regtoframe(const struct reg *regp, struct trapframe *framep)
+{
 	framep->tf_regs[FRAME_V0] = regp->r_regs[R_V0];
 	framep->tf_regs[FRAME_T0] = regp->r_regs[R_T0];
 	framep->tf_regs[FRAME_T1] = regp->r_regs[R_T1];
 	framep->tf_regs[FRAME_T2] = regp->r_regs[R_T2];
 	framep->tf_regs[FRAME_T3] = regp->r_regs[R_T3];
 	framep->tf_regs[FRAME_T4] = regp->r_regs[R_T4];
 	framep->tf_regs[FRAME_T5] = regp->r_regs[R_T5];
 	framep->tf_regs[FRAME_T6] = regp->r_regs[R_T6];
 	framep->tf_regs[FRAME_T7] = regp->r_regs[R_T7];
 	framep->tf_regs[FRAME_S0] = regp->r_regs[R_S0];
 	framep->tf_regs[FRAME_S1] = regp->r_regs[R_S1];
 	framep->tf_regs[FRAME_S2] = regp->r_regs[R_S2];
 	framep->tf_regs[FRAME_S3] = regp->r_regs[R_S3];
 	framep->tf_regs[FRAME_S4] = regp->r_regs[R_S4];
 	framep->tf_regs[FRAME_S5] = regp->r_regs[R_S5];
 	framep->tf_regs[FRAME_S6] = regp->r_regs[R_S6];
 	framep->tf_regs[FRAME_A0] = regp->r_regs[R_A0];
 	framep->tf_regs[FRAME_A1] = regp->r_regs[R_A1];
 	framep->tf_regs[FRAME_A2] = regp->r_regs[R_A2];
 	framep->tf_regs[FRAME_A3] = regp->r_regs[R_A3];
 	framep->tf_regs[FRAME_A4] = regp->r_regs[R_A4];
 	framep->tf_regs[FRAME_A5] = regp->r_regs[R_A5];
 	framep->tf_regs[FRAME_T8] = regp->r_regs[R_T8];
 	framep->tf_regs[FRAME_T9] = regp->r_regs[R_T9];
 	framep->tf_regs[FRAME_T10] = regp->r_regs[R_T10];
 	framep->tf_regs[FRAME_T11] = regp->r_regs[R_T11];
 	framep->tf_regs[FRAME_RA] = regp->r_regs[R_RA];
 	framep->tf_regs[FRAME_T12] = regp->r_regs[R_T12];
 	framep->tf_regs[FRAME_AT] = regp->r_regs[R_AT];
 	framep->tf_regs[FRAME_GP] = regp->r_regs[R_GP];
 	/* framep->tf_regs[FRAME_SP] = regp->r_regs[R_SP]; XXX */
 	/* ??? = regp->r_regs[R_ZERO]; */
+}
 void
 printregs(struct reg *regp)
+{
 	int i;
 	for (i = 0; i < 32; i++)
 		printf("R%d:\t0x%016lx%s", i, regp->r_regs[i],
 		   i & 1 ? "\n" : "\t");
+}
 void
 regdump(struct trapframe *framep)
+{
 	struct reg reg;
 	frametoreg(framep, &reg);
 	reg.r_regs[R_SP] = alpha_pal_rdusp();
 	printf("REGISTERS:\n");
 	printregs(&reg);
+}
 void *
 getframe(const struct lwp *l, int sig, int *onstack)
+{
 	void *frame;
 	/* Do we need to jump onto the signal stack? */
 	*onstack =
 	    (l->l_sigstk.ss_flags & (SS_DISABLE | SS_ONSTACK)) == 0 &&
 	    (SIGACTION(l->l_proc, sig).sa_flags & SA_ONSTACK) != 0;
 	if (*onstack)
 		frame = (void *)((char *)l->l_sigstk.ss_sp +
 					l->l_sigstk.ss_size);
 	else
 		frame = (void *)(alpha_pal_rdusp());
 	return (frame);
+}
 void
 buildcontext(struct lwp *l, const void *catcher, const void *tramp, const void *fp)
+{
 	struct trapframe *tf = l->l_md.md_tf;
 	tf->tf_regs[FRAME_RA] = (uint64_t)tramp;
 	tf->tf_regs[FRAME_PC] = (uint64_t)catcher;
 	tf->tf_regs[FRAME_T12] = (uint64_t)catcher;
 	alpha_pal_wrusp((unsigned long)fp);
+}
 /*
  * Send an interrupt to process, new style
  */
 void
 sendsig_siginfo(const ksiginfo_t *ksi, const sigset_t *mask)
+{
 	struct lwp *l = curlwp;
 	struct proc *p = l->l_proc;
 	struct sigacts *ps = p->p_sigacts;
 	int onstack, sig = ksi->ksi_signo, error;
 	struct sigframe_siginfo *fp, frame;
 	struct trapframe *tf;
 	sig_t catcher = SIGACTION(p, ksi->ksi_signo).sa_handler;
 	fp = (struct sigframe_siginfo *)getframe(l,ksi->ksi_signo,&onstack);
 	tf = l->l_md.md_tf;
 	/* Allocate space for the signal handler context. */
 	fp--;
 #ifdef DEBUG
 	if ((sigdebug & SDB_KSTACK) && p->p_pid == sigpid)
 		printf("sendsig_siginfo(%d): sig %d ssp %p usp %p\n", p->p_pid,
 		    sig, &onstack, fp);
 #endif
 	/* Build stack frame for signal trampoline. */
 	memset(&frame, 0, sizeof(frame));
 	frame.sf_si._info = ksi->ksi_info;
 	frame.sf_uc.uc_flags = _UC_SIGMASK;
 	frame.sf_uc.uc_sigmask = *mask;
 	frame.sf_uc.uc_link = l->l_ctxlink;
 	sendsig_reset(l, sig);
 	mutex_exit(p->p_lock);
 	cpu_getmcontext(l, &frame.sf_uc.uc_mcontext, &frame.sf_uc.uc_flags);
 	error = copyout(&frame, fp, sizeof(frame));
 	mutex_enter(p->p_lock);
 	if (error != 0) {
 		/*
 		 * Process has trashed its stack; give it an illegal
 		 * instruction to halt it in its tracks.
 		 */
 #ifdef DEBUG
 		if ((sigdebug & SDB_KSTACK) && p->p_pid == sigpid)
 			printf("sendsig_siginfo(%d): copyout failed on sig %d\n",
 			    p->p_pid, sig);
 #endif
 		sigexit(l, SIGILL);
 		/* NOTREACHED */
+	}
 #ifdef DEBUG
 	if (sigdebug & SDB_FOLLOW)
 		printf("sendsig_siginfo(%d): sig %d usp %p code %x\n",
 		       p->p_pid, sig, fp, ksi->ksi_code);
 #endif
 	/*
 	 * Set up the registers to directly invoke the signal handler.  The
 	 * signal trampoline is then used to return from the signal.  Note
 	 * the trampoline version numbers are coordinated with machine-
 	 * dependent code in libc.
 	 */
 	tf->tf_regs[FRAME_A0] = sig;
 	tf->tf_regs[FRAME_A1] = (uint64_t)&fp->sf_si;
 	tf->tf_regs[FRAME_A2] = (uint64_t)&fp->sf_uc;
 	buildcontext(l,catcher,ps->sa_sigdesc[sig].sd_tramp,fp);
 	/* Remember that we're now on the signal stack. */
 	if (onstack)
 		l->l_sigstk.ss_flags |= SS_ONSTACK;
 #ifdef DEBUG
 	if (sigdebug & SDB_FOLLOW)
 		printf("sendsig_siginfo(%d): pc %lx, catcher %lx\n", p->p_pid,
 		    tf->tf_regs[FRAME_PC], tf->tf_regs[FRAME_A3]);
 	if ((sigdebug & SDB_KSTACK) && p->p_pid == sigpid)
 		printf("sendsig_siginfo(%d): sig %d returns\n",
 		    p->p_pid, sig);
 #endif
+}
 /*
  * machine dependent system variables.
  */
 SYSCTL_SETUP(sysctl_machdep_setup, "sysctl machdep subtree setup")
+{
 	sysctl_createv(clog, 0, NULL, NULL,
 		       CTLFLAG_PERMANENT,
 		       CTLTYPE_NODE, "machdep", NULL,
 		       NULL, 0, NULL, 0,
 		       CTL_MACHDEP, CTL_EOL);
 	sysctl_createv(clog, 0, NULL, NULL,
 		       CTLFLAG_PERMANENT,
 		       CTLTYPE_STRUCT, "console_device", NULL,
 		       sysctl_consdev, 0, NULL, sizeof(dev_t),
 		       CTL_MACHDEP, CPU_CONSDEV, CTL_EOL);
 	sysctl_createv(clog, 0, NULL, NULL,
 		       CTLFLAG_PERMANENT,
 		       CTLTYPE_STRING, "root_device", NULL,
 		       sysctl_root_device, 0, NULL, 0,
 		       CTL_MACHDEP, CPU_ROOT_DEVICE, CTL_EOL);
 	sysctl_createv(clog, 0, NULL, NULL,
 		       CTLFLAG_PERMANENT|CTLFLAG_READWRITE,
 		       CTLTYPE_INT, "unaligned_print",
 		       SYSCTL_DESCR("Warn about unaligned accesses"),
 		       NULL, 0, &alpha_unaligned_print, 0,
 		       CTL_MACHDEP, CPU_UNALIGNED_PRINT, CTL_EOL);
 	sysctl_createv(clog, 0, NULL, NULL,
 		       CTLFLAG_PERMANENT|CTLFLAG_READWRITE,
 		       CTLTYPE_INT, "unaligned_fix",
 		       SYSCTL_DESCR("Fix up unaligned accesses"),
 		       NULL, 0, &alpha_unaligned_fix, 0,
 		       CTL_MACHDEP, CPU_UNALIGNED_FIX, CTL_EOL);
 	sysctl_createv(clog, 0, NULL, NULL,
 		       CTLFLAG_PERMANENT|CTLFLAG_READWRITE,
 		       CTLTYPE_INT, "unaligned_sigbus",
 		       SYSCTL_DESCR("Do SIGBUS for fixed unaligned accesses"),
 		       NULL, 0, &alpha_unaligned_sigbus, 0,
 		       CTL_MACHDEP, CPU_UNALIGNED_SIGBUS, CTL_EOL);
 	sysctl_createv(clog, 0, NULL, NULL,
 		       CTLFLAG_PERMANENT,
 		       CTLTYPE_STRING, "booted_kernel", NULL,
 		       NULL, 0, bootinfo.booted_kernel, 0,
 		       CTL_MACHDEP, CPU_BOOTED_KERNEL, CTL_EOL);
 	sysctl_createv(clog, 0, NULL, NULL,
 		       CTLFLAG_PERMANENT|CTLFLAG_READWRITE,
 		       CTLTYPE_INT, "fp_sync_complete", NULL,
 		       NULL, 0, &alpha_fp_sync_complete, 0,
 		       CTL_MACHDEP, CPU_FP_SYNC_COMPLETE, CTL_EOL);
+}
 /*
  * Set registers on exec.
  */
 void
 setregs(register struct lwp *l, struct exec_package *pack, vaddr_t stack)
+{
 	struct trapframe *tfp = l->l_md.md_tf;
 	struct pcb *pcb;
 #ifdef DEBUG
 	int i;
 #endif
 #ifdef DEBUG
 	/*
 	 * Crash and dump, if the user requested it.
 	 */
 	if (boothowto & RB_DUMP)
 		panic("crash requested by boot flags");
 #endif
 #ifdef DEBUG
 	for (i = 0; i < FRAME_SIZE; i++)
 		tfp->tf_regs[i] = 0xbabefacedeadbeef;
 #else
 	memset(tfp->tf_regs, 0, FRAME_SIZE * sizeof tfp->tf_regs[0]);
 #endif
 	pcb = lwp_getpcb(l);
 	memset(&pcb->pcb_fp, 0, sizeof(pcb->pcb_fp));
 	alpha_pal_wrusp(stack);
 	tfp->tf_regs[FRAME_PS] = ALPHA_PSL_USERSET;
 	tfp->tf_regs[FRAME_PC] = pack->ep_entry & ~3;
 	tfp->tf_regs[FRAME_A0] = stack;			/* a0 = sp */
 	tfp->tf_regs[FRAME_A1] = 0;			/* a1 = rtld cleanup */
 	tfp->tf_regs[FRAME_A2] = 0;			/* a2 = rtld object */
 	tfp->tf_regs[FRAME_A3] = l->l_proc->p_psstrp;	/* a3 = ps_strings */
 	tfp->tf_regs[FRAME_T12] = tfp->tf_regs[FRAME_PC];	/* a.k.a. PV */
 	if (__predict_true((l->l_md.md_flags & IEEE_INHERIT) == 0)) {
 		l->l_md.md_flags &= ~MDLWP_FP_C;
 		pcb->pcb_fp.fpr_cr = FPCR_DYN(FP_RN);
+	}
+}
 /*
  * Wait "n" microseconds.
  */
 void
 delay(unsigned long n)
+{
 	unsigned long pcc0, pcc1, curcycle, cycles, usec;
 	if (n == 0)
 		return;
 	pcc0 = alpha_rpcc() & 0xffffffffUL;
 	cycles = 0;
 	usec = 0;
 	while (usec <= n) {
 		/*
 		 * Get the next CPU cycle count- assumes that we cannot
 		 * have had more than one 32 bit overflow.
 		 */
 		pcc1 = alpha_rpcc() & 0xffffffffUL;
 		if (pcc1 < pcc0)
 			curcycle = (pcc1 + 0x100000000UL) - pcc0;
 		else
 			curcycle = pcc1 - pcc0;
 		/*
 		 * We now have the number of processor cycles since we
 		 * last checked. Add the current cycle count to the
 		 * running total. If it's over cycles_per_usec, increment
 		 * the usec counter.
 		 */
 		cycles += curcycle;
 		while (cycles > cycles_per_usec) {
 			usec++;
 			cycles -= cycles_per_usec;
+		}
 		pcc0 = pcc1;
+	}
+}
 #ifdef EXEC_ECOFF
 void
 cpu_exec_ecoff_setregs(struct lwp *l, struct exec_package *epp, vaddr_t stack)
+{
 	struct ecoff_exechdr *execp = (struct ecoff_exechdr *)epp->ep_hdr;
 	l->l_md.md_tf->tf_regs[FRAME_GP] = execp->a.gp_value;
+}
 /*
  * cpu_exec_ecoff_hook():
  *	cpu-dependent ECOFF format hook for execve().
+ *
  * Do any machine-dependent diddling of the exec package when doing ECOFF.
+ *
  */
 int
 cpu_exec_ecoff_probe(struct lwp *l, struct exec_package *epp)
+{
 	struct ecoff_exechdr *execp = (struct ecoff_exechdr *)epp->ep_hdr;
 	int error;
 	if (execp->f.f_magic == ECOFF_MAGIC_NETBSD_ALPHA)
 		error = 0;
 	else
 		error = ENOEXEC;
 	return (error);
+}
 #endif /* EXEC_ECOFF */
 int
 mm_md_physacc(paddr_t pa, vm_prot_t prot)
+{
 	u_quad_t size;
 	int i;
 	for (i = 0; i < mem_cluster_cnt; i++) {
 		if (pa < mem_clusters[i].start)
 			continue;
 		size = mem_clusters[i].size & ~PAGE_MASK;
 		if (pa >= (mem_clusters[i].start + size))
 			continue;
 		if ((prot & mem_clusters[i].size & PAGE_MASK) == prot)
 			return 0;
+	}
 	return EFAULT;
+}
 bool
 mm_md_direct_mapped_io(void *addr, paddr_t *paddr)
+{
 	vaddr_t va = (vaddr_t)addr;
 	if (va >= ALPHA_K0SEG_BASE && va <= ALPHA_K0SEG_END) {
 		*paddr = ALPHA_K0SEG_TO_PHYS(va);
 		return true;
+	}
 	return false;
+}
 bool
 mm_md_direct_mapped_phys(paddr_t paddr, vaddr_t *vaddr)
+{
 	*vaddr = ALPHA_PHYS_TO_K0SEG(paddr);
 	return true;
+}
 /* XXX XXX BEGIN XXX XXX */
 paddr_t alpha_XXX_dmamap_or;					/* XXX */
 								/* XXX */
 paddr_t								/* XXX */
 alpha_XXX_dmamap(vaddr_t v)					/* XXX */
 {								/* XXX */
 								/* XXX */
 	return (vtophys(v) | alpha_XXX_dmamap_or);		/* XXX */
 }								/* XXX */
 /* XXX XXX END XXX XXX */
 char *
 dot_conv(unsigned long x)
+{
 	int i;
 	char *xc;
 	static int next;
 	static char space[2][20];
 	xc = space[next ^= 1] + sizeof space[0];
 	*--xc = '\0';
 	for (i = 0;; ++i) {
 		if (i && (i & 3) == 0)
 			*--xc = '.';
 		*--xc = hexdigits[x & 0xf];
 		x >>= 4;
 		if (x == 0)
 			break;
+	}
 	return xc;
+}
 void
 cpu_getmcontext(struct lwp *l, mcontext_t *mcp, unsigned int *flags)
+{
 	struct trapframe *frame = l->l_md.md_tf;
 	struct pcb *pcb = lwp_getpcb(l);
 	__greg_t *gr = mcp->__gregs;
 	__greg_t ras_pc;
 	/* Save register context. */
 	frametoreg(frame, (struct reg *)gr);
 	/* XXX if there's a better, general way to get the USP of
 	 * an LWP that might or might not be curlwp, I'd like to know
 	 * about it.
 	 */
 	if (l == curlwp) {
 		gr[_REG_SP] = alpha_pal_rdusp();
 		gr[_REG_UNIQUE] = alpha_pal_rdunique();
 	} else {
 		gr[_REG_SP] = pcb->pcb_hw.apcb_usp;
 		gr[_REG_UNIQUE] = pcb->pcb_hw.apcb_unique;
+	}
 	gr[_REG_PC] = frame->tf_regs[FRAME_PC];
 	gr[_REG_PS] = frame->tf_regs[FRAME_PS];
 	if ((ras_pc = (__greg_t)ras_lookup(l->l_proc,
 	    (void *) gr[_REG_PC])) != -1)
 		gr[_REG_PC] = ras_pc;
 	*flags |= _UC_CPU | _UC_TLSBASE;
 	/* Save floating point register context, if any, and copy it. */
 	if (fpu_valid_p(l)) {
 		fpu_save(l);
 		(void)memcpy(&mcp->__fpregs, &pcb->pcb_fp,
 		    sizeof (mcp->__fpregs));
 		mcp->__fpregs.__fp_fpcr = alpha_read_fp_c(l);
 		*flags |= _UC_FPU;
+	}
+}
 int
 cpu_mcontext_validate(struct lwp *l, const mcontext_t *mcp)
+{
 	const __greg_t *gr = mcp->__gregs;
 	if ((gr[_REG_PS] & ALPHA_PSL_USERSET) != ALPHA_PSL_USERSET ||
 	    (gr[_REG_PS] & ALPHA_PSL_USERCLR) != 0)
 		return EINVAL;
 	return 0;
+}
 int
 cpu_setmcontext(struct lwp *l, const mcontext_t *mcp, unsigned int flags)
+{
 	struct trapframe *frame = l->l_md.md_tf;
 	struct pcb *pcb = lwp_getpcb(l);
 	const __greg_t *gr = mcp->__gregs;
 	int error;
 	/* Restore register context, if any. */
 	if (flags & _UC_CPU) {
 		/* Check for security violations first. */
 		error = cpu_mcontext_validate(l, mcp);
 		if (error)
 			return error;
 		regtoframe((const struct reg *)gr, l->l_md.md_tf);
 		if (l == curlwp)
 			alpha_pal_wrusp(gr[_REG_SP]);
 		else
 			pcb->pcb_hw.apcb_usp = gr[_REG_SP];
 		frame->tf_regs[FRAME_PC] = gr[_REG_PC];
 		frame->tf_regs[FRAME_PS] = gr[_REG_PS];
+	}
 	if (flags & _UC_TLSBASE)
 		lwp_setprivate(l, (void *)(uintptr_t)gr[_REG_UNIQUE]);
 	/* Restore floating point register context, if any. */
 	if (flags & _UC_FPU) {
 		/* If we have an FP register context, get rid of it. */
 		fpu_discard(l, true);
 		(void)memcpy(&pcb->pcb_fp, &mcp->__fpregs,
 		    sizeof (pcb->pcb_fp));
 		l->l_md.md_flags = mcp->__fpregs.__fp_fpcr & MDLWP_FP_C;
+	}
 	return (0);
+}
 static void
 cpu_kick(struct cpu_info * const ci)
+{
 #if defined(MULTIPROCESSOR)
 	alpha_send_ipi(ci->ci_cpuid, ALPHA_IPI_AST);
 #endif /* MULTIPROCESSOR */
+}
 /*
  * Preempt the current process if in interrupt from user mode,
  * or after the current trap/syscall if in system mode.
  */
 void
 cpu_need_resched(struct cpu_info *ci, struct lwp *l, int flags)
+{
 	KASSERT(kpreempt_disabled());
 	if ((flags & RESCHED_IDLE) != 0) {
 		/*
 		 * Nothing to do here; we are not currently using WTINT
 		 * in cpu_idle().
 		 */
 		return;
+	}
 	/* XXX RESCHED_KPREEMPT XXX */
 	KASSERT((flags & RESCHED_UPREEMPT) != 0);
 	if ((flags & RESCHED_REMOTE) != 0) {
 		cpu_kick(ci);
 	} else {
 		aston(l);
+	}
+}
 /*
  * Notify the current lwp (l) that it has a signal pending,
  * process as soon as possible.
  */
 void
 cpu_signotify(struct lwp *l)
+{
 	KASSERT(kpreempt_disabled());
 	if (l->l_cpu != curcpu()) {
 		cpu_kick(l->l_cpu);
 	} else {
 		aston(l);
+	}
+}
 /*
  * Give a profiling tick to the current process when the user profiling
  * buffer pages are invalid.  On the alpha, request an AST to send us
  * through trap, marking the proc as needing a profiling tick.
  */
 void
 cpu_need_proftick(struct lwp *l)
+{
 	KASSERT(kpreempt_disabled());
 	KASSERT(l->l_cpu == curcpu());
 	l->l_pflag |= LP_OWEUPC;
 	aston(l);
+}

 @@ -1,2402 +1,2372 @@
-/* $NetBSD: pmap.c,v 1.270 2020/09/03 02:05:03 thorpej Exp $ */
+/* $NetBSD: pmap.c,v 1.271 2020/09/03 02:09:09 thorpej Exp $ */
 /*-
  * Copyright (c) 1998, 1999, 2000, 2001, 2007, 2008, 2020
  * 	The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
  * NASA Ames Research Center, by Andrew Doran and Mindaugas Rasiukevicius,
  * and by Chris G. Demetriou.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Copyright (c) 1991, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This code is derived from software contributed to Berkeley by
  * the Systems Programming Group of the University of Utah Computer
  * Science Department.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)pmap.c	8.6 (Berkeley) 5/27/94
  */
 /*
  * DEC Alpha physical map management code.
+ *
  * History:
+ *
  *	This pmap started life as a Motorola 68851/68030 pmap,
  *	written by Mike Hibler at the University of Utah.
+ *
  *	It was modified for the DEC Alpha by Chris Demetriou
  *	at Carnegie Mellon University.
+ *
  *	Support for non-contiguous physical memory was added by
  *	Jason R. Thorpe of the Numerical Aerospace Simulation
  *	Facility, NASA Ames Research Center and Chris Demetriou.
+ *
  *	Page table management and a major cleanup were undertaken
  *	by Jason R. Thorpe, with lots of help from Ross Harvey of
  *	Avalon Computer Systems and from Chris Demetriou.
+ *
  *	Support for the new UVM pmap interface was written by
  *	Jason R. Thorpe.
+ *
  *	Support for ASNs was written by Jason R. Thorpe, again
  *	with help from Chris Demetriou and Ross Harvey.
+ *
  *	The locking protocol was written by Jason R. Thorpe,
  *	using Chuck Cranor's i386 pmap for UVM as a model.
+ *
  *	TLB shootdown code was written (and then subsequently
  *	rewritten some years later, borrowing some ideas from
  *	the x86 pmap) by Jason R. Thorpe.
+ *
  *	Multiprocessor modifications by Andrew Doran and
  *	Jason R. Thorpe.
+ *
  * Notes:
+ *
  *	All user page table access is done via K0SEG.  Kernel
  *	page table access is done via the recursive Virtual Page
  *	Table becase kernel PT pages are pre-allocated and never
  *	freed, so no VPT fault handling is requiried.
  */
 /*
  *	Manages physical address maps.
+ *
  *	Since the information managed by this module is
  *	also stored by the logical address mapping module,
  *	this module may throw away valid virtual-to-physical
  *	mappings at almost any time.  However, invalidations
  *	of virtual-to-physical mappings must be done as
  *	requested.
+ *
  *	In order to cope with hardware architectures which
  *	make virtual-to-physical map invalidates expensive,
  *	this module may delay invalidate or reduced protection
  *	operations until such time as they are actually
  *	necessary.  This module is given full information as
  *	to which processors are currently using which maps,
  *	and to when physical maps must be made correct.
  */
 #include "opt_lockdebug.h"
 #include "opt_sysv.h"
 #include "opt_multiprocessor.h"
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.270 2020/09/03 02:05:03 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.271 2020/09/03 02:09:09 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/proc.h>
 #include <sys/malloc.h>
 #include <sys/pool.h>
 #include <sys/buf.h>
 #include <sys/evcnt.h>
 #include <sys/atomic.h>
 #include <sys/cpu.h>
 #include <uvm/uvm.h>
-#if defined(_PMAP_MAY_USE_PROM_CONSOLE) || defined(MULTIPROCESSOR)
+#if defined(MULTIPROCESSOR)
 #include <machine/rpb.h>
 #endif
 #ifdef DEBUG
 #define	PDB_FOLLOW	0x0001
 #define	PDB_INIT	0x0002
 #define	PDB_ENTER	0x0004
 #define	PDB_REMOVE	0x0008
 #define	PDB_CREATE	0x0010
 #define	PDB_PTPAGE	0x0020
 #define	PDB_ASN		0x0040
 #define	PDB_BITS	0x0080
 #define	PDB_COLLECT	0x0100
 #define	PDB_PROTECT	0x0200
 #define	PDB_BOOTSTRAP	0x1000
 #define	PDB_PARANOIA	0x2000
 #define	PDB_WIRING	0x4000
 #define	PDB_PVDUMP	0x8000
 int debugmap = 0;
 int pmapdebug = PDB_PARANOIA;
 #endif
 #if defined(MULTIPROCESSOR)
 #define	PMAP_MP(x)	x
 #else
 #define	PMAP_MP(x)	__nothing
 #endif /* MULTIPROCESSOR */
 /*
  * Given a map and a machine independent protection code,
  * convert to an alpha protection code.
  */
 #define pte_prot(m, p)	(protection_codes[m == pmap_kernel() ? 0 : 1][p])
 static int	protection_codes[2][8] __read_mostly;
 /*
  * kernel_lev1map:
+ *
  *	Kernel level 1 page table.  This maps all kernel level 2
  *	page table pages, and is used as a template for all user
  *	pmap level 1 page tables.  When a new user level 1 page
  *	table is allocated, all kernel_lev1map PTEs for kernel
  *	addresses are copied to the new map.
+ *
  *	The kernel also has an initial set of kernel level 2 page
  *	table pages.  These map the kernel level 3 page table pages.
  *	As kernel level 3 page table pages are added, more level 2
  *	page table pages may be added to map them.  These pages are
  *	never freed.
+ *
  *	Finally, the kernel also has an initial set of kernel level
  *	3 page table pages.  These map pages in K1SEG.  More level
  *	3 page table pages may be added at run-time if additional
  *	K1SEG address space is required.  These pages are never freed.
+ *
  * NOTE: When mappings are inserted into the kernel pmap, all
  * level 2 and level 3 page table pages must already be allocated
  * and mapped into the parent page table.
  */
 pt_entry_t	*kernel_lev1map __read_mostly;
 /*
  * Virtual Page Table.
  */
 static pt_entry_t *VPT __read_mostly;
 static struct {
 	struct pmap k_pmap;
 } kernel_pmap_store __cacheline_aligned;
 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store.k_pmap;
 /* PA of first available physical page */
 paddr_t    	avail_start __read_mostly;
 /* PA of last available physical page */
 paddr_t		avail_end __read_mostly;
 /* VA of last avail page (end of kernel AS) */
 static vaddr_t	virtual_end __read_mostly;
 /* Has pmap_init completed? */
 static bool pmap_initialized __read_mostly;
 /* Instrumentation */
 u_long		pmap_pages_stolen __read_mostly;
 /*
  * This variable contains the number of CPU IDs we need to allocate
  * space for when allocating the pmap structure.  It is used to
  * size a per-CPU array of ASN and ASN Generation number.
  */
 static u_long 	pmap_ncpuids __read_mostly;
 #ifndef PMAP_PV_LOWAT
 #define	PMAP_PV_LOWAT	16
 #endif
 int		pmap_pv_lowat __read_mostly = PMAP_PV_LOWAT;
 /*
  * List of all pmaps, used to update them when e.g. additional kernel
  * page tables are allocated.  This list is kept LRU-ordered by
  * pmap_activate().
  */
 static TAILQ_HEAD(, pmap) pmap_all_pmaps __cacheline_aligned;
 /*
  * The pools from which pmap structures and sub-structures are allocated.
  */
 static struct pool_cache pmap_pmap_cache __read_mostly;
 static struct pool_cache pmap_l1pt_cache __read_mostly;
 static struct pool_cache pmap_pv_cache __read_mostly;
 CTASSERT(offsetof(struct pmap, pm_asni[0]) == COHERENCY_UNIT);
 CTASSERT(PMAP_SIZEOF(ALPHA_MAXPROCS) < ALPHA_PGBYTES);
 CTASSERT(sizeof(struct pmap_asn_info) == COHERENCY_UNIT);
 /*
  * Address Space Numbers.
+ *
  * On many implementations of the Alpha architecture, the TLB entries and
  * I-cache blocks are tagged with a unique number within an implementation-
  * specified range.  When a process context becomes active, the ASN is used
  * to match TLB entries; if a TLB entry for a particular VA does not match
  * the current ASN, it is ignored (one could think of the processor as
  * having a collection of <max ASN> separate TLBs).  This allows operating
  * system software to skip the TLB flush that would otherwise be necessary
  * at context switch time.
+ *
  * Alpha PTEs have a bit in them (PG_ASM - Address Space Match) that
  * causes TLB entries to match any ASN.  The PALcode also provides
  * a TBI (Translation Buffer Invalidate) operation that flushes all
  * TLB entries that _do not_ have PG_ASM.  We use this bit for kernel
  * mappings, so that invalidation of all user mappings does not invalidate
  * kernel mappings (which are consistent across all processes).
+ *
  * pmap_next_asn always indicates to the next ASN to use.  When
  * pmap_next_asn exceeds pmap_max_asn, we start a new ASN generation.
+ *
  * When a new ASN generation is created, the per-process (i.e. non-PG_ASM)
  * TLB entries and the I-cache are flushed, the generation number is bumped,
  * and pmap_next_asn is changed to indicate the first non-reserved ASN.
+ *
  * We reserve ASN #0 for pmaps that use the global kernel_lev1map.  This
  * prevents the following scenario to ensure no accidental accesses to
  * user space for LWPs using the kernel pmap.  This is important because
  * the PALcode may use the recursive VPT to service TLB misses.
+ *
  * By reserving an ASN for the kernel, we are guaranteeing that an lwp
  * will not see any valid user space TLB entries until it passes through
  * pmap_activate() for the first time.
+ *
  * On processors that do not support ASNs, the PALcode invalidates
  * non-ASM TLB entries automatically on swpctx.  We completely skip
  * the ASN machinery in this case because the PALcode neither reads
  * nor writes that field of the HWPCB.
  */
 /* max ASN supported by the system */
 static u_int	pmap_max_asn __read_mostly;
 /*
  * Locking:
+ *
  *	READ/WRITE LOCKS
  *	----------------
+ *
  *	* pmap_main_lock - This lock is used to prevent deadlock and/or
  *	  provide mutex access to the pmap module.  Most operations lock
  *	  the pmap first, then PV lists as needed.  However, some operations,
  *	  such as pmap_page_protect(), lock the PV lists before locking
  *	  the pmaps.  To prevent deadlock, we require a mutex lock on the
  *	  pmap module if locking in the PV->pmap direction.  This is
  *	  implemented by acquiring a (shared) read lock on pmap_main_lock
  *	  if locking pmap->PV and a (exclusive) write lock if locking in
  *	  the PV->pmap direction.  Since only one thread can hold a write
  *	  lock at a time, this provides the mutex.
+ *
  *	MUTEXES
  *	-------
+ *
  *	* pmap lock (global hash) - These locks protect the pmap structures.
+ *
  *	* pmap activation lock (global hash) - These IPL_SCHED spin locks
  *	  synchronize pmap_activate() and TLB shootdowns.  This has a lock
  *	  ordering constraint with the tlb_lock:
+ *
  *		tlb_lock -> pmap activation lock
+ *
  *	* pvh_lock (global hash) - These locks protect the PV lists for
  *	  managed pages.
+ *
  *	* tlb_lock - This IPL_VM lock serializes local and remote TLB
  *	  invalidation.
+ *
  *	* pmap_all_pmaps_lock - This lock protects the global list of
  *	  all pmaps.
+ *
  *	* pmap_growkernel_lock - This lock protects pmap_growkernel()
  *	  and the virtual_end variable.
+ *
  *	  There is a lock ordering constraint for pmap_growkernel_lock.
  *	  pmap_growkernel() acquires the locks in the following order:
+ *
  *		pmap_growkernel_lock (write) -> pmap_all_pmaps_lock ->
  *		    pmap lock
+ *
  *	  We need to ensure consistency between user pmaps and the
  *	  kernel_lev1map.  For this reason, pmap_growkernel_lock must
  *	  be held to prevent kernel_lev1map changing across pmaps
  *	  being added to / removed from the global pmaps list.
+ *
  *	Address space number management (global ASN counters and per-pmap
  *	ASN state) are not locked; they use arrays of values indexed
  *	per-processor.
+ *
  *	All internal functions which operate on a pmap are called
  *	with the pmap already locked by the caller (which will be
  *	an interface function).
  */
 static krwlock_t pmap_main_lock __cacheline_aligned;
 static kmutex_t pmap_all_pmaps_lock __cacheline_aligned;
 static krwlock_t pmap_growkernel_lock __cacheline_aligned;
 #define	PMAP_MAP_TO_HEAD_LOCK()		rw_enter(&pmap_main_lock, RW_READER)
 #define	PMAP_MAP_TO_HEAD_UNLOCK()	rw_exit(&pmap_main_lock)
 #define	PMAP_HEAD_TO_MAP_LOCK()		rw_enter(&pmap_main_lock, RW_WRITER)
 #define	PMAP_HEAD_TO_MAP_UNLOCK()	rw_exit(&pmap_main_lock)
 static union {
 	kmutex_t	lock;
 	uint8_t		pad[COHERENCY_UNIT];
 } pmap_pvh_locks[64] __cacheline_aligned;
 #define	PVH_LOCK_HASH(pg)						\
 	((((uintptr_t)(pg)) >> 6) & 63)
 static inline kmutex_t *
 pmap_pvh_lock(struct vm_page *pg)
+{
 	return &pmap_pvh_locks[PVH_LOCK_HASH(pg)].lock;
+}
 static union {
 	struct {
 		kmutex_t	lock;
 		kmutex_t	activation_lock;
 	} locks;
 	uint8_t		pad[COHERENCY_UNIT];
 } pmap_pmap_locks[64] __cacheline_aligned;
 #define	PMAP_LOCK_HASH(pm)						\
 	((((uintptr_t)(pm)) >> 6) & 63)
 static inline kmutex_t *
 pmap_pmap_lock(pmap_t const pmap)
+{
 	return &pmap_pmap_locks[PMAP_LOCK_HASH(pmap)].locks.lock;
+}
 static inline kmutex_t *
 pmap_activation_lock(pmap_t const pmap)
+{
 	return &pmap_pmap_locks[PMAP_LOCK_HASH(pmap)].locks.activation_lock;
+}
 #define	PMAP_LOCK(pmap)		mutex_enter(pmap_pmap_lock(pmap))
 #define	PMAP_UNLOCK(pmap)	mutex_exit(pmap_pmap_lock(pmap))
 #define	PMAP_ACT_LOCK(pmap)	mutex_spin_enter(pmap_activation_lock(pmap))
 #define	PMAP_ACT_TRYLOCK(pmap)	mutex_tryenter(pmap_activation_lock(pmap))
 #define	PMAP_ACT_UNLOCK(pmap)	mutex_spin_exit(pmap_activation_lock(pmap))
 #if defined(MULTIPROCESSOR)
 #define	pmap_all_cpus()		cpus_running
 #else
 #define	pmap_all_cpus()		~0UL
 #endif /* MULTIPROCESSOR */
 /*
  * TLB management.
+ *
  * TLB invalidations need to be performed on local and remote CPUs
  * whenever parts of the PTE that the hardware or PALcode understands
  * changes.  In order amortize the cost of these operations, we will
  * queue up to 8 addresses to invalidate in a batch.  Any more than
  * that, and we will hit the entire TLB.
  * Some things that add complexity:
+ *
  * ==> ASNs. A CPU may have valid TLB entries for other than the current
  *     address spaace.  We can only invalidate TLB entries for the current
  *     address space, so when asked to invalidate a VA for the non-current
  *     pmap on a given CPU, we simply invalidate the ASN for that pmap,CPU
  *     tuple so that new one is allocated on the next activation on that
  *     CPU.  N.B. that for CPUs that don't implement ASNs, SWPCTX does all
  *     the work necessary, so we can skip some work in the pmap module
  *     itself.
+ *
  *     When a pmap is activated on a given CPU, we set a corresponding
  *     bit in pmap::pm_cpus, indicating that it potentially has valid
  *     TLB entries for that address space.  This bitmap is then used to
  *     determine which remote CPUs need to be notified of invalidations.
  *     The bit is cleared when the ASN is invalidated on that CPU.
+ *
  *     In order to serialize with activating an address space on a
  *     given CPU (that we can reliably send notifications only to
  *     relevant remote CPUs), we acquire the pmap lock in pmap_activate()
  *     and also hold the lock while remote shootdowns take place.
  *     This does not apply to the kernel pmap; all CPUs are notified about
  *     invalidations for the kernel pmap, and the pmap lock is not held
  *     in pmap_activate() for the kernel pmap.
+ *
  * ==> P->V operations (e.g. pmap_page_protect()) may require sending
  *     invalidations for multiple address spaces.  We only track one
  *     address space at a time, and if we encounter more than one, then
  *     the notification each CPU gets is to hit the entire TLB.  Note
  *     also that we can't serialize with pmap_activate() in this case,
  *     so all CPUs will get the notification, and they check when
  *     processing the notification if the pmap is current on that CPU.
+ *
  * Invalidation information is gathered into a pmap_tlb_context structure
  * that includes room for 8 VAs, the pmap the VAs belong to, a bitmap of
  * CPUs to be notified, and a list for PT pages that are freed during
  * removal off mappings.  The number of valid addresses in the list as
  * well as flags are sqeezed into the lower bits of the first two VAs.
  * Storage for this structure is allocated on the stack.  We need to be
  * careful to keep the size of this struture under control.
+ *
  * When notifying remote CPUs, we acquire the tlb_lock (which also
  * blocks IPIs), record the pointer to our context structure, set a
  * global bitmap off CPUs to be notified, and then send the IPIs to
  * each victim.  While the other CPUs are in-flight, we then perform
  * any invalidations necessary on the local CPU.  Once that is done,
  * we then wait the the global context pointer to be cleared, which
  * will be done by the final remote CPU to complete their work. This
  * method reduces cache line contention during pocessing.
+ *
  * When removing mappings in user pmaps, this implemention frees page
  * table pages back to the VM system once they contain no valid mappings.
  * As we do this, we must ensure to invalidate TLB entries that the
  * CPU might hold for the respective recursive VPT mappings.  This must
  * be done whenever an L1 or L2 PTE is invalidated.  Until these VPT
  * translations are invalidated, the PT pages must not be reused.  For
  * this reason, we keep a list of freed PT pages in the context stucture
  * and drain them off once all invalidations are complete.
+ *
  * NOTE: The value of TLB_CTX_MAXVA is tuned to accommodate the UBC
  * window size (defined as 64KB on alpha in <machine/vmparam.h>).
  */
 #define	TLB_CTX_MAXVA		8
 #define	TLB_CTX_ALLVA		PAGE_MASK
 #define	TLB_CTX_F_ASM		__BIT(0)
 #define	TLB_CTX_F_IMB		__BIT(1)
 #define	TLB_CTX_F_KIMB		__BIT(2)
 #define	TLB_CTX_F_PV		__BIT(3)
 #define	TLB_CTX_F_MULTI		__BIT(4)
 #define	TLB_CTX_COUNT(ctx)	((ctx)->t_addrdata[0] & PAGE_MASK)
 #define	TLB_CTX_INC_COUNT(ctx)	 (ctx)->t_addrdata[0]++
 #define	TLB_CTX_SET_ALLVA(ctx)	 (ctx)->t_addrdata[0] |= TLB_CTX_ALLVA
 #define	TLB_CTX_FLAGS(ctx)	((ctx)->t_addrdata[1] & PAGE_MASK)
 #define	TLB_CTX_SET_FLAG(ctx, f) (ctx)->t_addrdata[1] |= (f)
 #define	TLB_CTX_VA(ctx, i)	((ctx)->t_addrdata[(i)] & ~PAGE_MASK)
 #define	TLB_CTX_SETVA(ctx, i, va)					\
 	(ctx)->t_addrdata[(i)] = (va) | ((ctx)->t_addrdata[(i)] & PAGE_MASK)
 struct pmap_tlb_context {
 	uintptr_t	t_addrdata[TLB_CTX_MAXVA];
 	pmap_t		t_pmap;
 	LIST_HEAD(, vm_page) t_freeptq;
 };
 static struct {
 	kmutex_t	lock;
 	struct evcnt	events;
 } tlb_shootdown __cacheline_aligned;
 #define	tlb_lock	tlb_shootdown.lock
 #define	tlb_evcnt	tlb_shootdown.events
 #if defined(MULTIPROCESSOR)
 static const struct pmap_tlb_context *tlb_context __cacheline_aligned;
 static unsigned long tlb_pending __cacheline_aligned;
 #endif /* MULTIPROCESSOR */
 #if defined(TLB_STATS)
 #define	TLB_COUNT_DECL(cnt)	static struct evcnt tlb_stat_##cnt
 #define	TLB_COUNT(cnt)		atomic_inc_64(&tlb_stat_##cnt .ev_count)
 #define	TLB_COUNT_ATTACH(cnt)						\
 	evcnt_attach_dynamic_nozero(&tlb_stat_##cnt, EVCNT_TYPE_MISC,	\
 	    NULL, "TLB", #cnt)
 TLB_COUNT_DECL(invalidate_multi_tbia);
 TLB_COUNT_DECL(invalidate_multi_tbiap);
 TLB_COUNT_DECL(invalidate_multi_imb);
 TLB_COUNT_DECL(invalidate_kern_tbia);
 TLB_COUNT_DECL(invalidate_kern_tbis);
 TLB_COUNT_DECL(invalidate_kern_imb);
 TLB_COUNT_DECL(invalidate_user_not_current);
 TLB_COUNT_DECL(invalidate_user_lazy_imb);
 TLB_COUNT_DECL(invalidate_user_tbiap);
 TLB_COUNT_DECL(invalidate_user_tbis);
 TLB_COUNT_DECL(shootdown_kernel);
 TLB_COUNT_DECL(shootdown_user);
 TLB_COUNT_DECL(shootdown_imb);
 TLB_COUNT_DECL(shootdown_kimb);
 TLB_COUNT_DECL(shootdown_overflow);
 TLB_COUNT_DECL(shootdown_all_user);
 TLB_COUNT_DECL(shootdown_all_user_imb);
 TLB_COUNT_DECL(shootdown_pv);
 TLB_COUNT_DECL(shootdown_pv_multi);
 TLB_COUNT_DECL(shootnow_over_notify);
 TLB_COUNT_DECL(shootnow_remote);
 TLB_COUNT_DECL(reason_remove_kernel);
 TLB_COUNT_DECL(reason_remove_user);
 TLB_COUNT_DECL(reason_page_protect_read);
 TLB_COUNT_DECL(reason_page_protect_none);
 TLB_COUNT_DECL(reason_protect);
 TLB_COUNT_DECL(reason_enter_kernel);
 TLB_COUNT_DECL(reason_enter_user);
 TLB_COUNT_DECL(reason_kenter);
 TLB_COUNT_DECL(reason_enter_l2pt_delref);
 TLB_COUNT_DECL(reason_enter_l3pt_delref);
 TLB_COUNT_DECL(reason_kremove);
 TLB_COUNT_DECL(reason_clear_modify);
 TLB_COUNT_DECL(reason_clear_reference);
 TLB_COUNT_DECL(reason_emulate_reference);
 TLB_COUNT_DECL(asn_reuse);
 TLB_COUNT_DECL(asn_newgen);
 TLB_COUNT_DECL(asn_assign);
 TLB_COUNT_DECL(activate_both_change);
 TLB_COUNT_DECL(activate_asn_change);
 TLB_COUNT_DECL(activate_ptbr_change);
 TLB_COUNT_DECL(activate_swpctx);
 TLB_COUNT_DECL(activate_skip_swpctx);
 #else /* ! TLB_STATS */
 #define	TLB_COUNT(cnt)		__nothing
 #define	TLB_COUNT_ATTACH(cnt)	__nothing
 #endif /* TLB_STATS */
 static void
 pmap_tlb_init(void)
+{
 	/* mutex is initialized in pmap_bootstrap(). */
 	evcnt_attach_dynamic_nozero(&tlb_evcnt, EVCNT_TYPE_MISC,
 	    NULL, "TLB", "shootdown");
 	TLB_COUNT_ATTACH(invalidate_multi_tbia);
 	TLB_COUNT_ATTACH(invalidate_multi_tbiap);
 	TLB_COUNT_ATTACH(invalidate_multi_imb);
 	TLB_COUNT_ATTACH(invalidate_kern_tbia);
 	TLB_COUNT_ATTACH(invalidate_kern_tbis);
 	TLB_COUNT_ATTACH(invalidate_kern_imb);
 	TLB_COUNT_ATTACH(invalidate_user_not_current);
 	TLB_COUNT_ATTACH(invalidate_user_lazy_imb);
 	TLB_COUNT_ATTACH(invalidate_user_tbiap);
 	TLB_COUNT_ATTACH(invalidate_user_tbis);
 	TLB_COUNT_ATTACH(shootdown_kernel);
 	TLB_COUNT_ATTACH(shootdown_user);
 	TLB_COUNT_ATTACH(shootdown_imb);
 	TLB_COUNT_ATTACH(shootdown_kimb);
 	TLB_COUNT_ATTACH(shootdown_overflow);
 	TLB_COUNT_ATTACH(shootdown_all_user);
 	TLB_COUNT_ATTACH(shootdown_all_user_imb);
 	TLB_COUNT_ATTACH(shootdown_pv);
 	TLB_COUNT_ATTACH(shootdown_pv_multi);
 	TLB_COUNT_ATTACH(shootnow_over_notify);
 	TLB_COUNT_ATTACH(shootnow_remote);
 	TLB_COUNT_ATTACH(reason_remove_kernel);
 	TLB_COUNT_ATTACH(reason_remove_user);
 	TLB_COUNT_ATTACH(reason_page_protect_read);
 	TLB_COUNT_ATTACH(reason_page_protect_none);
 	TLB_COUNT_ATTACH(reason_protect);
 	TLB_COUNT_ATTACH(reason_enter_kernel);
 	TLB_COUNT_ATTACH(reason_enter_user);
 	TLB_COUNT_ATTACH(reason_kenter);
 	TLB_COUNT_ATTACH(reason_enter_l2pt_delref);
 	TLB_COUNT_ATTACH(reason_enter_l3pt_delref);
 	TLB_COUNT_ATTACH(reason_kremove);
 	TLB_COUNT_ATTACH(reason_clear_modify);
 	TLB_COUNT_ATTACH(reason_clear_reference);
 	TLB_COUNT_ATTACH(asn_reuse);
 	TLB_COUNT_ATTACH(asn_newgen);
 	TLB_COUNT_ATTACH(asn_assign);
 	TLB_COUNT_ATTACH(activate_both_change);
 	TLB_COUNT_ATTACH(activate_asn_change);
 	TLB_COUNT_ATTACH(activate_ptbr_change);
 	TLB_COUNT_ATTACH(activate_swpctx);
 	TLB_COUNT_ATTACH(activate_skip_swpctx);
+}
 static inline void
 pmap_tlb_context_init(struct pmap_tlb_context * const tlbctx)
+{
 	/* Initialize the minimum number of fields. */
 	tlbctx->t_addrdata[0] = 0;
 	tlbctx->t_addrdata[1] = 0;
 	tlbctx->t_pmap = NULL;
 	LIST_INIT(&tlbctx->t_freeptq);
+}
 static void
 pmap_tlb_shootdown(pmap_t const pmap, vaddr_t const va,
     pt_entry_t const pte_bits, struct pmap_tlb_context * const tlbctx)
+{
 	KASSERT(pmap != NULL);
 	KASSERT((va & PAGE_MASK) == 0);
 	/*
 	 * Figure out who needs to hear about this, and the scope
 	 * of an all-entries invalidate.
 	 */
 	if (pmap == pmap_kernel()) {
 		TLB_COUNT(shootdown_kernel);
 		KASSERT(pte_bits & PG_ASM);
 		TLB_CTX_SET_FLAG(tlbctx, TLB_CTX_F_ASM);
 		/* Note if an I-stream sync is also needed. */
 		if (pte_bits & PG_EXEC) {
 			TLB_COUNT(shootdown_kimb);
 			TLB_CTX_SET_FLAG(tlbctx, TLB_CTX_F_KIMB);
+		}
 	} else {
 		TLB_COUNT(shootdown_user);
 		KASSERT((pte_bits & PG_ASM) == 0);
 		/* Note if an I-stream sync is also needed. */
 		if (pte_bits & PG_EXEC) {
 			TLB_COUNT(shootdown_imb);
 			TLB_CTX_SET_FLAG(tlbctx, TLB_CTX_F_IMB);
+		}
+	}
 	KASSERT(tlbctx->t_pmap == NULL || tlbctx->t_pmap == pmap);
 	tlbctx->t_pmap = pmap;
 	/*
 	 * If we're already at the max, just tell each active CPU
 	 * to nail everything.
 	 */
 	const uintptr_t count = TLB_CTX_COUNT(tlbctx);
 	if (count > TLB_CTX_MAXVA) {
 		return;
+	}
 	if (count == TLB_CTX_MAXVA) {
 		TLB_COUNT(shootdown_overflow);
 		TLB_CTX_SET_ALLVA(tlbctx);
 		return;
+	}
 	TLB_CTX_SETVA(tlbctx, count, va);
 	TLB_CTX_INC_COUNT(tlbctx);
+}
 static void
 pmap_tlb_shootdown_all_user(pmap_t const pmap, pt_entry_t const pte_bits,
     struct pmap_tlb_context * const tlbctx)
+{
 	KASSERT(pmap != pmap_kernel());
 	TLB_COUNT(shootdown_all_user);
 	/* Note if an I-stream sync is also needed. */
 	if (pte_bits & PG_EXEC) {
 		TLB_COUNT(shootdown_all_user_imb);
 		TLB_CTX_SET_FLAG(tlbctx, TLB_CTX_F_IMB);
+	}
 	TLB_CTX_SET_ALLVA(tlbctx);
+}
 static void
 pmap_tlb_shootdown_pv(const pv_entry_t pv, pt_entry_t const pte_bits,
     struct pmap_tlb_context * const tlbctx)
+{
 	uintptr_t flags = TLB_CTX_F_PV;
 	TLB_COUNT(shootdown_pv);
 	if (tlbctx->t_pmap == NULL || tlbctx->t_pmap == pv->pv_pmap) {
 		if (tlbctx->t_pmap == NULL) {
 			pmap_reference(pv->pv_pmap);
+		}
 		pmap_tlb_shootdown(pv->pv_pmap, pv->pv_va, pte_bits, tlbctx);
 	} else {
 		TLB_COUNT(shootdown_pv_multi);
 		flags |= TLB_CTX_F_MULTI;
 		if (pv->pv_pmap == pmap_kernel()) {
 			KASSERT(pte_bits & PG_ASM);
 			flags |= TLB_CTX_F_ASM;
 		} else {
 			KASSERT((pte_bits & PG_ASM) == 0);
+		}
 		/*
 		 * No need to distinguish between kernel and user IMB
 		 * here; see pmap_tlb_invalidate_multi().
 		 */
 		if (pte_bits & PG_EXEC) {
 			flags |= TLB_CTX_F_IMB;
+		}
 		TLB_CTX_SET_ALLVA(tlbctx);
+	}
 	TLB_CTX_SET_FLAG(tlbctx, flags);
+}
 static void
 pmap_tlb_invalidate_multi(const struct pmap_tlb_context * const tlbctx)
+{
 	if (TLB_CTX_FLAGS(tlbctx) & TLB_CTX_F_ASM) {
 		TLB_COUNT(invalidate_multi_tbia);
 		ALPHA_TBIA();
 	} else {
 		TLB_COUNT(invalidate_multi_tbiap);
 		ALPHA_TBIAP();
+	}
 	if (TLB_CTX_FLAGS(tlbctx) & (TLB_CTX_F_IMB | TLB_CTX_F_KIMB)) {
 		TLB_COUNT(invalidate_multi_imb);
 		alpha_pal_imb();
+	}
+}
 static void
 pmap_tlb_invalidate_kernel(const struct pmap_tlb_context * const tlbctx)
+{
 	const uintptr_t count = TLB_CTX_COUNT(tlbctx);
 	if (count == TLB_CTX_ALLVA) {
 		TLB_COUNT(invalidate_kern_tbia);
 		ALPHA_TBIA();
 	} else {
 		TLB_COUNT(invalidate_kern_tbis);
 		for (uintptr_t i = 0; i < count; i++) {
 			ALPHA_TBIS(TLB_CTX_VA(tlbctx, i));
+		}
+	}
 	if (TLB_CTX_FLAGS(tlbctx) & TLB_CTX_F_KIMB) {
 		TLB_COUNT(invalidate_kern_imb);
 		alpha_pal_imb();
+	}
+}
 static void
 pmap_tlb_invalidate(const struct pmap_tlb_context * const tlbctx,
     const struct cpu_info * const ci)
+{
 	const uintptr_t count = TLB_CTX_COUNT(tlbctx);
 	if (TLB_CTX_FLAGS(tlbctx) & TLB_CTX_F_MULTI) {
 		pmap_tlb_invalidate_multi(tlbctx);
 		return;
+	}
 	if (TLB_CTX_FLAGS(tlbctx) & TLB_CTX_F_ASM) {
 		pmap_tlb_invalidate_kernel(tlbctx);
 		return;
+	}
 	KASSERT(kpreempt_disabled());
 	pmap_t const pmap = tlbctx->t_pmap;
 	KASSERT(pmap != NULL);
 	const u_long cpu_mask = 1UL << ci->ci_cpuid;
 	if (__predict_false(pmap != ci->ci_pmap)) {
 		TLB_COUNT(invalidate_user_not_current);
 		/*
 		 * For CPUs that don't implement ASNs, the SWPCTX call
 		 * does all of the TLB invalidation work for us.
 		 */
 		if (__predict_false(pmap_max_asn == 0)) {
 			return;
+		}
 		/*
 		 * We cannot directly invalidate the TLB in this case,
 		 * so force allocation of a new ASN when the pmap becomes
 		 * active again.
 		 */
 		pmap->pm_asni[ci->ci_cpuid].pma_asngen = PMAP_ASNGEN_INVALID;
 		atomic_and_ulong(&pmap->pm_cpus, ~cpu_mask);
 		/*
 		 * This isn't strictly necessary; when we allocate a
 		 * new ASN, we're going to clear this bit and skip
 		 * syncing the I-stream.  But we will keep this bit
 		 * of accounting for internal consistency.
 		 */
 		if (TLB_CTX_FLAGS(tlbctx) & TLB_CTX_F_IMB) {
 			atomic_or_ulong(&pmap->pm_needisync, cpu_mask);
+		}
 		return;
+	}
 	if (TLB_CTX_FLAGS(tlbctx) & TLB_CTX_F_IMB) {
 		TLB_COUNT(invalidate_user_lazy_imb);
 		atomic_or_ulong(&pmap->pm_needisync, cpu_mask);
+	}
 	if (count == TLB_CTX_ALLVA) {
 		/*
 		 * Another option here for CPUs that implement ASNs is
 		 * to allocate a new ASN and do a SWPCTX.  That's almost
 		 * certainly faster than a TBIAP, but would require us
 		 * to synchronize against IPIs in pmap_activate().
 		 */
 		TLB_COUNT(invalidate_user_tbiap);
 		KASSERT((TLB_CTX_FLAGS(tlbctx) & TLB_CTX_F_ASM) == 0);
 		ALPHA_TBIAP();
 	} else {
 		TLB_COUNT(invalidate_user_tbis);
 		for (uintptr_t i = 0; i < count; i++) {
 			ALPHA_TBIS(TLB_CTX_VA(tlbctx, i));
+		}
+	}
+}
 static void
 pmap_tlb_shootnow(const struct pmap_tlb_context * const tlbctx)
+{
 	if (TLB_CTX_COUNT(tlbctx) == 0) {
 		/* No work to do. */
 		return;
+	}
 	/*
 	 * Acquire the shootdown mutex.  This will also block IPL_VM
 	 * interrupts and disable preemption.  It is critically important
 	 * that IPIs not be blocked in this routine.
 	 */
 	KASSERT((alpha_pal_rdps() & ALPHA_PSL_IPL_MASK) < ALPHA_PSL_IPL_CLOCK);
 	mutex_spin_enter(&tlb_lock);
 	tlb_evcnt.ev_count++;
 	const struct cpu_info *ci = curcpu();
 	const u_long this_cpu = 1UL << ci->ci_cpuid;
 	u_long active_cpus;
 	bool activation_locked;
 	/*
 	 * Figure out who to notify.  If it's for the kernel or
 	 * multiple aaddress spaces, we notify everybody.  If
 	 * it's a single user pmap, then we try to acquire the
 	 * activation lock so we can get an accurate accounting
 	 * of who needs to be notified.  If we can't acquire
 	 * the activation lock, then just notify everyone and
 	 * let them sort it out when they process the IPI.
 	 */
 	if (TLB_CTX_FLAGS(tlbctx) & (TLB_CTX_F_ASM | TLB_CTX_F_MULTI)) {
 		active_cpus = pmap_all_cpus();
 		activation_locked = false;
 	} else {
 		KASSERT(tlbctx->t_pmap != NULL);
 		activation_locked = PMAP_ACT_TRYLOCK(tlbctx->t_pmap);
 		if (__predict_true(activation_locked)) {
 			active_cpus = tlbctx->t_pmap->pm_cpus;
 		} else {
 			TLB_COUNT(shootnow_over_notify);
 			active_cpus = pmap_all_cpus();
+		}
+	}
 #if defined(MULTIPROCESSOR)
 	/*
 	 * If there are remote CPUs that need to do work, get them
 	 * started now.
 	 */
 	const u_long remote_cpus = active_cpus & ~this_cpu;
 	KASSERT(tlb_context == NULL);
 	if (remote_cpus) {
 		TLB_COUNT(shootnow_remote);
 		tlb_context = tlbctx;
 		tlb_pending = remote_cpus;
 		alpha_multicast_ipi(remote_cpus, ALPHA_IPI_SHOOTDOWN);
+	}
 #endif /* MULTIPROCESSOR */
 	/*
 	 * Now that the remotes have been notified, release the
 	 * activation lock.
 	 */
 	if (activation_locked) {
 		KASSERT(tlbctx->t_pmap != NULL);
 		PMAP_ACT_UNLOCK(tlbctx->t_pmap);
+	}
 	/*
 	 * Do any work that we might need to do.  We don't need to
 	 * synchronize with activation here because we know that
 	 * for the current CPU, activation status will not change.
 	 */
 	if (active_cpus & this_cpu) {
 		pmap_tlb_invalidate(tlbctx, ci);
+	}
 #if defined(MULTIPROCESSOR)
 	/* Wait for remote CPUs to finish. */
 	if (remote_cpus) {
 		int backoff = SPINLOCK_BACKOFF_MIN;
 		u_int spins = 0;
 		while (atomic_load_relaxed(&tlb_context) != NULL) {
 			SPINLOCK_BACKOFF(backoff);
 			if (spins++ > 0x0fffffff) {
 				printf("TLB LOCAL MASK  = 0x%016lx\n",
 				    this_cpu);
 				printf("TLB REMOTE MASK = 0x%016lx\n",
 				    remote_cpus);
 				printf("TLB REMOTE PENDING = 0x%016lx\n",
 				    tlb_pending);
 				printf("TLB CONTEXT = %p\n", tlb_context);
 				printf("TLB LOCAL IPL = %lu\n",
 				    alpha_pal_rdps() & ALPHA_PSL_IPL_MASK);
 				panic("pmap_tlb_shootnow");
+			}
+		}
 		membar_consumer();
+	}
 	KASSERT(tlb_context == NULL);
 #endif /* MULTIPROCESSOR */
 	mutex_spin_exit(&tlb_lock);
 	if (__predict_false(TLB_CTX_FLAGS(tlbctx) & TLB_CTX_F_PV)) {
 		/*
 		 * P->V TLB operations may operate on multiple pmaps.
 		 * The shootdown takes a reference on the first pmap it
 		 * encounters, in order to prevent it from disappearing,
 		 * in the hope that we end up with a single-pmap P->V
 		 * operation (instrumentation shows this is not rare).
+		 *
 		 * Once this shootdown is finished globally, we need to
 		 * release this extra reference.
 		 */
 		KASSERT(tlbctx->t_pmap != NULL);
 		pmap_destroy(tlbctx->t_pmap);
+	}
+}
 #if defined(MULTIPROCESSOR)
 void
 pmap_tlb_shootdown_ipi(struct cpu_info * const ci,
     struct trapframe * const tf __unused)
+{
 	KASSERT(tlb_context != NULL);
 	pmap_tlb_invalidate(tlb_context, ci);
 	if (atomic_and_ulong_nv(&tlb_pending, ~(1UL << ci->ci_cpuid)) == 0) {
 		membar_producer();
 		atomic_store_relaxed(&tlb_context, NULL);
+	}
+}
 #endif /* MULTIPROCESSOR */
 static void
 pmap_tlb_physpage_free(paddr_t const ptpa,
     struct pmap_tlb_context * const tlbctx)
+{
 	struct vm_page * const pg = PHYS_TO_VM_PAGE(ptpa);
 	KASSERT(pg != NULL);
 #ifdef DEBUG
 	struct vm_page_md * const md = VM_PAGE_TO_MD(pg);
 	KDASSERT(md->pvh_refcnt == 0);
 #endif
 	LIST_INSERT_HEAD(&tlbctx->t_freeptq, pg, pageq.list);
+}
 static void
 pmap_tlb_ptpage_drain(struct pmap_tlb_context * const tlbctx)
+{
 	struct vm_page *pg;
 	while ((pg = LIST_FIRST(&tlbctx->t_freeptq)) != NULL) {
 		LIST_REMOVE(pg, pageq.list);
 		uvm_pagefree(pg);
+	}
+}
 /*
  * Internal routines
  */
 static void	alpha_protection_init(void);
 static pt_entry_t pmap_remove_mapping(pmap_t, vaddr_t, pt_entry_t *, bool,
 				      pv_entry_t *,
 				      struct pmap_tlb_context *);
 static void	pmap_changebit(struct vm_page *, pt_entry_t, pt_entry_t,
 			       struct pmap_tlb_context *);
 /*
  * PT page management functions.
  */
 static int	pmap_ptpage_alloc(pt_entry_t *, int);
 static void	pmap_ptpage_free(pt_entry_t *, struct pmap_tlb_context *);
 static void	pmap_l3pt_delref(pmap_t, vaddr_t, pt_entry_t *,
 		     struct pmap_tlb_context *);
 static void	pmap_l2pt_delref(pmap_t, pt_entry_t *, pt_entry_t *,
 		     struct pmap_tlb_context *);
 static void	pmap_l1pt_delref(pmap_t, pt_entry_t *);
 static void	*pmap_l1pt_alloc(struct pool *, int);
 static void	pmap_l1pt_free(struct pool *, void *);
 static struct pool_allocator pmap_l1pt_allocator = {
 	pmap_l1pt_alloc, pmap_l1pt_free, 0,
 };
 static int	pmap_l1pt_ctor(void *, void *, int);
 /*
  * PV table management functions.
  */
 static int	pmap_pv_enter(pmap_t, struct vm_page *, vaddr_t, pt_entry_t *,
 			      bool, pv_entry_t);
 static void	pmap_pv_remove(pmap_t, struct vm_page *, vaddr_t, bool,
 			       pv_entry_t *);
 static void	*pmap_pv_page_alloc(struct pool *, int);
 static void	pmap_pv_page_free(struct pool *, void *);
 static struct pool_allocator pmap_pv_page_allocator = {
 	pmap_pv_page_alloc, pmap_pv_page_free, 0,
 };
 #ifdef DEBUG
 void	pmap_pv_dump(paddr_t);
 #endif
 #define	pmap_pv_alloc()		pool_cache_get(&pmap_pv_cache, PR_NOWAIT)
 #define	pmap_pv_free(pv)	pool_cache_put(&pmap_pv_cache, (pv))
 /*
  * ASN management functions.
  */
 static u_int	pmap_asn_alloc(pmap_t, struct cpu_info *);
 /*
  * Misc. functions.
  */
 static bool	pmap_physpage_alloc(int, paddr_t *);
 static void	pmap_physpage_free(paddr_t);
 static int	pmap_physpage_addref(void *);
 static int	pmap_physpage_delref(void *);
 static bool	vtophys_internal(vaddr_t, paddr_t *p);
 /*
  * PMAP_KERNEL_PTE:
+ *
  *	Get a kernel PTE.
+ *
  *	If debugging, do a table walk.  If not debugging, just use
  *	the Virtual Page Table, since all kernel page tables are
  *	pre-allocated and mapped in.
  */
 #ifdef DEBUG
 #define	PMAP_KERNEL_PTE(va)						\
 ({									\
 	pt_entry_t *l1pte_, *l2pte_;					\
+									\
 	l1pte_ = pmap_l1pte(pmap_kernel(), va);				\
 	if (pmap_pte_v(l1pte_) == 0) {					\
 		printf("kernel level 1 PTE not valid, va 0x%lx "	\
 		    "(line %d)\n", (va), __LINE__);			\
 		panic("PMAP_KERNEL_PTE");				\
 	}								\
 	l2pte_ = pmap_l2pte(pmap_kernel(), va, l1pte_);			\
 	if (pmap_pte_v(l2pte_) == 0) {					\
 		printf("kernel level 2 PTE not valid, va 0x%lx "	\
 		    "(line %d)\n", (va), __LINE__);			\
 		panic("PMAP_KERNEL_PTE");				\
 	}								\
 	pmap_l3pte(pmap_kernel(), va, l2pte_);				\
 })
 #else
 #define	PMAP_KERNEL_PTE(va)	(&VPT[VPT_INDEX((va))])
 #endif
 /*
  * PMAP_STAT_{INCR,DECR}:
+ *
  *	Increment or decrement a pmap statistic.
  */
 #define	PMAP_STAT_INCR(s, v)	atomic_add_long((unsigned long *)(&(s)), (v))
 #define	PMAP_STAT_DECR(s, v)	atomic_add_long((unsigned long *)(&(s)), -(v))
 /*
  * pmap_init_cpu:
+ *
  *	Initilize pmap data in the cpu_info.
  */
 void
 pmap_init_cpu(struct cpu_info * const ci)
+{
 	pmap_t const pmap = pmap_kernel();
 	/* All CPUs start out using the kernel pmap. */
 	atomic_or_ulong(&pmap->pm_cpus, 1UL << ci->ci_cpuid);
 	pmap_reference(pmap);
 	ci->ci_pmap = pmap;
 	/* Initialize ASN allocation logic. */
 	ci->ci_next_asn = PMAP_ASN_FIRST_USER;
 	ci->ci_asn_gen = PMAP_ASNGEN_INITIAL;
+}
 /*
  * pmap_bootstrap:
+ *
  *	Bootstrap the system to run with virtual memory.
+ *
  *	Note: no locking is necessary in this function.
  */
 void
 pmap_bootstrap(paddr_t ptaddr, u_int maxasn, u_long ncpuids)
+{
 	vsize_t lev2mapsize, lev3mapsize;
 	pt_entry_t *lev2map, *lev3map;
 	pt_entry_t pte;
 	vsize_t bufsz;
 	struct pcb *pcb;
 	int i;
 #ifdef DEBUG
 	if (pmapdebug & (PDB_FOLLOW|PDB_BOOTSTRAP))
 		printf("pmap_bootstrap(0x%lx, %u)\n", ptaddr, maxasn);
 #endif
 	/*
 	 * Compute the number of pages kmem_arena will have.
 	 */
 	kmeminit_nkmempages();
 	/*
 	 * Figure out how many initial PTE's are necessary to map the
 	 * kernel.  We also reserve space for kmem_alloc_pageable()
 	 * for vm_fork().
 	 */
 	/* Get size of buffer cache and set an upper limit */
 	bufsz = buf_memcalc();
 	buf_setvalimit(bufsz);
 	lev3mapsize =
 		(VM_PHYS_SIZE + (ubc_nwins << ubc_winshift) +
 		 bufsz + 16 * NCARGS + pager_map_size) / PAGE_SIZE +
 		(maxproc * UPAGES) + nkmempages;
 	lev3mapsize = roundup(lev3mapsize, NPTEPG);
 	/*
 	 * Initialize `FYI' variables.  Note we're relying on
 	 * the fact that BSEARCH sorts the vm_physmem[] array
 	 * for us.
 	 */
 	avail_start = ptoa(uvm_physseg_get_avail_start(uvm_physseg_get_first()));
 	avail_end = ptoa(uvm_physseg_get_avail_end(uvm_physseg_get_last()));
 	virtual_end = VM_MIN_KERNEL_ADDRESS + lev3mapsize * PAGE_SIZE;
 #if 0
 	printf("avail_start = 0x%lx\n", avail_start);
 	printf("avail_end = 0x%lx\n", avail_end);
 	printf("virtual_end = 0x%lx\n", virtual_end);
 #endif
 	/*
 	 * Allocate a level 1 PTE table for the kernel.
 	 * This is always one page long.
 	 * IF THIS IS NOT A MULTIPLE OF PAGE_SIZE, ALL WILL GO TO HELL.
 	 */
 	kernel_lev1map = (pt_entry_t *)
 	    uvm_pageboot_alloc(sizeof(pt_entry_t) * NPTEPG);
 	/*
 	 * Allocate a level 2 PTE table for the kernel.
 	 * These must map all of the level3 PTEs.
 	 * IF THIS IS NOT A MULTIPLE OF PAGE_SIZE, ALL WILL GO TO HELL.
 	 */
 	lev2mapsize = roundup(howmany(lev3mapsize, NPTEPG), NPTEPG);
 	lev2map = (pt_entry_t *)
 	    uvm_pageboot_alloc(sizeof(pt_entry_t) * lev2mapsize);
 	/*
 	 * Allocate a level 3 PTE table for the kernel.
 	 * Contains lev3mapsize PTEs.
 	 */
 	lev3map = (pt_entry_t *)
 	    uvm_pageboot_alloc(sizeof(pt_entry_t) * lev3mapsize);
 	/*
 	 * Set up level 1 page table
 	 */
 	/* Map all of the level 2 pte pages */
 	for (i = 0; i < howmany(lev2mapsize, NPTEPG); i++) {
 		pte = (ALPHA_K0SEG_TO_PHYS(((vaddr_t)lev2map) +
 		    (i*PAGE_SIZE)) >> PGSHIFT) << PG_SHIFT;
 		pte |= PG_V | PG_ASM | PG_KRE | PG_KWE | PG_WIRED;
 		kernel_lev1map[l1pte_index(VM_MIN_KERNEL_ADDRESS +
 		    (i*PAGE_SIZE*NPTEPG*NPTEPG))] = pte;
+	}
 	/* Map the virtual page table */
 	pte = (ALPHA_K0SEG_TO_PHYS((vaddr_t)kernel_lev1map) >> PGSHIFT)
 	    << PG_SHIFT;
 	pte |= PG_V | PG_KRE | PG_KWE; /* NOTE NO ASM */
 	kernel_lev1map[l1pte_index(VPTBASE)] = pte;
 	VPT = (pt_entry_t *)VPTBASE;
 #ifdef _PMAP_MAY_USE_PROM_CONSOLE
 	extern pt_entry_t prom_pte;			/* XXX */
 	extern int prom_mapped;				/* XXX */
 	if (pmap_uses_prom_console()) {
 		/*
 		 * XXX Save old PTE so we can remap the PROM, if
 		 * XXX necessary.
 		 */
 		prom_pte = *(pt_entry_t *)ptaddr & ~PG_ASM;
 	prom_mapped = 0;
 	/*
 	 * Actually, this code lies.  The prom is still mapped, and will
 	 * remain so until the context switch after alpha_init() returns.
 	 */
 #endif
 	/*
 	 * Set up level 2 page table.
 	 */
 	/* Map all of the level 3 pte pages */
 	for (i = 0; i < howmany(lev3mapsize, NPTEPG); i++) {
 		pte = (ALPHA_K0SEG_TO_PHYS(((vaddr_t)lev3map) +
 		    (i*PAGE_SIZE)) >> PGSHIFT) << PG_SHIFT;
 		pte |= PG_V | PG_ASM | PG_KRE | PG_KWE | PG_WIRED;
 		lev2map[l2pte_index(VM_MIN_KERNEL_ADDRESS+
 		    (i*PAGE_SIZE*NPTEPG))] = pte;
+	}
 	/* Initialize the pmap_growkernel_lock. */
 	rw_init(&pmap_growkernel_lock);
 	/*
 	 * Set up level three page table (lev3map)
 	 */
 	/* Nothing to do; it's already zero'd */
 	/*
 	 * Initialize the pmap pools and list.
 	 */
 	pmap_ncpuids = ncpuids;
 	pool_cache_bootstrap(&pmap_pmap_cache, PMAP_SIZEOF(pmap_ncpuids),
 	    COHERENCY_UNIT, 0, 0, "pmap", NULL, IPL_NONE, NULL, NULL, NULL);
 	pool_cache_bootstrap(&pmap_l1pt_cache, PAGE_SIZE, 0, 0, 0, "pmapl1pt",
 	    &pmap_l1pt_allocator, IPL_NONE, pmap_l1pt_ctor, NULL, NULL);
 	pool_cache_bootstrap(&pmap_pv_cache, sizeof(struct pv_entry), 0, 0,
 	    PR_LARGECACHE, "pmappv", &pmap_pv_page_allocator, IPL_NONE, NULL,
 	    NULL, NULL);
 	TAILQ_INIT(&pmap_all_pmaps);
 	/* Initialize the ASN logic.  See also pmap_init_cpu(). */
 	pmap_max_asn = maxasn;
 	/*
 	 * Initialize the locks.
 	 */
 	rw_init(&pmap_main_lock);
 	mutex_init(&pmap_all_pmaps_lock, MUTEX_DEFAULT, IPL_NONE);
 	for (i = 0; i < __arraycount(pmap_pvh_locks); i++) {
 		mutex_init(&pmap_pvh_locks[i].lock, MUTEX_DEFAULT, IPL_NONE);
+	}
 	for (i = 0; i < __arraycount(pmap_pvh_locks); i++) {
 		mutex_init(&pmap_pmap_locks[i].locks.lock,
 		    MUTEX_DEFAULT, IPL_NONE);
 		mutex_init(&pmap_pmap_locks[i].locks.activation_lock,
 		    MUTEX_SPIN, IPL_SCHED);
+	}
 	/*
 	 * This must block any interrupt from which a TLB shootdown
 	 * could be issued, but must NOT block IPIs.
 	 */
 	mutex_init(&tlb_lock, MUTEX_SPIN, IPL_VM);
 	/*
 	 * Initialize kernel pmap.  Note that all kernel mappings
 	 * have PG_ASM set, so the ASN doesn't really matter for
 	 * the kernel pmap.  Also, since the kernel pmap always
 	 * references kernel_lev1map, it always has an invalid ASN
 	 * generation.
 	 */
 	memset(pmap_kernel(), 0, sizeof(struct pmap));
 	pmap_kernel()->pm_lev1map = kernel_lev1map;
 	pmap_kernel()->pm_count = 1;
 	/* Kernel pmap does not have ASN info. */
 	TAILQ_INSERT_TAIL(&pmap_all_pmaps, pmap_kernel(), pm_list);
 	/*
 	 * Set up lwp0's PCB such that the ptbr points to the right place
 	 * and has the kernel pmap's (really unused) ASN.
 	 */
 	pcb = lwp_getpcb(&lwp0);
 	pcb->pcb_hw.apcb_ptbr =
 	    ALPHA_K0SEG_TO_PHYS((vaddr_t)kernel_lev1map) >> PGSHIFT;
 	pcb->pcb_hw.apcb_asn = PMAP_ASN_KERNEL;
 	struct cpu_info * const ci = curcpu();
 	pmap_init_cpu(ci);
+}
 #ifdef _PMAP_MAY_USE_PROM_CONSOLE
 int
 pmap_uses_prom_console(void)
 	return (cputype == ST_DEC_21000);
 #endif /* _PMAP_MAY_USE_PROM_CONSOLE */
 /*
  * pmap_virtual_space:		[ INTERFACE ]
+ *
  *	Define the initial bounds of the kernel virtual address space.
  */
 void
 pmap_virtual_space(vaddr_t *vstartp, vaddr_t *vendp)
+{
 	*vstartp = VM_MIN_KERNEL_ADDRESS;	/* kernel is in K0SEG */
 	*vendp = VM_MAX_KERNEL_ADDRESS;		/* we use pmap_growkernel */
+}
 /*
  * pmap_steal_memory:		[ INTERFACE ]
+ *
  *	Bootstrap memory allocator (alternative to vm_bootstrap_steal_memory()).
  *	This function allows for early dynamic memory allocation until the
  *	virtual memory system has been bootstrapped.  After that point, either
  *	kmem_alloc or malloc should be used.  This function works by stealing
  *	pages from the (to be) managed page pool, then implicitly mapping the
  *	pages (by using their k0seg addresses) and zeroing them.
+ *
  *	It may be used once the physical memory segments have been pre-loaded
  *	into the vm_physmem[] array.  Early memory allocation MUST use this
  *	interface!  This cannot be used after vm_page_startup(), and will
  *	generate a panic if tried.
+ *
  *	Note that this memory will never be freed, and in essence it is wired
  *	down.
+ *
  *	We must adjust *vstartp and/or *vendp iff we use address space
  *	from the kernel virtual address range defined by pmap_virtual_space().
+ *
  *	Note: no locking is necessary in this function.
  */
 vaddr_t
 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp)
+{
 	int npgs;
 	vaddr_t va;
 	paddr_t pa;
 	uvm_physseg_t bank;
 	size = round_page(size);
 	npgs = atop(size);
 #if 0
 	printf("PSM: size 0x%lx (npgs 0x%x)\n", size, npgs);
 #endif
 	for (bank = uvm_physseg_get_first();
 	     uvm_physseg_valid_p(bank);
 	     bank = uvm_physseg_get_next(bank)) {
 		if (uvm.page_init_done == true)
 			panic("pmap_steal_memory: called _after_ bootstrap");
 #if 0
 		printf("     bank %d: avail_start 0x%"PRIxPADDR", start 0x%"PRIxPADDR", "
 		    "avail_end 0x%"PRIxPADDR"\n", bank, uvm_physseg_get_avail_start(bank),
 		    uvm_physseg_get_start(bank), uvm_physseg_get_avail_end(bank));
 #endif
 		if (uvm_physseg_get_avail_start(bank) != uvm_physseg_get_start(bank) ||
 		    uvm_physseg_get_avail_start(bank) >= uvm_physseg_get_avail_end(bank))
 			continue;
 #if 0
 		printf("             avail_end - avail_start = 0x%"PRIxPADDR"\n",
 		    uvm_physseg_get_avail_end(bank) - uvm_physseg_get_avail_start(bank));
 #endif
 		if (uvm_physseg_get_avail_end(bank) - uvm_physseg_get_avail_start(bank)
 		    < npgs)
 			continue;
 		/*
 		 * There are enough pages here; steal them!
 		 */
 		pa = ptoa(uvm_physseg_get_start(bank));
 		uvm_physseg_unplug(atop(pa), npgs);
 		va = ALPHA_PHYS_TO_K0SEG(pa);
 		memset((void *)va, 0, size);
 		pmap_pages_stolen += npgs;
 		return (va);
+	}
 	/*
 	 * If we got here, this was no memory left.
 	 */
 	panic("pmap_steal_memory: no memory to steal");
+}
 /*
  * pmap_init:			[ INTERFACE ]
+ *
  *	Initialize the pmap module.  Called by vm_init(), to initialize any
  *	structures that the pmap system needs to map virtual memory.
+ *
  *	Note: no locking is necessary in this function.
  */
 void
 pmap_init(void)
+{
 #ifdef DEBUG
 	if (pmapdebug & PDB_FOLLOW)
 	        printf("pmap_init()\n");
 #endif
 	/* initialize protection array */
 	alpha_protection_init();
 	/* Initialize TLB handling. */
 	pmap_tlb_init();
 	/*
 	 * Set a low water mark on the pv_entry pool, so that we are
 	 * more likely to have these around even in extreme memory
 	 * starvation.
 	 */
 	pool_cache_setlowat(&pmap_pv_cache, pmap_pv_lowat);
 	/*
 	 * Now it is safe to enable pv entry recording.
 	 */
 	pmap_initialized = true;
 #if 0
 	for (uvm_physseg_t bank = uvm_physseg_get_first();
 	    uvm_physseg_valid_p(bank);
 	    bank = uvm_physseg_get_next(bank)) {
 		printf("bank %d\n", bank);
 		printf("\tstart = 0x%lx\n", ptoa(uvm_physseg_get_start(bank)));
 		printf("\tend = 0x%lx\n", ptoa(uvm_physseg_get_end(bank)));
 		printf("\tavail_start = 0x%lx\n",
 		    ptoa(uvm_physseg_get_avail_start(bank)));
 		printf("\tavail_end = 0x%lx\n",
 		    ptoa(uvm_physseg_get_avail_end(bank)));
+	}
 #endif
+}
 /*
  * pmap_create:			[ INTERFACE ]
+ *
  *	Create and return a physical map.
+ *
  *	Note: no locking is necessary in this function.
  */
 pmap_t
 pmap_create(void)
+{
 	pmap_t pmap;
 	int i;
 #ifdef DEBUG
 	if (pmapdebug & (PDB_FOLLOW|PDB_CREATE))
 		printf("pmap_create()\n");
 #endif
 	pmap = pool_cache_get(&pmap_pmap_cache, PR_WAITOK);
 	memset(pmap, 0, sizeof(*pmap));
 	pmap->pm_count = 1;
 	/*
 	 * There are only kernel mappings at this point; give the pmap
 	 * the kernel ASN.  This will be initialized to correct values
 	 * when the pmap is activated.
 	 */
 	for (i = 0; i < pmap_ncpuids; i++) {
 		pmap->pm_asni[i].pma_asn = PMAP_ASN_KERNEL;
 		pmap->pm_asni[i].pma_asngen = PMAP_ASNGEN_INVALID;
+	}
  try_again:
 	rw_enter(&pmap_growkernel_lock, RW_READER);
 	pmap->pm_lev1map = pool_cache_get(&pmap_l1pt_cache, PR_NOWAIT);
 	if (__predict_false(pmap->pm_lev1map == NULL)) {
 		rw_exit(&pmap_growkernel_lock);
 		(void) kpause("pmap_create", false, hz >> 2, NULL);
 		goto try_again;
+	}
 	mutex_enter(&pmap_all_pmaps_lock);
 	TAILQ_INSERT_TAIL(&pmap_all_pmaps, pmap, pm_list);
 	mutex_exit(&pmap_all_pmaps_lock);
 	rw_exit(&pmap_growkernel_lock);
 	return (pmap);
+}
 /*
  * pmap_destroy:		[ INTERFACE ]
+ *
  *	Drop the reference count on the specified pmap, releasing
  *	all resources if the reference count drops to zero.
  */
 void
 pmap_destroy(pmap_t pmap)
+{
 #ifdef DEBUG
 	if (pmapdebug & PDB_FOLLOW)
 		printf("pmap_destroy(%p)\n", pmap);
 #endif
 	PMAP_MP(membar_exit());
 	if (atomic_dec_ulong_nv(&pmap->pm_count) > 0)
 		return;
 	rw_enter(&pmap_growkernel_lock, RW_READER);
 	/*
 	 * Remove it from the global list of all pmaps.
 	 */
 	mutex_enter(&pmap_all_pmaps_lock);
 	TAILQ_REMOVE(&pmap_all_pmaps, pmap, pm_list);
 	mutex_exit(&pmap_all_pmaps_lock);
 	pool_cache_put(&pmap_l1pt_cache, pmap->pm_lev1map);
 	pmap->pm_lev1map = NULL;
 	rw_exit(&pmap_growkernel_lock);
 	pool_cache_put(&pmap_pmap_cache, pmap);
+}
 /*
  * pmap_reference:		[ INTERFACE ]
+ *
  *	Add a reference to the specified pmap.
  */
 void
 pmap_reference(pmap_t pmap)
+{
 #ifdef DEBUG
 	if (pmapdebug & PDB_FOLLOW)
 		printf("pmap_reference(%p)\n", pmap);
 #endif
 	atomic_inc_ulong(&pmap->pm_count);
 	PMAP_MP(membar_enter());
+}
 /*
  * pmap_remove:			[ INTERFACE ]
+ *
  *	Remove the given range of addresses from the specified map.
+ *
  *	It is assumed that the start and end are properly
  *	rounded to the page size.
  */
 static void
 pmap_remove_internal(pmap_t pmap, vaddr_t sva, vaddr_t eva,
     struct pmap_tlb_context * const tlbctx)
+{
 	pt_entry_t *l1pte, *l2pte, *l3pte;
 	pt_entry_t *saved_l2pte, *saved_l3pte;
 	vaddr_t l1eva, l2eva, l3vptva;
 	pt_entry_t pte_bits;
 #ifdef DEBUG
 	if (pmapdebug & (PDB_FOLLOW|PDB_REMOVE|PDB_PROTECT))
 		printf("pmap_remove(%p, %lx, %lx)\n", pmap, sva, eva);
 #endif
 	/*
 	 * If this is the kernel pmap, we can use a faster method
 	 * for accessing the PTEs (since the PT pages are always
 	 * resident).
+	 *
 	 * Note that this routine should NEVER be called from an
 	 * interrupt context; pmap_kremove() is used for that.
 	 */
 	if (pmap == pmap_kernel()) {
 		PMAP_MAP_TO_HEAD_LOCK();
 		PMAP_LOCK(pmap);
 		while (sva < eva) {
 			l3pte = PMAP_KERNEL_PTE(sva);
 			if (pmap_pte_v(l3pte)) {
 				pte_bits = pmap_remove_mapping(pmap, sva,
 				    l3pte, true, NULL, tlbctx);
 				pmap_tlb_shootdown(pmap, sva, pte_bits,
 				    tlbctx);
+			}
 			sva += PAGE_SIZE;
+		}
 		PMAP_MAP_TO_HEAD_UNLOCK();
 		PMAP_UNLOCK(pmap);
 		pmap_tlb_shootnow(tlbctx);
 		pmap_tlb_ptpage_drain(tlbctx);
 		TLB_COUNT(reason_remove_kernel);
 		return;
+	}
 	KASSERT(sva < VM_MAXUSER_ADDRESS);
 	KASSERT(eva <= VM_MAXUSER_ADDRESS);
 	KASSERT(pmap->pm_lev1map != kernel_lev1map);
 	PMAP_MAP_TO_HEAD_LOCK();
 	PMAP_LOCK(pmap);
 	l1pte = pmap_l1pte(pmap, sva);
 	for (; sva < eva; sva = l1eva, l1pte++) {
 		l1eva = alpha_trunc_l1seg(sva) + ALPHA_L1SEG_SIZE;
 		if (pmap_pte_v(l1pte)) {
 			saved_l2pte = l2pte = pmap_l2pte(pmap, sva, l1pte);
 			/*
 			 * Add a reference to the L2 table so it won't
 			 * get removed from under us.
 			 */
 			pmap_physpage_addref(saved_l2pte);
 			for (; sva < l1eva && sva < eva; sva = l2eva, l2pte++) {
 				l2eva =
 				    alpha_trunc_l2seg(sva) + ALPHA_L2SEG_SIZE;
 				if (pmap_pte_v(l2pte)) {
 					saved_l3pte = l3pte =
 					    pmap_l3pte(pmap, sva, l2pte);
 					/*
 					 * Add a reference to the L3 table so
 					 * it won't get removed from under us.
 					 */
 					pmap_physpage_addref(saved_l3pte);
 					/*
 					 * Remember this sva; if the L3 table
 					 * gets removed, we need to invalidate
 					 * the VPT TLB entry for it.
 					 */
 					l3vptva = sva;
 					for (; sva < l2eva && sva < eva;
 					     sva += PAGE_SIZE, l3pte++) {
 						if (!pmap_pte_v(l3pte)) {
 							continue;
+						}
 						pte_bits =
 						    pmap_remove_mapping(
 							pmap, sva,
 							l3pte, true,
 							NULL, tlbctx);
 						pmap_tlb_shootdown(pmap,
 						    sva, pte_bits, tlbctx);
+					}
 					/*
 					 * Remove the reference to the L3
 					 * table that we added above.  This
 					 * may free the L3 table.
 					 */
 					pmap_l3pt_delref(pmap, l3vptva,
 					    saved_l3pte, tlbctx);
+				}
+			}
 			/*
 			 * Remove the reference to the L2 table that we
 			 * added above.  This may free the L2 table.
 			 */
 			pmap_l2pt_delref(pmap, l1pte, saved_l2pte, tlbctx);
+		}
+	}
 	PMAP_MAP_TO_HEAD_UNLOCK();
 	PMAP_UNLOCK(pmap);
 	pmap_tlb_shootnow(tlbctx);
 	pmap_tlb_ptpage_drain(tlbctx);
 	TLB_COUNT(reason_remove_user);
+}
 void
 pmap_remove(pmap_t pmap, vaddr_t sva, vaddr_t eva)
+{
 	struct pmap_tlb_context tlbctx;
 	pmap_tlb_context_init(&tlbctx);
 	pmap_remove_internal(pmap, sva, eva, &tlbctx);
+}
 /*
  * pmap_page_protect:		[ INTERFACE ]
+ *
  *	Lower the permission for all mappings to a given page to
  *	the permissions specified.
  */
 void
 pmap_page_protect(struct vm_page *pg, vm_prot_t prot)
+{
 	struct vm_page_md * const md = VM_PAGE_TO_MD(pg);
 	pv_entry_t pv, nextpv;
 	pt_entry_t opte;
 	kmutex_t *lock;
 	struct pmap_tlb_context tlbctx;
 #ifdef DEBUG
 	paddr_t pa = VM_PAGE_TO_PHYS(pg);
 	if ((pmapdebug & (PDB_FOLLOW|PDB_PROTECT)) ||
 	    (prot == VM_PROT_NONE && (pmapdebug & PDB_REMOVE)))
 		printf("pmap_page_protect(%p, %x)\n", pg, prot);
 #endif
 	pmap_tlb_context_init(&tlbctx);
 	switch (prot) {
 	case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE:
 	case VM_PROT_READ|VM_PROT_WRITE:
 		return;
 	/* copy_on_write */
 	case VM_PROT_READ|VM_PROT_EXECUTE:
 	case VM_PROT_READ:
 		PMAP_HEAD_TO_MAP_LOCK();
 		lock = pmap_pvh_lock(pg);
 		mutex_enter(lock);
 		for (pv = md->pvh_list; pv != NULL; pv = pv->pv_next) {
 			PMAP_LOCK(pv->pv_pmap);
 			opte = atomic_load_relaxed(pv->pv_pte);
 			if (opte & (PG_KWE | PG_UWE)) {
 				atomic_store_relaxed(pv->pv_pte,
 				    opte & ~(PG_KWE | PG_UWE));
 				pmap_tlb_shootdown_pv(pv, opte, &tlbctx);
+			}
 			PMAP_UNLOCK(pv->pv_pmap);
+		}
 		mutex_exit(lock);
 		PMAP_HEAD_TO_MAP_UNLOCK();
 		pmap_tlb_shootnow(&tlbctx);
 		TLB_COUNT(reason_page_protect_read);
 		return;
 	/* remove_all */
 	default:
 		break;
+	}
 	PMAP_HEAD_TO_MAP_LOCK();
 	lock = pmap_pvh_lock(pg);
 	mutex_enter(lock);
 	for (pv = md->pvh_list; pv != NULL; pv = nextpv) {
 		pt_entry_t pte_bits;
 		nextpv = pv->pv_next;
 		PMAP_LOCK(pv->pv_pmap);
 		pte_bits = pmap_remove_mapping(pv->pv_pmap, pv->pv_va,
 		    pv->pv_pte, false, NULL, &tlbctx);
 		pmap_tlb_shootdown_pv(pv, pte_bits, &tlbctx);
 		PMAP_UNLOCK(pv->pv_pmap);
+	}
 	mutex_exit(lock);
 	PMAP_HEAD_TO_MAP_UNLOCK();
 	pmap_tlb_shootnow(&tlbctx);
 	pmap_tlb_ptpage_drain(&tlbctx);
 	TLB_COUNT(reason_page_protect_none);
+}
 /*
  * pmap_protect:		[ INTERFACE ]
+ *
  *	Set the physical protection on the specified range of this map
  *	as requested.
  */
 void
 pmap_protect(pmap_t pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot)
+{
 	pt_entry_t *l1pte, *l2pte, *l3pte, opte;
 	vaddr_t l1eva, l2eva;
 	struct pmap_tlb_context tlbctx;
 #ifdef DEBUG
 	if (pmapdebug & (PDB_FOLLOW|PDB_PROTECT))
 		printf("pmap_protect(%p, %lx, %lx, %x)\n",
 		    pmap, sva, eva, prot);
 #endif
 	pmap_tlb_context_init(&tlbctx);
 	if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
 		pmap_remove_internal(pmap, sva, eva, &tlbctx);
 		return;
+	}
 	const pt_entry_t bits = pte_prot(pmap, prot);
 	PMAP_LOCK(pmap);
 	l1pte = pmap_l1pte(pmap, sva);
 	for (; sva < eva; sva = l1eva, l1pte++) {
 		l1eva = alpha_trunc_l1seg(sva) + ALPHA_L1SEG_SIZE;
 		if (pmap_pte_v(l1pte)) {
 			l2pte = pmap_l2pte(pmap, sva, l1pte);
 			for (; sva < l1eva && sva < eva; sva = l2eva, l2pte++) {
 				l2eva =
 				    alpha_trunc_l2seg(sva) + ALPHA_L2SEG_SIZE;
 				if (pmap_pte_v(l2pte)) {
 					l3pte = pmap_l3pte(pmap, sva, l2pte);
 					for (; sva < l2eva && sva < eva;
 					     sva += PAGE_SIZE, l3pte++) {
 						if (pmap_pte_v(l3pte) &&
 						    pmap_pte_prot_chg(l3pte,
 								      bits)) {
 							opte = atomic_load_relaxed(l3pte);
 							pmap_pte_set_prot(l3pte,
 							   bits);
 							pmap_tlb_shootdown(pmap,
 							    sva, opte, &tlbctx);
+						}
+					}
+				}
+			}
+		}
+	}
 	PMAP_UNLOCK(pmap);
 	pmap_tlb_shootnow(&tlbctx);
 	TLB_COUNT(reason_protect);
+}
 /*
  * pmap_enter_tlb_shootdown:
+ *
  *	Carry out a TLB shootdown on behalf of a pmap_enter()
  *	or a pmap_kenter_pa().  This is factored out separately
  *	because we expect it to be not a common case.
  */
 static void __noinline
 pmap_enter_tlb_shootdown(pmap_t const pmap, vaddr_t const va,
     pt_entry_t const pte_bits, bool locked)
+{
 	struct pmap_tlb_context tlbctx;
 	pmap_tlb_context_init(&tlbctx);
 	pmap_tlb_shootdown(pmap, va, pte_bits, &tlbctx);
 	if (locked) {
 		PMAP_UNLOCK(pmap);
+	}
 	pmap_tlb_shootnow(&tlbctx);
+}
 /*
  * pmap_enter_l2pt_delref:
+ *
  *	Release a reference on an L2 PT page for pmap_enter().
  *	This is factored out separately becacause we expect it
  *	to be a rare case.
  */
 static void __noinline
 pmap_enter_l2pt_delref(pmap_t const pmap, pt_entry_t * const l1pte,
     pt_entry_t * const l2pte)
+{
 	struct pmap_tlb_context tlbctx;
 	/*
 	 * PALcode may have tried to service a TLB miss with
 	 * this L2 PTE, so we need to make sure we don't actully
 	 * free the PT page untl we've shot down any TLB entries
 	 * for this VPT index.
 	 */
 	pmap_tlb_context_init(&tlbctx);
 	pmap_l2pt_delref(pmap, l1pte, l2pte, &tlbctx);
 	PMAP_UNLOCK(pmap);
 	pmap_tlb_shootnow(&tlbctx);
 	pmap_tlb_ptpage_drain(&tlbctx);
 	TLB_COUNT(reason_enter_l2pt_delref);
+}
 /*
  * pmap_enter_l3pt_delref:
+ *
  *	Release a reference on an L3 PT page for pmap_enter().
  *	This is factored out separately becacause we expect it
  *	to be a rare case.
  */
 static void __noinline
 pmap_enter_l3pt_delref(pmap_t const pmap, vaddr_t const va,
     pt_entry_t * const pte)
+{
 	struct pmap_tlb_context tlbctx;
 	/*
 	 * PALcode may have tried to service a TLB miss with
 	 * this PTE, so we need to make sure we don't actully
 	 * free the PT page untl we've shot down any TLB entries
 	 * for this VPT index.
 	 */
 	pmap_tlb_context_init(&tlbctx);
 	pmap_l3pt_delref(pmap, va, pte, &tlbctx);
 	PMAP_UNLOCK(pmap);
 	pmap_tlb_shootnow(&tlbctx);
 	pmap_tlb_ptpage_drain(&tlbctx);
 	TLB_COUNT(reason_enter_l3pt_delref);
+}
 /*
  * pmap_enter:			[ INTERFACE ]
+ *
  *	Insert the given physical page (p) at
  *	the specified virtual address (v) in the
  *	target physical map with the protection requested.
+ *
  *	If specified, the page will be wired down, meaning
  *	that the related pte can not be reclaimed.
+ *
  *	Note:  This is the only routine which MAY NOT lazy-evaluate
  *	or lose information.  That is, this routine must actually
  *	insert this page into the given map NOW.
  */
 int
 pmap_enter(pmap_t pmap, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
+{
 	pt_entry_t *pte, npte, opte;
 	pv_entry_t opv = NULL;
 	paddr_t opa;
 	bool tflush = false;
 	int error = 0;
 	kmutex_t *lock;
 #ifdef DEBUG
 	if (pmapdebug & (PDB_FOLLOW|PDB_ENTER))
 		printf("pmap_enter(%p, %lx, %lx, %x, %x)\n",
 		       pmap, va, pa, prot, flags);
 #endif
 	struct vm_page * const pg = PHYS_TO_VM_PAGE(pa);
 	const bool wired = (flags & PMAP_WIRED) != 0;
 	PMAP_MAP_TO_HEAD_LOCK();
 	PMAP_LOCK(pmap);
 	if (pmap == pmap_kernel()) {
 		KASSERT(va >= VM_MIN_KERNEL_ADDRESS);
 		pte = PMAP_KERNEL_PTE(va);
 	} else {
 		pt_entry_t *l1pte, *l2pte;
 		KASSERT(va < VM_MAXUSER_ADDRESS);
 		KASSERT(pmap->pm_lev1map != kernel_lev1map);
 		/*
 		 * Check to see if the level 1 PTE is valid, and
 		 * allocate a new level 2 page table page if it's not.
 		 * A reference will be added to the level 2 table when
 		 * the level 3 table is created.
 		 */
 		l1pte = pmap_l1pte(pmap, va);
 		if (pmap_pte_v(l1pte) == 0) {
 			pmap_physpage_addref(l1pte);
 			error = pmap_ptpage_alloc(l1pte, PGU_L2PT);
 			if (error) {
 				pmap_l1pt_delref(pmap, l1pte);
 				if (flags & PMAP_CANFAIL)
 					goto out;
 				panic("pmap_enter: unable to create L2 PT "
 				    "page");
+			}
 #ifdef DEBUG
 			if (pmapdebug & PDB_PTPAGE)
 				printf("pmap_enter: new level 2 table at "
 				    "0x%lx\n", pmap_pte_pa(l1pte));
 #endif
+		}
 		/*
 		 * Check to see if the level 2 PTE is valid, and
 		 * allocate a new level 3 page table page if it's not.
 		 * A reference will be added to the level 3 table when
 		 * the mapping is validated.
 		 */
 		l2pte = pmap_l2pte(pmap, va, l1pte);
 		if (pmap_pte_v(l2pte) == 0) {
 			pmap_physpage_addref(l2pte);
 			error = pmap_ptpage_alloc(l2pte, PGU_L3PT);
 			if (error) {
 				/* unlocks pmap */
 				pmap_enter_l2pt_delref(pmap, l1pte, l2pte);
 				if (flags & PMAP_CANFAIL) {
 					PMAP_LOCK(pmap);
 					goto out;
+				}
 				panic("pmap_enter: unable to create L3 PT "
 				    "page");
+			}
 #ifdef DEBUG
 			if (pmapdebug & PDB_PTPAGE)
 				printf("pmap_enter: new level 3 table at "
 				    "0x%lx\n", pmap_pte_pa(l2pte));
 #endif
+		}
 		/*
 		 * Get the PTE that will map the page.
 		 */
 		pte = pmap_l3pte(pmap, va, l2pte);
+	}
 	/* Remember all of the old PTE; used for TBI check later. */
 	opte = atomic_load_relaxed(pte);
 	/*
 	 * Check to see if the old mapping is valid.  If not, validate the
 	 * new one immediately.
 	 */
 	if ((opte & PG_V) == 0) {
 		/* No TLB invalidatons needed for new mappings. */
 		if (pmap != pmap_kernel()) {
 			/*
 			 * New mappings gain a reference on the level 3
 			 * table.
 			 */
 			pmap_physpage_addref(pte);
+		}
 		goto validate_enterpv;
+	}
 	opa = pmap_pte_pa(pte);
 	if (opa == pa) {
 		/*
 		 * Mapping has not changed; must be a protection or
 		 * wiring change.
 		 */
 		if (pmap_pte_w_chg(pte, wired ? PG_WIRED : 0)) {
 #ifdef DEBUG
 			if (pmapdebug & PDB_ENTER)
 				printf("pmap_enter: wiring change -> %d\n",
 				    wired);
 #endif
 			/* Adjust the wiring count. */
 			if (wired)
 				PMAP_STAT_INCR(pmap->pm_stats.wired_count, 1);
 			else
 				PMAP_STAT_DECR(pmap->pm_stats.wired_count, 1);
+		}
 		/* Set the PTE. */
 		goto validate;
+	}
 	/*
 	 * The mapping has changed.  We need to invalidate the
 	 * old mapping before creating the new one.
 	 */
 #ifdef DEBUG
 	if (pmapdebug & PDB_ENTER)
 		printf("pmap_enter: removing old mapping 0x%lx\n", va);
 #endif
 	if (pmap != pmap_kernel()) {
 		/*
 		 * Gain an extra reference on the level 3 table.
 		 * pmap_remove_mapping() will delete a reference,
 		 * and we don't want the table to be erroneously
 		 * freed.
 		 */
 		pmap_physpage_addref(pte);
+	}
 	/* Already have the bits from opte above. */
 	(void) pmap_remove_mapping(pmap, va, pte, true, &opv, NULL);
  validate_enterpv:
 	/* Enter the mapping into the pv_table if appropriate. */
 	if (pg != NULL) {
 		error = pmap_pv_enter(pmap, pg, va, pte, true, opv);
 		if (error) {
 			/* This can only fail if opv == NULL */
 			KASSERT(opv == NULL);
 			/* unlocks pmap */
 			pmap_enter_l3pt_delref(pmap, va, pte);
 			if (flags & PMAP_CANFAIL) {
 				PMAP_LOCK(pmap);
 				goto out;
+			}
 			panic("pmap_enter: unable to enter mapping in PV "
 			    "table");
+		}
 		opv = NULL;
+	}
 	/* Increment counters. */
 	PMAP_STAT_INCR(pmap->pm_stats.resident_count, 1);
 	if (wired)
 		PMAP_STAT_INCR(pmap->pm_stats.wired_count, 1);
  validate:
 	/* Build the new PTE. */
 	npte = ((pa >> PGSHIFT) << PG_SHIFT) | pte_prot(pmap, prot) | PG_V;
 	if (pg != NULL) {
 		struct vm_page_md * const md = VM_PAGE_TO_MD(pg);
 		int attrs;
 		KASSERT(((flags & VM_PROT_ALL) & ~prot) == 0);
 		lock = pmap_pvh_lock(pg);
 		mutex_enter(lock);
 		if (flags & VM_PROT_WRITE)
 			md->pvh_attrs |= (PGA_REFERENCED|PGA_MODIFIED);
 		else if (flags & VM_PROT_ALL)
 			md->pvh_attrs |= PGA_REFERENCED;
 		attrs = md->pvh_attrs;
 		mutex_exit(lock);
 		/* Set up referenced/modified emulation for new mapping. */
 		if ((attrs & PGA_REFERENCED) == 0)
 			npte |= PG_FOR | PG_FOW | PG_FOE;
 		else if ((attrs & PGA_MODIFIED) == 0)
 			npte |= PG_FOW;
 		/*
 		 * Mapping was entered on PV list.
 		 */
 		npte |= PG_PVLIST;
+	}
 	if (wired)
 		npte |= PG_WIRED;
 #ifdef DEBUG
 	if (pmapdebug & PDB_ENTER)
 		printf("pmap_enter: new pte = 0x%lx\n", npte);
 #endif
 	/*
 	 * If the HW / PALcode portion of the new PTE is the same as the
 	 * old PTE, no TBI is necessary.
 	 */
 	if (opte & PG_V) {
 		tflush = PG_PALCODE(opte) != PG_PALCODE(npte);
+	}
 	/* Set the new PTE. */
 	atomic_store_relaxed(pte, npte);
 out:
 	PMAP_MAP_TO_HEAD_UNLOCK();
 	/*
 	 * Invalidate the TLB entry for this VA and any appropriate
 	 * caches.
 	 */
 	if (tflush) {
 		/* unlocks pmap */
 		pmap_enter_tlb_shootdown(pmap, va, opte, true);
 		if (pmap == pmap_kernel()) {
 			TLB_COUNT(reason_enter_kernel);
 		} else {
 			TLB_COUNT(reason_enter_user);
+		}
 	} else {
 		PMAP_UNLOCK(pmap);
+	}
 	if (opv)
 		pmap_pv_free(opv);
 	return error;
+}
 /*
  * pmap_kenter_pa:		[ INTERFACE ]
+ *
  *	Enter a va -> pa mapping into the kernel pmap without any
  *	physical->virtual tracking.
+ *
  *	Note: no locking is necessary in this function.
  */
 void
 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
+{
 	pmap_t const pmap = pmap_kernel();
 #ifdef DEBUG
 	if (pmapdebug & (PDB_FOLLOW|PDB_ENTER))
 		printf("pmap_kenter_pa(%lx, %lx, %x)\n",
 		    va, pa, prot);
 #endif
 	KASSERT(va >= VM_MIN_KERNEL_ADDRESS);
 	pt_entry_t * const pte = PMAP_KERNEL_PTE(va);
 	/* Build the new PTE. */
 	const pt_entry_t npte =
 	    ((pa >> PGSHIFT) << PG_SHIFT) | pte_prot(pmap_kernel(), prot) |
 	    PG_V | PG_WIRED;
 	/* Set the new PTE. */
 	const pt_entry_t opte = atomic_load_relaxed(pte);
 	atomic_store_relaxed(pte, npte);
 	PMAP_MP(membar_enter());
 	PMAP_STAT_INCR(pmap->pm_stats.resident_count, 1);
 	PMAP_STAT_INCR(pmap->pm_stats.wired_count, 1);
 	/*
 	 * There should not have been anything here, previously,
 	 * so we can skip TLB shootdowns, etc. in the common case.
 	 */
 	if (__predict_false(opte & PG_V)) {
 		const pt_entry_t diff = npte ^ opte;
 		printf_nolog("%s: mapping already present\n", __func__);
 		PMAP_STAT_DECR(pmap->pm_stats.resident_count, 1);
 		if (diff & PG_WIRED)
 			PMAP_STAT_DECR(pmap->pm_stats.wired_count, 1);
 		/* XXX Can't handle this case. */
 		if (diff & PG_PVLIST)
 			panic("pmap_kenter_pa: old mapping was managed");
 		pmap_enter_tlb_shootdown(pmap_kernel(), va, opte, false);
 		TLB_COUNT(reason_kenter);
+	}
+}
 /*
  * pmap_kremove:		[ INTERFACE ]
+ *
  *	Remove a mapping entered with pmap_kenter_pa() starting at va,
  *	for size bytes (assumed to be page rounded).
  */
 void
 pmap_kremove(vaddr_t va, vsize_t size)
+{
 	pt_entry_t *pte, opte;
 	pmap_t const pmap = pmap_kernel();
 	struct pmap_tlb_context tlbctx;
 #ifdef DEBUG
 	if (pmapdebug & (PDB_FOLLOW|PDB_ENTER))
 		printf("pmap_kremove(%lx, %lx)\n",
 		    va, size);
 #endif
 	pmap_tlb_context_init(&tlbctx);
 	KASSERT(va >= VM_MIN_KERNEL_ADDRESS);
 	for (; size != 0; size -= PAGE_SIZE, va += PAGE_SIZE) {
 		pte = PMAP_KERNEL_PTE(va);
 		opte = atomic_load_relaxed(pte);
 		if (opte & PG_V) {
 			KASSERT((opte & PG_PVLIST) == 0);
 			/* Zap the mapping. */
 			atomic_store_relaxed(pte, PG_NV);
 			pmap_tlb_shootdown(pmap, va, opte, &tlbctx);
 			/* Update stats. */
 			PMAP_STAT_DECR(pmap->pm_stats.resident_count, 1);
 			PMAP_STAT_DECR(pmap->pm_stats.wired_count, 1);
+		}
+	}
 	pmap_tlb_shootnow(&tlbctx);
 	TLB_COUNT(reason_kremove);
+}
 /*
  * pmap_unwire:			[ INTERFACE ]
+ *
  *	Clear the wired attribute for a map/virtual-address pair.
+ *
  *	The mapping must already exist in the pmap.
  */
 void
 pmap_unwire(pmap_t pmap, vaddr_t va)
+{
 	pt_entry_t *pte;
 #ifdef DEBUG
 	if (pmapdebug & PDB_FOLLOW)
 		printf("pmap_unwire(%p, %lx)\n", pmap, va);
 #endif
 	PMAP_LOCK(pmap);
 	pte = pmap_l3pte(pmap, va, NULL);
 	KASSERT(pte != NULL);
 	KASSERT(pmap_pte_v(pte));
 	/*
 	 * If wiring actually changed (always?) clear the wire bit and
 	 * update the wire count.  Note that wiring is not a hardware

 @@ -1,124 +1,137 @@
-/* $NetBSD: prom.h,v 1.14 2012/02/06 02:14:13 matt Exp $ */
+/* $NetBSD: prom.h,v 1.15 2020/09/03 02:09:09 thorpej Exp $ */
 /*
  * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
  * All rights reserved.
+ *
  * Author: Keith Bostic, Chris G. Demetriou
+ *
  * Permission to use, copy, modify and distribute this software and
  * its documentation is hereby granted, provided that both the copyright
  * notice and this permission notice appear in all copies of the
  * software, derivative works or modified versions, and any portions
  * thereof, and that both notices appear in supporting documentation.
+ *
  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
  * Carnegie Mellon requests users of this software to return to
+ *
  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  *  School of Computer Science
  *  Carnegie Mellon University
  *  Pittsburgh PA 15213-3890
+ *
  * any improvements or extensions that they make and grant Carnegie the
  * rights to redistribute these changes.
  */
 #ifndef	ASSEMBLER
 struct prom_vec {
 	uint64_t	routine;
 	void		*routine_arg;
 };
 /* The return value from a prom call. */
 typedef union {
 	struct {
 		uint64_t
 			retval	: 32,		/* return value. */
 			unit	: 8,
 			mbz	: 8,
 			error	: 13,
 			status	: 3;
 	} u;
 	uint64_t bits;
 } prom_return_t;
 #ifdef _STANDALONE
 int	getchar(void);
 void	putchar(int);
 #endif
 void	prom_halt(int) __attribute__((__noreturn__));
 int	prom_getenv(int, char *, int);
 void	hwrpb_primary_init(void);
 void	hwrpb_restart_setup(void);
 #endif
 /* Prom operation values. */
 #define	PROM_R_CLOSE		0x11
 #define	PROM_R_GETC		0x01
 #define	PROM_R_GETENV		0x22
 #define	PROM_R_OPEN		0x10
 #define	PROM_R_PUTS		0x02
 #define	PROM_R_READ		0x13
 #define	PROM_R_WRITE		0x14
 #define	PROM_R_IOCTL		0x12
 /* Prom IOCTL operation subcodes */
 #define	PROM_I_SKIP2IRG		1
 #define	PROM_I_SKIP2MARK	2
 #define	PROM_I_REWIND		3
 #define	PROM_I_WRITEMARK	4
 /* Environment variable values. */
 #define	PROM_E_BOOTED_DEV	0x4
 #define	PROM_E_BOOTED_FILE	0x6
 #define	PROM_E_BOOTED_OSFLAGS	0x8
 #define	PROM_E_TTY_DEV		0xf
 #define	PROM_E_SCSIID		0x42
 #define	PROM_E_SCSIFAST		0x43
 #if defined(_STANDALONE) || defined(ENABLEPROM)
 /*
  * These can't be called from the kernel without great care.
+ *
  * There have to be stub routines to do the copying that ensures that the
  * PROM doesn't get called with an address larger than 32 bits.  Calls that
  * either don't need to copy anything, or don't need the copy because it's
  * already being done elsewhere, are defined here.
  */
 #define	prom_open(dev, len)						\
 	prom_dispatch(PROM_R_OPEN, (dev), (len), 0, 0)
 #define	prom_close(chan)						\
 	prom_dispatch(PROM_R_CLOSE, chan, 0, 0, 0)
 #define	prom_read(chan, len, buf, blkno)				\
 	prom_dispatch(PROM_R_READ, chan, len, (uint64_t)buf, blkno)
 #define	prom_write(chan, len, buf, blkno)				\
 	prom_dispatch(PROM_R_WRITE, chan, len, (uint64_t)buf, blkno)
 #define	prom_ioctl(chan, op, count)					\
 	prom_dispatch(PROM_R_IOCTL, chan, op, (int64_t)count, 0, 0)
 #define	prom_putstr(chan, str, len)					\
 	prom_dispatch(PROM_R_PUTS, chan, (uint64_t)str, len, 0)
 #define	prom_getc(chan)							\
 	prom_dispatch(PROM_R_GETC, chan, 0, 0, 0)
 #define prom_getenv_disp(id, buf, len)					\
 	prom_dispatch(PROM_R_GETENV, id, (uint64_t)buf, len, 0)
 #endif
 #ifndef ASSEMBLER
 #ifdef _KERNEL
 #ifdef _KERNEL_OPT
 #include "opt_dec_kn8ae.h"
 #if defined(DEC_KN8AE)
 #define _PROM_MAY_USE_PROM_CONSOLE
 #endif /* DEC_KN8AE */
 #endif /* _KERNEL_OPT */
 extern bool prom_interface_initialized;
 bool	prom_uses_prom_console(void);
 void	prom_enter(void);
 void	prom_leave(void);
 void	promcnputc(dev_t, int);
 int	promcngetc(dev_t);
 int	promcnlookc(dev_t, char *);
 uint64_t	prom_dispatch(uint64_t, uint64_t, uint64_t, uint64_t,
 		    uint64_t);
 #endif /* _KERNEL */
 #endif /* ASSEMBLER */

 @@ -1,390 +1,430 @@
-/* $NetBSD: prom.c,v 1.53 2020/08/30 16:26:56 thorpej Exp $ */
+/* $NetBSD: prom.c,v 1.54 2020/09/03 02:09:09 thorpej Exp $ */
 /*
  * Copyright (c) 1992, 1994, 1995, 1996 Carnegie Mellon University
  * All Rights Reserved.
+ *
  * Permission to use, copy, modify and distribute this software and its
  * documentation is hereby granted, provided that both the copyright
  * notice and this permission notice appear in all copies of the
  * software, derivative works or modified versions, and any portions
  * thereof, and that both notices appear in supporting documentation.
+ *
  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
  * Carnegie Mellon requests users of this software to return to
+ *
  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  *  School of Computer Science
  *  Carnegie Mellon University
  *  Pittsburgh PA 15213-3890
+ *
  * any improvements or extensions that they make and grant Carnegie Mellon
  * the rights to redistribute these changes.
  */
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: prom.c,v 1.53 2020/08/30 16:26:56 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: prom.c,v 1.54 2020/09/03 02:09:09 thorpej Exp $");
 #include "opt_multiprocessor.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/proc.h>
 #include <sys/cpu.h>
 #include <uvm/uvm_extern.h>
 #include <machine/rpb.h>
 #include <machine/alpha.h>
 #define	ENABLEPROM
 #include <machine/prom.h>
 #include <dev/cons.h>
 /* XXX this is to fake out the console routines, while booting. */
 struct consdev promcons = {
 	.cn_getc = promcngetc,
 	.cn_putc = promcnputc,
 	.cn_pollc = nullcnpollc,
 	.cn_dev = makedev(23,0),
 	.cn_pri = 1
 };
-struct rpb	*hwrpb;
+struct rpb	*hwrpb __read_mostly;
 int		alpha_console;
 extern struct prom_vec prom_dispatch_v;
-static int	prom_is_qemu;		/* XXX */
+bool		prom_interface_initialized;
 int		prom_mapped = 1;	/* Is PROM still mapped? */
 static bool	prom_is_qemu;		/* XXX */
 static kmutex_t	prom_lock;
-#ifdef _PMAP_MAY_USE_PROM_CONSOLE
+#ifdef _PROM_MAY_USE_PROM_CONSOLE
 int		prom_mapped = 1;	/* Is PROM still mapped? */
 pt_entry_t	prom_pte, saved_pte[1];	/* XXX */
 static pt_entry_t *
 prom_lev1map(void)
+{
 	struct alpha_pcb *apcb;
 	/*
 	 * Find the level 1 map that we're currently running on.
 	 */
 	apcb = (struct alpha_pcb *)ALPHA_PHYS_TO_K0SEG(curpcb);
 	return ((pt_entry_t *)ALPHA_PHYS_TO_K0SEG(apcb->apcb_ptbr << PGSHIFT));
+}
-#endif /* _PMAP_MAY_USE_PROM_CONSOLE */
+#endif /* _PROM_MAY_USE_PROM_CONSOLE */
 bool
 prom_uses_prom_console(void)
+{
 #ifdef _PROM_MAY_USE_PROM_CONSOLE
 	return (cputype == ST_DEC_21000);
 #else
 	return false;
 #endif
+}
 static void
 prom_init_cputype(const struct rpb * const rpb)
+{
 	cputype = rpb->rpb_type;
 	if (cputype < 0) {
 		/*
 		 * At least some white-box systems have SRM which
 		 * reports a systype that's the negative of their
 		 * blue-box counterpart.
 		 */
 		cputype = -cputype;
+	}
+}
 static void
 prom_check_qemu(const struct rpb * const rpb)
+{
 	if (!prom_is_qemu) {
 		if (rpb->rpb_ssn[0] == 'Q' &&
 		    rpb->rpb_ssn[1] == 'E' &&
 		    rpb->rpb_ssn[2] == 'M' &&
 		    rpb->rpb_ssn[3] == 'U') {
-			prom_is_qemu = 1;
+			prom_is_qemu = true;
+		}
+	}
+}
 void
-init_prom_interface(struct rpb *rpb)
+init_prom_interface(u_long ptb_pfn, struct rpb *rpb)
+{
 	static bool prom_interface_initialized;
 	if (prom_interface_initialized)
 		return;
 	struct crb *c;
 	prom_init_cputype(rpb);
 	prom_check_qemu(rpb);
 	c = (struct crb *)((char *)rpb + rpb->rpb_crb_off);
 	prom_dispatch_v.routine_arg = c->crb_v_dispatch;
 	prom_dispatch_v.routine = c->crb_v_dispatch->entry_va;
 #ifdef _PROM_MAY_USE_PROM_CONSOLE
 	if (prom_uses_prom_console()) {
 		/*
 		 * XXX Save old PTE so we can remap the PROM, if
 		 * XXX necessary.
 		 */
 		pt_entry_t * const l1pt =
 		    (pt_entry_t *)ALPHA_PHYS_TO_K0SEG(ptb_pfn << PGSHIFT);
 		prom_pte = l1pt[0] & ~PG_ASM;
+	}
 #endif /* _PROM_MAY_USE_PROM_CONSOLE */
 	mutex_init(&prom_lock, MUTEX_DEFAULT, IPL_HIGH);
 	prom_interface_initialized = true;
+}
 void
 init_bootstrap_console(void)
+{
 	char buf[4];
-	init_prom_interface(hwrpb);
+	/* init_prom_interface() has already been called. */
 	if (! prom_interface_initialized) {
 		prom_halt(1);
+	}
 	prom_getenv(PROM_E_TTY_DEV, buf, sizeof(buf));
 	alpha_console = buf[0] - '0';
 	/* XXX fake out the console routines, for now */
 	cn_tab = &promcons;
+}
-#ifdef _PMAP_MAY_USE_PROM_CONSOLE
+#ifdef _PROM_MAY_USE_PROM_CONSOLE
 static void prom_cache_sync(void);
 #endif
 void
 prom_enter(void)
+{
 	mutex_enter(&prom_lock);
-#ifdef _PMAP_MAY_USE_PROM_CONSOLE
+#ifdef _PROM_MAY_USE_PROM_CONSOLE
 	/*
 	 * If we have not yet switched out of the PROM's context
 	 * (i.e. the first one after alpha_init()), then the PROM
 	 * is still mapped, regardless of the `prom_mapped' setting.
 	 */
 	if (prom_mapped == 0 && curpcb != 0) {
-		if (!pmap_uses_prom_console())
+		if (!prom_uses_prom_console())
 			panic("prom_enter");
+		{
 			pt_entry_t *lev1map;
 			lev1map = prom_lev1map();	/* XXX */
 			saved_pte[0] = lev1map[0];	/* XXX */
 			lev1map[0] = prom_pte;		/* XXX */
+		}
 		prom_cache_sync();			/* XXX */
+	}
 #endif
+}
 void
 prom_leave(void)
+{
-#ifdef _PMAP_MAY_USE_PROM_CONSOLE
+#ifdef _PROM_MAY_USE_PROM_CONSOLE
 	/*
 	 * See comment above.
 	 */
 	if (prom_mapped == 0 && curpcb != 0) {
-		if (!pmap_uses_prom_console())
+		if (!prom_uses_prom_console())
 			panic("prom_leave");
+		{
 			pt_entry_t *lev1map;
 			lev1map = prom_lev1map();	/* XXX */
 			lev1map[0] = saved_pte[0];	/* XXX */
+		}
 		prom_cache_sync();			/* XXX */
+	}
 #endif
 	mutex_exit(&prom_lock);
+}
-#ifdef _PMAP_MAY_USE_PROM_CONSOLE
+#ifdef _PROM_MAY_USE_PROM_CONSOLE
 static void
 prom_cache_sync(void)
+{
 	ALPHA_TBIA();
 	alpha_pal_imb();
+}
 #endif
 /*
  * promcnputc:
+ *
  * Remap char before passing off to prom.
+ *
  * Prom only takes 32 bit addresses. Copy char somewhere prom can
  * find it. This routine will stop working after pmap_rid_of_console
  * is called in alpha_init. This is due to the hard coded address
  * of the console area.
  */
 void
 promcnputc(dev_t dev, int c)
+{
 	prom_return_t ret;
 	unsigned char *to = (unsigned char *)0x20000000;
 	/* XXX */
 	if (prom_is_qemu)
 		return;
 	prom_enter();
 	*to = c;
 	do {
 		ret.bits = prom_putstr(alpha_console, to, 1);
 	} while ((ret.u.retval & 1) == 0);
 	prom_leave();
+}
 /*
  * promcngetc:
+ *
  * Wait for the prom to get a real char and pass it back.
  */
 int
 promcngetc(dev_t dev)
+{
 	prom_return_t ret;
 	/* XXX */
 	if (prom_is_qemu)
 		return 0;
 	for (;;) {
 		prom_enter();
 	        ret.bits = prom_getc(alpha_console);
 		prom_leave();
 	        if (ret.u.status == 0 || ret.u.status == 1)
 	                return (ret.u.retval);
+	}
+}
 /*
  * promcnlookc:
+ *
  * See if prom has a real char and pass it back.
  */
 int
 promcnlookc(dev_t dev, char *cp)
+{
 	prom_return_t ret;
 	/* XXX */
 	if (prom_is_qemu)
 		return 0;
 	prom_enter();
 	ret.bits = prom_getc(alpha_console);
 	prom_leave();
 	if (ret.u.status == 0 || ret.u.status == 1) {
 		*cp = ret.u.retval;
 		return 1;
 	} else
 		return 0;
+}
 int
 prom_getenv(int id, char *buf, int len)
+{
 	unsigned char *to = (unsigned char *)0x20000000;
 	prom_return_t ret;
 	/* XXX */
 	if (prom_is_qemu)
 		return 0;
 	prom_enter();
 	ret.bits = prom_getenv_disp(id, to, len);
 	if (ret.u.status & 0x4)
 		ret.u.retval = 0;
 	len = uimin(len - 1, ret.u.retval);
 	memcpy(buf, to, len);
 	buf[len] = '\0';
 	prom_leave();
 	return len;
+}
 void
 prom_halt(int halt)
+{
 	struct pcs *p;
 	/*
 	 * Turn off interrupts, for sanity.
 	 */
 	(void) splhigh();
 	/*
 	 * Set "boot request" part of the CPU state depending on what
 	 * we want to happen when we halt.
 	 */
 	p = LOCATE_PCS(hwrpb, hwrpb->rpb_primary_cpu_id);
 	p->pcs_flags &= ~(PCS_RC | PCS_HALT_REQ);
 	if (halt)
 		p->pcs_flags |= PCS_HALT_STAY_HALTED;
 	else
 		p->pcs_flags |= PCS_HALT_WARM_BOOT;
 	/*
 	 * Halt the machine.
 	 */
 	alpha_pal_halt();
+}
 uint64_t
 hwrpb_checksum(void)
+{
 	uint64_t *p, sum;
 	int i;
 	for (i = 0, p = (uint64_t *)hwrpb, sum = 0;
 	    i < (offsetof(struct rpb, rpb_checksum) / sizeof (uint64_t));
 	    i++, p++)
 		sum += *p;
 	return (sum);
+}
 void
 hwrpb_primary_init(void)
+{
 	struct pcb *pcb;
 	struct pcs *p;
 	p = LOCATE_PCS(hwrpb, hwrpb->rpb_primary_cpu_id);
 	/* Initialize the primary's HWPCB and the Virtual Page Table Base. */
 	pcb = lwp_getpcb(&lwp0);
 	memcpy(p->pcs_hwpcb, &pcb->pcb_hw, sizeof(pcb->pcb_hw));
 	hwrpb->rpb_vptb = VPTBASE;
 	hwrpb->rpb_checksum = hwrpb_checksum();
+}
 void
 hwrpb_restart_setup(void)
+{
 	struct pcs *p;
 	/* Clear bootstrap-in-progress flag since we're done bootstrapping */
 	p = LOCATE_PCS(hwrpb, hwrpb->rpb_primary_cpu_id);
 	p->pcs_flags &= ~PCS_BIP;
 	/* when 'c'ontinuing from console halt, do a dump */
 	hwrpb->rpb_rest_term = (uint64_t)&XentRestart;
 	hwrpb->rpb_rest_term_val = 0x1;
 	hwrpb->rpb_checksum = hwrpb_checksum();
 	p->pcs_flags |= (PCS_RC | PCS_CV);
+}
 uint64_t
 console_restart(struct trapframe *framep)
+{
 	struct pcs *p;
 	/* Clear restart-capable flag, since we can no longer restart. */
 	p = LOCATE_PCS(hwrpb, hwrpb->rpb_primary_cpu_id);
 	p->pcs_flags &= ~PCS_RC;
 	/* Fill in the missing frame slots */
 	framep->tf_regs[FRAME_PS] = p->pcs_halt_ps;
 	framep->tf_regs[FRAME_PC] = p->pcs_halt_pc;
 	framep->tf_regs[FRAME_T11] = p->pcs_halt_r25;
 	framep->tf_regs[FRAME_RA] = p->pcs_halt_r26;
 	framep->tf_regs[FRAME_T12] = p->pcs_halt_r27;
 	panic("user requested console halt");
 	return (1);
+}