Thu Oct 15 01:00:01 2020 UTC ()
Expose a bunch of CPU details, including implementation version and
architecture extensions, via sysctl:

hw.cpu0.model = 21264A-0 (EV67)
hw.cpu0.major = 11
hw.cpu0.minor = 0
hw.cpu0.implver = 2
hw.cpu0.amask = 0x1307
hw.cpu0.bwx = 1
hw.cpu0.fix = 1
hw.cpu0.cix = 1
hw.cpu0.mvi = 1
hw.cpu0.pat = 1
hw.cpu0.pmi = 1
hw.cpu0.vax_fp = 1
hw.cpu0.ieee_fp = 1
hw.cpu0.primary_eligible = 1
hw.cpu0.primary = 1
hw.cpu0.cpu_id = 0
hw.cpu0.pcc_freq = 239990688

as well as some potentially interesting system-level variables:

machdep.cctr = 0
machdep.is_qemu = 1

Should address the basic concern in PR port-alpha/15835.


(thorpej)
diff -r1.102 -r1.103 src/sys/arch/alpha/alpha/cpu.c
diff -r1.368 -r1.369 src/sys/arch/alpha/alpha/machdep.c
diff -r1.98 -r1.99 src/sys/arch/alpha/include/cpu.h
diff -r1.5 -r1.6 src/sys/arch/alpha/include/cpuvar.h
cvs diff -r1.102 -r1.103 src/sys/arch/alpha/alpha/cpu.c (expand / switch to unified diff)

--- src/sys/arch/alpha/alpha/cpu.c 2020/10/10 03:05:04 1.102
+++ src/sys/arch/alpha/alpha/cpu.c 2020/10/15 01:00:01 1.103
@@ -1,17 +1,17 @@ @@ -1,17 +1,17 @@
1/* $NetBSD: cpu.c,v 1.102 2020/10/10 03:05:04 thorpej Exp $ */ 1/* $NetBSD: cpu.c,v 1.103 2020/10/15 01:00:01 thorpej Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 4 * Copyright (c) 1998, 1999, 2000, 2001, 2020 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center. 9 * NASA Ames Research Center.
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer. 15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright 16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the 17 * notice, this list of conditions and the following disclaimer in the
@@ -49,38 +49,39 @@ @@ -49,38 +49,39 @@
49 * Carnegie Mellon requests users of this software to return to 49 * Carnegie Mellon requests users of this software to return to
50 * 50 *
51 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 51 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
52 * School of Computer Science 52 * School of Computer Science
53 * Carnegie Mellon University 53 * Carnegie Mellon University
54 * Pittsburgh PA 15213-3890 54 * Pittsburgh PA 15213-3890
55 * 55 *
56 * any improvements or extensions that they make and grant Carnegie the 56 * any improvements or extensions that they make and grant Carnegie the
57 * rights to redistribute these changes. 57 * rights to redistribute these changes.
58 */ 58 */
59 59
60#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 60#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
61 61
62__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.102 2020/10/10 03:05:04 thorpej Exp $"); 62__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.103 2020/10/15 01:00:01 thorpej Exp $");
63 63
64#include "opt_ddb.h" 64#include "opt_ddb.h"
65#include "opt_multiprocessor.h" 65#include "opt_multiprocessor.h"
66 66
67#include <sys/param.h> 67#include <sys/param.h>
68#include <sys/systm.h> 68#include <sys/systm.h>
69#include <sys/device.h> 69#include <sys/device.h>
70#include <sys/kmem.h> 70#include <sys/kmem.h>
71#include <sys/proc.h> 71#include <sys/proc.h>
72#include <sys/atomic.h> 72#include <sys/atomic.h>
73#include <sys/cpu.h> 73#include <sys/cpu.h>
 74#include <sys/sysctl.h>
74 75
75#include <uvm/uvm_extern.h> 76#include <uvm/uvm_extern.h>
76 77
77#include <machine/autoconf.h> 78#include <machine/autoconf.h>
78#include <machine/cpuvar.h> 79#include <machine/cpuvar.h>
79#include <machine/rpb.h> 80#include <machine/rpb.h>
80#include <machine/prom.h> 81#include <machine/prom.h>
81#include <machine/alpha.h> 82#include <machine/alpha.h>
82 83
83struct cpu_info cpu_info_primary __cacheline_aligned = { 84struct cpu_info cpu_info_primary __cacheline_aligned = {
84 .ci_curlwp = &lwp0 85 .ci_curlwp = &lwp0
85}; 86};
86struct cpu_info *cpu_info_list = &cpu_info_primary; 87struct cpu_info *cpu_info_list = &cpu_info_primary;
@@ -137,53 +138,171 @@ static int cpumatch(device_t, cfdata_t,  @@ -137,53 +138,171 @@ static int cpumatch(device_t, cfdata_t,
137static void cpuattach(device_t, device_t, void *); 138static void cpuattach(device_t, device_t, void *);
138 139
139CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc), 140CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc),
140 cpumatch, cpuattach, NULL, NULL); 141 cpumatch, cpuattach, NULL, NULL);
141 142
142static void cpu_announce_extensions(struct cpu_info *); 143static void cpu_announce_extensions(struct cpu_info *);
143 144
144extern struct cfdriver cpu_cd; 145extern struct cfdriver cpu_cd;
145 146
146static const char * const lcaminor[] = { 147static const char * const lcaminor[] = {
147 "", 148 "",
148 "21066", "21066", 149 "21066", "21066",
149 "21068", "21068", 150 "21068", "21068",
150 "21066A", "21068A", 0 151 "21066A", "21068A",
 152 NULL
151}; 153};
152 154
153const struct cputable_struct { 155const struct cputable_struct {
154 int cpu_major_code; 156 const char *cpu_evname;
155 const char *cpu_major_name; 157 const char *cpu_major_name;
156 const char * const *cpu_minor_names; 158 const char * const *cpu_minor_names;
157} cpunametable[] = { 159} cpunametable[] = {
158 { PCS_PROC_EV3, "EV3", NULL }, 160[PCS_PROC_EV3] ={ "EV3", NULL, NULL },
159 { PCS_PROC_EV4, "21064", NULL }, 161[PCS_PROC_EV4] ={ "EV4", "21064", NULL },
160 { PCS_PROC_SIMULATION, "Sim", NULL }, 162[PCS_PROC_SIMULATION]={ "Sim", NULL, NULL },
161 { PCS_PROC_LCA4, "LCA", lcaminor }, 163[PCS_PROC_LCA4] ={ "LCA4", NULL, lcaminor },
162 { PCS_PROC_EV5, "21164", NULL }, 164[PCS_PROC_EV5] ={ "EV5", "21164", NULL },
163 { PCS_PROC_EV45, "21064A", NULL }, 165[PCS_PROC_EV45] ={ "EV45", "21064A", NULL },
164 { PCS_PROC_EV56, "21164A", NULL }, 166[PCS_PROC_EV56] ={ "EV56", "21164A", NULL },
165 { PCS_PROC_EV6, "21264", NULL }, 167[PCS_PROC_EV6] ={ "EV6", "21264", NULL },
166 { PCS_PROC_PCA56, "PCA56", NULL }, 168[PCS_PROC_PCA56] ={ "PCA56", "21164PC", NULL },
167 { PCS_PROC_PCA57, "PCA57", NULL }, 169[PCS_PROC_PCA57] ={ "PCA57", "21164PC"/*XXX*/,NULL },
168 { PCS_PROC_EV67, "21264A", NULL }, 170[PCS_PROC_EV67] ={ "EV67", "21264A", NULL },
169 { PCS_PROC_EV68CB, "21264C", NULL }, 171[PCS_PROC_EV68CB] ={ "EV68CB", "21264C", NULL },
170 { PCS_PROC_EV68AL, "21264B", NULL }, 172[PCS_PROC_EV68AL] ={ "EV68AL", "21264B", NULL },
171 { PCS_PROC_EV68CX, "21264D", NULL }, 173[PCS_PROC_EV68CX] ={ "EV68CX", "21264D", NULL },
172 { PCS_PROC_EV7, "21364", NULL }, 174[PCS_PROC_EV7] ={ "EV7", "21364", NULL },
173 { PCS_PROC_EV79, "EV79", NULL }, 175[PCS_PROC_EV79] ={ "EV79", NULL, NULL },
174 { PCS_PROC_EV69, "EV69", NULL }, 176[PCS_PROC_EV69] ={ "EV69", NULL, NULL },
175}; 177};
176 178
 179static bool
 180cpu_description(const struct cpu_softc * const sc,
 181 char * const buf, size_t const buflen)
 182{
 183 const char * const *s;
 184 const char *ev;
 185 int i;
 186
 187 const uint32_t major = sc->sc_major_type;
 188 const uint32_t minor = sc->sc_minor_type;
 189
 190 if (major < __arraycount(cpunametable) &&
 191 (ev = cpunametable[major].cpu_evname) != NULL) {
 192 s = cpunametable[major].cpu_minor_names;
 193 for (i = 0; s != NULL && s[i] != NULL; i++) {
 194 if (i == minor && strlen(s[i]) != 0) {
 195 break;
 196 }
 197 }
 198 if (s == NULL || s[i] == NULL) {
 199 s = &cpunametable[major].cpu_major_name;
 200 i = 0;
 201 if (s[i] == NULL) {
 202 s = NULL;
 203 }
 204 }
 205
 206 /*
 207 * Example strings:
 208 *
 209 * Sim-0
 210 * 21068-3 (LCA4) [uses minor table]
 211 * 21264C-5 (EV68CB)
 212 * 21164PC-1 (PCA56)
 213 */
 214 if (s != NULL) {
 215 snprintf(buf, buflen, "%s-%d (%s)", s[i], minor, ev);
 216 } else {
 217 snprintf(buf, buflen, "%s-%d", ev, minor);
 218 }
 219 return true;
 220 }
 221
 222 snprintf(buf, buflen, "UNKNOWN CPU TYPE (%u:%u)", major, minor);
 223 return false;
 224}
 225
 226static int
 227cpu_sysctl_model(SYSCTLFN_ARGS)
 228{
 229 struct sysctlnode node = *rnode;
 230 const struct cpu_softc * const sc = node.sysctl_data;
 231 char model[32];
 232
 233 cpu_description(sc, model, sizeof(model));
 234 node.sysctl_data = model;
 235 return sysctl_lookup(SYSCTLFN_CALL(&node));
 236}
 237
 238static int
 239cpu_sysctl_amask_bit(SYSCTLFN_ARGS, unsigned long const bit)
 240{
 241 struct sysctlnode node = *rnode;
 242 const struct cpu_softc * const sc = node.sysctl_data;
 243
 244 bool result = (sc->sc_amask & bit) ? true : false;
 245 node.sysctl_data = &result;
 246 return sysctl_lookup(SYSCTLFN_CALL(&node));
 247}
 248
 249static int
 250cpu_sysctl_bwx(SYSCTLFN_ARGS)
 251{
 252 return cpu_sysctl_amask_bit(SYSCTLFN_CALL(rnode), ALPHA_AMASK_BWX);
 253}
 254
 255static int
 256cpu_sysctl_fix(SYSCTLFN_ARGS)
 257{
 258 return cpu_sysctl_amask_bit(SYSCTLFN_CALL(rnode), ALPHA_AMASK_FIX);
 259}
 260
 261static int
 262cpu_sysctl_cix(SYSCTLFN_ARGS)
 263{
 264 return cpu_sysctl_amask_bit(SYSCTLFN_CALL(rnode), ALPHA_AMASK_CIX);
 265}
 266
 267static int
 268cpu_sysctl_mvi(SYSCTLFN_ARGS)
 269{
 270 return cpu_sysctl_amask_bit(SYSCTLFN_CALL(rnode), ALPHA_AMASK_MVI);
 271}
 272
 273static int
 274cpu_sysctl_pat(SYSCTLFN_ARGS)
 275{
 276 return cpu_sysctl_amask_bit(SYSCTLFN_CALL(rnode), ALPHA_AMASK_PAT);
 277}
 278
 279static int
 280cpu_sysctl_pmi(SYSCTLFN_ARGS)
 281{
 282 return cpu_sysctl_amask_bit(SYSCTLFN_CALL(rnode), ALPHA_AMASK_PMI);
 283}
 284
 285static int
 286cpu_sysctl_primary(SYSCTLFN_ARGS)
 287{
 288 struct sysctlnode node = *rnode;
 289 const struct cpu_softc * const sc = node.sysctl_data;
 290
 291 bool result = CPU_IS_PRIMARY(sc->sc_ci);
 292 node.sysctl_data = &result;
 293 return sysctl_lookup(SYSCTLFN_CALL(&node));
 294}
 295
177/* 296/*
178 * The following is an attempt to map out how booting secondary CPUs 297 * The following is an attempt to map out how booting secondary CPUs
179 * works. 298 * works.
180 * 299 *
181 * As we find processors during the autoconfiguration sequence, all 300 * As we find processors during the autoconfiguration sequence, all
182 * processors have idle stacks and PCBs created for them, including 301 * processors have idle stacks and PCBs created for them, including
183 * the primary (although the primary idles on lwp0's PCB until its 302 * the primary (although the primary idles on lwp0's PCB until its
184 * idle PCB is created). 303 * idle PCB is created).
185 * 304 *
186 * Right before calling uvm_scheduler(), main() calls, on lwp0's 305 * Right before calling uvm_scheduler(), main() calls, on lwp0's
187 * context, cpu_boot_secondary_processors(). This is our key to 306 * context, cpu_boot_secondary_processors(). This is our key to
188 * actually spin up the additional processor's we've found. We 307 * actually spin up the additional processor's we've found. We
189 * run through our cpu_info[] array looking for secondary processors 308 * run through our cpu_info[] array looking for secondary processors
@@ -209,152 +328,136 @@ cpumatch(device_t parent, cfdata_t cfdat @@ -209,152 +328,136 @@ cpumatch(device_t parent, cfdata_t cfdat
209 if (strcmp(ma->ma_name, cpu_cd.cd_name) != 0) 328 if (strcmp(ma->ma_name, cpu_cd.cd_name) != 0)
210 return (0); 329 return (0);
211 330
212 /* XXX CHECK SLOT? */ 331 /* XXX CHECK SLOT? */
213 /* XXX CHECK PRIMARY? */ 332 /* XXX CHECK PRIMARY? */
214 333
215 return (1); 334 return (1);
216} 335}
217 336
218static void 337static void
219cpuattach(device_t parent, device_t self, void *aux) 338cpuattach(device_t parent, device_t self, void *aux)
220{ 339{
221 struct cpu_softc * const sc = device_private(self); 340 struct cpu_softc * const sc = device_private(self);
222 struct mainbus_attach_args *ma = aux; 341 const struct mainbus_attach_args * const ma = aux;
223 int i; 
224 const char * const *s; 
225 struct pcs *p; 
226 uint32_t major, minor; 
227 struct cpu_info *ci; 342 struct cpu_info *ci;
 343 char model[32];
 344
 345 const bool primary = ma->ma_slot == hwrpb->rpb_primary_cpu_id;
228 346
229 sc->sc_dev = self; 347 sc->sc_dev = self;
230 348
231 p = LOCATE_PCS(hwrpb, ma->ma_slot); 349 const struct pcs * const p = LOCATE_PCS(hwrpb, ma->ma_slot);
232 major = PCS_CPU_MAJORTYPE(p); 350 sc->sc_major_type = PCS_CPU_MAJORTYPE(p);
233 minor = PCS_CPU_MINORTYPE(p); 351 sc->sc_minor_type = PCS_CPU_MINORTYPE(p);
234 352
235 aprint_normal(": ID %d%s, ", ma->ma_slot, 353 const bool recognized = cpu_description(sc, model, sizeof(model));
236 ma->ma_slot == hwrpb->rpb_primary_cpu_id ? " (primary)" : ""); 354
237 355 aprint_normal(": ID %d%s, ", ma->ma_slot, primary ? " (primary)" : "");
238 for(i = 0; i < __arraycount(cpunametable); ++i) { 356 if (recognized) {
239 if (cpunametable[i].cpu_major_code == major) { 357 aprint_normal("%s", model);
240 aprint_normal("%s-%d", 358 } else {
241 cpunametable[i].cpu_major_name, minor); 359 aprint_error("%s", model);
242 s = cpunametable[i].cpu_minor_names; 
243 for(i = 0; s && s[i]; ++i) { 
244 if (i == minor && strlen(s[i]) != 0) { 
245 aprint_normal(" (%s)", s[i]); 
246 goto recognized; 
247 } 
248 } 
249 goto recognized; 
250 } 
251 } 360 }
252 aprint_error("UNKNOWN CPU TYPE (%d:%d)", major, minor); 
253 361
254recognized: 
255 aprint_naive("\n"); 362 aprint_naive("\n");
256 aprint_normal("\n"); 363 aprint_normal("\n");
257 364
258#ifdef DEBUG 
259 if (p->pcs_proc_var != 0) { 365 if (p->pcs_proc_var != 0) {
260 bool needcomma = false; 366 bool needcomma = false;
261 const char *vaxfp = ""; 367 const char *vaxfp = "";
262 const char *ieeefp = ""; 368 const char *ieeefp = "";
263 const char *pe = ""; 369 const char *pe = "";
264 370
265 if (p->pcs_proc_var & PCS_VAR_VAXFP) { 371 if (p->pcs_proc_var & PCS_VAR_VAXFP) {
 372 sc->sc_vax_fp = true;
266 vaxfp = "VAX FP support"; 373 vaxfp = "VAX FP support";
267 needcomma = true; 374 needcomma = true;
268 } 375 }
269 if (p->pcs_proc_var & PCS_VAR_IEEEFP) { 376 if (p->pcs_proc_var & PCS_VAR_IEEEFP) {
 377 sc->sc_ieee_fp = true;
270 ieeefp = ", IEEE FP support"; 378 ieeefp = ", IEEE FP support";
271 if (!needcomma) 379 if (!needcomma)
272 ieeefp += 2; 380 ieeefp += 2;
273 needcomma = true; 381 needcomma = true;
274 } 382 }
275 if (p->pcs_proc_var & PCS_VAR_PE) { 383 if (p->pcs_proc_var & PCS_VAR_PE) {
 384 sc->sc_primary_eligible = true;
276 pe = ", Primary Eligible"; 385 pe = ", Primary Eligible";
277 if (!needcomma) 386 if (!needcomma)
278 pe += 2; 387 pe += 2;
279 needcomma = true; 388 needcomma = true;
280 } 389 }
281 aprint_debug_dev(sc->sc_dev, "%s%s%s", vaxfp, ieeefp, pe); 390 aprint_debug_dev(sc->sc_dev, "%s%s%s", vaxfp, ieeefp, pe);
282 if (p->pcs_proc_var & PCS_VAR_RESERVED) 391 if (p->pcs_proc_var & PCS_VAR_RESERVED)
283 aprint_debug("%sreserved bits: %#lx", 392 aprint_debug("%sreserved bits: %#lx",
284 needcomma ? ", " : "", 393 needcomma ? ", " : "",
285 p->pcs_proc_var & PCS_VAR_RESERVED); 394 p->pcs_proc_var & PCS_VAR_RESERVED);
286 aprint_debug("\n"); 395 aprint_debug("\n");
287 } 396 }
288#endif 
289 397
290 if (ma->ma_slot > ALPHA_WHAMI_MAXID) { 398 if (ma->ma_slot > ALPHA_WHAMI_MAXID) {
291 if (ma->ma_slot == hwrpb->rpb_primary_cpu_id) 399 if (primary)
292 panic("cpu_attach: primary CPU ID too large"); 400 panic("cpu_attach: primary CPU ID too large");
293 aprint_error_dev(sc->sc_dev, 401 aprint_error_dev(sc->sc_dev,
294 "processor ID too large, ignoring\n"); 402 "processor ID too large, ignoring\n");
295 return; 403 return;
296 } 404 }
297 405
298 if (ma->ma_slot == hwrpb->rpb_primary_cpu_id) 406 if (primary) {
299 ci = &cpu_info_primary; 407 ci = &cpu_info_primary;
300 else { 408 } else {
301 /* 409 /*
302 * kmem_zalloc() will guarante cache line alignment for 410 * kmem_zalloc() will guarante cache line alignment for
303 * all allocations >= CACHE_LINE_SIZE. 411 * all allocations >= CACHE_LINE_SIZE.
304 */ 412 */
305 ci = kmem_zalloc(sizeof(*ci), KM_SLEEP); 413 ci = kmem_zalloc(sizeof(*ci), KM_SLEEP);
306 KASSERT(((uintptr_t)ci & (CACHE_LINE_SIZE - 1)) == 0); 414 KASSERT(((uintptr_t)ci & (CACHE_LINE_SIZE - 1)) == 0);
307 } 415 }
308#if defined(MULTIPROCESSOR) 416#if defined(MULTIPROCESSOR)
309 cpu_info[ma->ma_slot] = ci; 417 cpu_info[ma->ma_slot] = ci;
310#endif 418#endif
311 ci->ci_cpuid = ma->ma_slot; 419 ci->ci_cpuid = ma->ma_slot;
312 ci->ci_softc = sc; 420 ci->ci_softc = sc;
313 ci->ci_pcc_freq = hwrpb->rpb_cc_freq; 421 ci->ci_pcc_freq = hwrpb->rpb_cc_freq;
314 422
315 /* 423 sc->sc_ci = ci;
316 * Though we could (should?) attach the LCA cpus' PCI 
317 * bus here there is no good reason to do so, and 
318 * the bus attachment code is easier to understand 
319 * and more compact if done the 'normal' way. 
320 */ 
321 424
322#if defined(MULTIPROCESSOR) 425#if defined(MULTIPROCESSOR)
323 /* 426 /*
324 * Make sure the processor is available for use. 427 * Make sure the processor is available for use.
325 */ 428 */
326 if ((p->pcs_flags & PCS_PA) == 0) { 429 if ((p->pcs_flags & PCS_PA) == 0) {
327 if (ma->ma_slot == hwrpb->rpb_primary_cpu_id) 430 if (primary)
328 panic("cpu_attach: primary not available?!"); 431 panic("cpu_attach: primary not available?!");
329 aprint_normal_dev(sc->sc_dev, 432 aprint_normal_dev(sc->sc_dev,
330 "processor not available for use\n"); 433 "processor not available for use\n");
331 return; 434 return;
332 } 435 }
333 436
334 /* Make sure the processor has valid PALcode. */ 437 /* Make sure the processor has valid PALcode. */
335 if ((p->pcs_flags & PCS_PV) == 0) { 438 if ((p->pcs_flags & PCS_PV) == 0) {
336 if (ma->ma_slot == hwrpb->rpb_primary_cpu_id) 439 if (primary)
337 panic("cpu_attach: primary has invalid PALcode?!"); 440 panic("cpu_attach: primary has invalid PALcode?!");
338 aprint_error_dev(sc->sc_dev, "PALcode not valid\n"); 441 aprint_error_dev(sc->sc_dev, "PALcode not valid\n");
339 return; 442 return;
340 } 443 }
341#endif /* MULTIPROCESSOR */ 444#endif /* MULTIPROCESSOR */
342 445
343 /* 446 /*
344 * If we're the primary CPU, no more work to do; we're already 447 * If we're the primary CPU, no more work to do; we're already
345 * running! 448 * running!
346 */ 449 */
347 if (ma->ma_slot == hwrpb->rpb_primary_cpu_id) { 450 if (primary) {
348 cpu_announce_extensions(ci); 451 cpu_announce_extensions(ci);
349#if defined(MULTIPROCESSOR) 452#if defined(MULTIPROCESSOR)
350 ci->ci_flags |= CPUF_PRIMARY|CPUF_RUNNING; 453 ci->ci_flags |= CPUF_PRIMARY|CPUF_RUNNING;
351 atomic_or_ulong(&cpus_booted, (1UL << ma->ma_slot)); 454 atomic_or_ulong(&cpus_booted, (1UL << ma->ma_slot));
352 atomic_or_ulong(&cpus_running, (1UL << ma->ma_slot)); 455 atomic_or_ulong(&cpus_running, (1UL << ma->ma_slot));
353#endif /* MULTIPROCESSOR */ 456#endif /* MULTIPROCESSOR */
354 } else { 457 } else {
355#if defined(MULTIPROCESSOR) 458#if defined(MULTIPROCESSOR)
356 int error; 459 int error;
357 460
358 error = mi_cpu_attach(ci); 461 error = mi_cpu_attach(ci);
359 if (error != 0) { 462 if (error != 0) {
360 aprint_error_dev(sc->sc_dev, 463 aprint_error_dev(sc->sc_dev,
@@ -377,57 +480,208 @@ recognized: @@ -377,57 +480,208 @@ recognized:
377#else /* ! MULTIPROCESSOR */ 480#else /* ! MULTIPROCESSOR */
378 aprint_normal_dev(sc->sc_dev, "processor off-line; " 481 aprint_normal_dev(sc->sc_dev, "processor off-line; "
379 "multiprocessor support not present in kernel\n"); 482 "multiprocessor support not present in kernel\n");
380#endif /* MULTIPROCESSOR */ 483#endif /* MULTIPROCESSOR */
381 } 484 }
382 485
383 evcnt_attach_dynamic(&sc->sc_evcnt_clock, EVCNT_TYPE_INTR, 486 evcnt_attach_dynamic(&sc->sc_evcnt_clock, EVCNT_TYPE_INTR,
384 NULL, device_xname(sc->sc_dev), "clock"); 487 NULL, device_xname(sc->sc_dev), "clock");
385 evcnt_attach_dynamic(&sc->sc_evcnt_device, EVCNT_TYPE_INTR, 488 evcnt_attach_dynamic(&sc->sc_evcnt_device, EVCNT_TYPE_INTR,
386 NULL, device_xname(sc->sc_dev), "device"); 489 NULL, device_xname(sc->sc_dev), "device");
387#if defined(MULTIPROCESSOR) 490#if defined(MULTIPROCESSOR)
388 alpha_ipi_init(ci); 491 alpha_ipi_init(ci);
389#endif 492#endif
 493
 494 struct sysctllog **log = &sc->sc_sysctllog;
 495 const struct sysctlnode *rnode, *cnode;
 496 int error;
 497
 498 error = sysctl_createv(log, 0, NULL, &rnode, CTLFLAG_PERMANENT,
 499 CTLTYPE_NODE, device_xname(sc->sc_dev),
 500 SYSCTL_DESCR("cpu properties"),
 501 NULL, 0,
 502 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
 503 if (error)
 504 return;
 505
 506 error = sysctl_createv(log, 0, &rnode, &cnode,
 507 CTLFLAG_PERMANENT, CTLTYPE_STRING, "model",
 508 SYSCTL_DESCR("cpu model"),
 509 cpu_sysctl_model, 0,
 510 (void *)sc, 0, CTL_CREATE, CTL_EOL);
 511 if (error)
 512 return;
 513
 514 error = sysctl_createv(log, 0, &rnode, &cnode,
 515 CTLFLAG_PERMANENT, CTLTYPE_INT, "major",
 516 SYSCTL_DESCR("cpu major type"),
 517 NULL, 0,
 518 &sc->sc_major_type, 0, CTL_CREATE, CTL_EOL);
 519 if (error)
 520 return;
 521
 522 error = sysctl_createv(log, 0, &rnode, &cnode,
 523 CTLFLAG_PERMANENT, CTLTYPE_INT, "minor",
 524 SYSCTL_DESCR("cpu minor type"),
 525 NULL, 0,
 526 &sc->sc_minor_type, 0, CTL_CREATE, CTL_EOL);
 527 if (error)
 528 return;
 529
 530 error = sysctl_createv(log, 0, &rnode, &cnode,
 531 CTLFLAG_PERMANENT, CTLTYPE_LONG, "implver",
 532 SYSCTL_DESCR("cpu implementation version"),
 533 NULL, 0,
 534 &sc->sc_implver, 0, CTL_CREATE, CTL_EOL);
 535 if (error)
 536 return;
 537
 538 error = sysctl_createv(log, 0, &rnode, &cnode,
 539 CTLFLAG_PERMANENT|CTLFLAG_HEX, CTLTYPE_LONG, "amask",
 540 SYSCTL_DESCR("architecture extensions mask"),
 541 NULL, 0,
 542 &sc->sc_amask, 0, CTL_CREATE, CTL_EOL);
 543 if (error)
 544 return;
 545
 546 error = sysctl_createv(log, 0, &rnode, &cnode,
 547 CTLFLAG_PERMANENT, CTLTYPE_BOOL, "bwx",
 548 SYSCTL_DESCR("cpu supports BWX extension"),
 549 cpu_sysctl_bwx, 0,
 550 (void *)sc, 0, CTL_CREATE, CTL_EOL);
 551 if (error)
 552 return;
 553
 554 error = sysctl_createv(log, 0, &rnode, &cnode,
 555 CTLFLAG_PERMANENT, CTLTYPE_BOOL, "fix",
 556 SYSCTL_DESCR("cpu supports FIX extension"),
 557 cpu_sysctl_fix, 0,
 558 (void *)sc, 0, CTL_CREATE, CTL_EOL);
 559 if (error)
 560 return;
 561
 562 error = sysctl_createv(log, 0, &rnode, &cnode,
 563 CTLFLAG_PERMANENT, CTLTYPE_BOOL, "cix",
 564 SYSCTL_DESCR("cpu supports CIX extension"),
 565 cpu_sysctl_cix, 0,
 566 (void *)sc, 0, CTL_CREATE, CTL_EOL);
 567 if (error)
 568 return;
 569
 570 error = sysctl_createv(log, 0, &rnode, &cnode,
 571 CTLFLAG_PERMANENT, CTLTYPE_BOOL, "mvi",
 572 SYSCTL_DESCR("cpu supports MVI extension"),
 573 cpu_sysctl_mvi, 0,
 574 (void *)sc, 0, CTL_CREATE, CTL_EOL);
 575 if (error)
 576 return;
 577
 578 error = sysctl_createv(log, 0, &rnode, &cnode,
 579 CTLFLAG_PERMANENT, CTLTYPE_BOOL, "pat",
 580 SYSCTL_DESCR("cpu supports PAT extension"),
 581 cpu_sysctl_pat, 0,
 582 (void *)sc, 0, CTL_CREATE, CTL_EOL);
 583 if (error)
 584 return;
 585
 586 error = sysctl_createv(log, 0, &rnode, &cnode,
 587 CTLFLAG_PERMANENT, CTLTYPE_BOOL, "pmi",
 588 SYSCTL_DESCR("cpu supports PMI extension"),
 589 cpu_sysctl_pmi, 0,
 590 (void *)sc, 0, CTL_CREATE, CTL_EOL);
 591 if (error)
 592 return;
 593
 594 error = sysctl_createv(log, 0, &rnode, &cnode,
 595 CTLFLAG_PERMANENT, CTLTYPE_BOOL, "vax_fp",
 596 SYSCTL_DESCR("cpu supports VAX FP"),
 597 NULL, 0,
 598 &sc->sc_vax_fp, 0, CTL_CREATE, CTL_EOL);
 599 if (error)
 600 return;
 601
 602 error = sysctl_createv(log, 0, &rnode, &cnode,
 603 CTLFLAG_PERMANENT, CTLTYPE_BOOL, "ieee_fp",
 604 SYSCTL_DESCR("cpu supports IEEE FP"),
 605 NULL, 0,
 606 &sc->sc_ieee_fp, 0, CTL_CREATE, CTL_EOL);
 607 if (error)
 608 return;
 609
 610 error = sysctl_createv(log, 0, &rnode, &cnode,
 611 CTLFLAG_PERMANENT, CTLTYPE_BOOL, "primary_eligible",
 612 SYSCTL_DESCR("cpu is primary-eligible"),
 613 NULL, 0,
 614 &sc->sc_primary_eligible, 0, CTL_CREATE, CTL_EOL);
 615 if (error)
 616 return;
 617
 618 error = sysctl_createv(log, 0, &rnode, &cnode,
 619 CTLFLAG_PERMANENT, CTLTYPE_BOOL, "primary",
 620 SYSCTL_DESCR("cpu is the primary cpu"),
 621 cpu_sysctl_primary, 0,
 622 (void *)sc, 0, CTL_CREATE, CTL_EOL);
 623 if (error)
 624 return;
 625
 626 error = sysctl_createv(log, 0, &rnode, &cnode,
 627 CTLFLAG_PERMANENT, CTLTYPE_LONG, "cpu_id",
 628 SYSCTL_DESCR("hardware cpu ID"),
 629 NULL, 0,
 630 &sc->sc_ci->ci_cpuid, 0, CTL_CREATE, CTL_EOL);
 631 if (error)
 632 return;
 633
 634 error = sysctl_createv(log, 0, &rnode, &cnode,
 635 CTLFLAG_PERMANENT, CTLTYPE_LONG, "pcc_freq",
 636 SYSCTL_DESCR("PCC frequency"),
 637 NULL, 0,
 638 &sc->sc_ci->ci_pcc_freq, 0, CTL_CREATE, CTL_EOL);
 639 if (error)
 640 return;
390} 641}
391 642
392static void 643static void
393cpu_announce_extensions(struct cpu_info *ci) 644cpu_announce_extensions(struct cpu_info *ci)
394{ 645{
395 u_long implver, amask = 0; 646 u_long implver, amask = 0;
396 char bits[64]; 647 char bits[64];
397 648
398 implver = alpha_implver(); 649 implver = alpha_implver();
399 if (implver >= ALPHA_IMPLVER_EV5) 650 if (implver >= ALPHA_IMPLVER_EV5)
400 amask = (~alpha_amask(ALPHA_AMASK_ALL)) & ALPHA_AMASK_ALL; 651 amask = (~alpha_amask(ALPHA_AMASK_ALL)) & ALPHA_AMASK_ALL;
401 652
 653 ci->ci_softc->sc_implver = implver;
 654 ci->ci_softc->sc_amask = amask;
 655
402 if (ci->ci_cpuid == hwrpb->rpb_primary_cpu_id) { 656 if (ci->ci_cpuid == hwrpb->rpb_primary_cpu_id) {
403 cpu_implver = implver; 657 cpu_implver = implver;
404 cpu_amask = amask; 658 cpu_amask = amask;
405 } else { 659 } else {
406 if (implver < cpu_implver) 660 if (implver < cpu_implver)
407 aprint_error_dev(ci->ci_softc->sc_dev, 661 aprint_error_dev(ci->ci_softc->sc_dev,
408 "WARNING: IMPLVER %lu < %lu\n", 662 "WARNING: IMPLVER %lu < %lu\n",
409 implver, cpu_implver); 663 implver, cpu_implver);
410 664
411 /* 665 /*
412 * Cap the system architecture mask to the intersection 666 * Cap the system architecture mask to the intersection
413 * of features supported by all processors in the system. 667 * of features supported by all processors in the system.
414 */ 668 */
415 cpu_amask &= amask; 669 cpu_amask &= amask;
416 } 670 }
417 671
418 if (amask) { 672 if (amask) {
419 snprintb(bits, sizeof(bits), 673 snprintb(bits, sizeof(bits),
420 ALPHA_AMASK_BITS, cpu_amask); 674 ALPHA_AMASK_BITS, amask);
421 aprint_normal_dev(ci->ci_softc->sc_dev, 675 aprint_normal_dev(ci->ci_softc->sc_dev,
422 "Architecture extensions: %s\n", bits); 676 "Architecture extensions: %s\n", bits);
423 } 677 }
424} 678}
425 679
426#if defined(MULTIPROCESSOR) 680#if defined(MULTIPROCESSOR)
427void 681void
428cpu_boot_secondary_processors(void) 682cpu_boot_secondary_processors(void)
429{ 683{
430 struct cpu_info *ci; 684 struct cpu_info *ci;
431 u_long i; 685 u_long i;
432 bool did_patch = false; 686 bool did_patch = false;
433 687
cvs diff -r1.368 -r1.369 src/sys/arch/alpha/alpha/machdep.c (expand / switch to unified diff)

--- src/sys/arch/alpha/alpha/machdep.c 2020/10/14 00:59:50 1.368
+++ src/sys/arch/alpha/alpha/machdep.c 2020/10/15 01:00:01 1.369
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: machdep.c,v 1.368 2020/10/14 00:59:50 thorpej Exp $ */ 1/* $NetBSD: machdep.c,v 1.369 2020/10/15 01:00:01 thorpej Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 1998, 1999, 2000, 2019, 2020 The NetBSD Foundation, Inc. 4 * Copyright (c) 1998, 1999, 2000, 2019, 2020 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center and by Chris G. Demetriou. 9 * NASA Ames Research Center and by Chris G. Demetriou.
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
@@ -57,27 +57,27 @@ @@ -57,27 +57,27 @@
57 * rights to redistribute these changes. 57 * rights to redistribute these changes.
58 */ 58 */
59 59
60#include "opt_ddb.h" 60#include "opt_ddb.h"
61#include "opt_kgdb.h" 61#include "opt_kgdb.h"
62#include "opt_modular.h" 62#include "opt_modular.h"
63#include "opt_multiprocessor.h" 63#include "opt_multiprocessor.h"
64#include "opt_dec_3000_300.h" 64#include "opt_dec_3000_300.h"
65#include "opt_dec_3000_500.h" 65#include "opt_dec_3000_500.h"
66#include "opt_execfmt.h" 66#include "opt_execfmt.h"
67 67
68#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
69 69
70__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.368 2020/10/14 00:59:50 thorpej Exp $"); 70__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.369 2020/10/15 01:00:01 thorpej Exp $");
71 71
72#include <sys/param.h> 72#include <sys/param.h>
73#include <sys/systm.h> 73#include <sys/systm.h>
74#include <sys/signalvar.h> 74#include <sys/signalvar.h>
75#include <sys/kernel.h> 75#include <sys/kernel.h>
76#include <sys/cpu.h> 76#include <sys/cpu.h>
77#include <sys/proc.h> 77#include <sys/proc.h>
78#include <sys/ras.h> 78#include <sys/ras.h>
79#include <sys/sched.h> 79#include <sys/sched.h>
80#include <sys/reboot.h> 80#include <sys/reboot.h>
81#include <sys/device.h> 81#include <sys/device.h>
82#include <sys/malloc.h> 82#include <sys/malloc.h>
83#include <sys/module.h> 83#include <sys/module.h>
@@ -1618,26 +1618,36 @@ SYSCTL_SETUP(sysctl_machdep_setup, "sysc @@ -1618,26 +1618,36 @@ SYSCTL_SETUP(sysctl_machdep_setup, "sysc
1618 SYSCTL_DESCR("Do SIGBUS for fixed unaligned accesses"), 1618 SYSCTL_DESCR("Do SIGBUS for fixed unaligned accesses"),
1619 NULL, 0, &alpha_unaligned_sigbus, 0, 1619 NULL, 0, &alpha_unaligned_sigbus, 0,
1620 CTL_MACHDEP, CPU_UNALIGNED_SIGBUS, CTL_EOL); 1620 CTL_MACHDEP, CPU_UNALIGNED_SIGBUS, CTL_EOL);
1621 sysctl_createv(clog, 0, NULL, NULL, 1621 sysctl_createv(clog, 0, NULL, NULL,
1622 CTLFLAG_PERMANENT, 1622 CTLFLAG_PERMANENT,
1623 CTLTYPE_STRING, "booted_kernel", NULL, 1623 CTLTYPE_STRING, "booted_kernel", NULL,
1624 NULL, 0, bootinfo.booted_kernel, 0, 1624 NULL, 0, bootinfo.booted_kernel, 0,
1625 CTL_MACHDEP, CPU_BOOTED_KERNEL, CTL_EOL); 1625 CTL_MACHDEP, CPU_BOOTED_KERNEL, CTL_EOL);
1626 sysctl_createv(clog, 0, NULL, NULL, 1626 sysctl_createv(clog, 0, NULL, NULL,
1627 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 1627 CTLFLAG_PERMANENT|CTLFLAG_READWRITE,
1628 CTLTYPE_INT, "fp_sync_complete", NULL, 1628 CTLTYPE_INT, "fp_sync_complete", NULL,
1629 NULL, 0, &alpha_fp_sync_complete, 0, 1629 NULL, 0, &alpha_fp_sync_complete, 0,
1630 CTL_MACHDEP, CPU_FP_SYNC_COMPLETE, CTL_EOL); 1630 CTL_MACHDEP, CPU_FP_SYNC_COMPLETE, CTL_EOL);
 1631 sysctl_createv(clog, 0, NULL, NULL,
 1632 CTLFLAG_PERMANENT,
 1633 CTLTYPE_INT, "cctr", NULL,
 1634 NULL, 0, &alpha_use_cctr, 0,
 1635 CTL_MACHDEP, CPU_CCTR, CTL_EOL);
 1636 sysctl_createv(clog, 0, NULL, NULL,
 1637 CTLFLAG_PERMANENT,
 1638 CTLTYPE_BOOL, "is_qemu", NULL,
 1639 NULL, 0, &alpha_is_qemu, 0,
 1640 CTL_MACHDEP, CPU_IS_QEMU, CTL_EOL);
1631} 1641}
1632 1642
1633/* 1643/*
1634 * Set registers on exec. 1644 * Set registers on exec.
1635 */ 1645 */
1636void 1646void
1637setregs(register struct lwp *l, struct exec_package *pack, vaddr_t stack) 1647setregs(register struct lwp *l, struct exec_package *pack, vaddr_t stack)
1638{ 1648{
1639 struct trapframe *tfp = l->l_md.md_tf; 1649 struct trapframe *tfp = l->l_md.md_tf;
1640 struct pcb *pcb; 1650 struct pcb *pcb;
1641#ifdef DEBUG 1651#ifdef DEBUG
1642 int i; 1652 int i;
1643#endif 1653#endif
cvs diff -r1.98 -r1.99 src/sys/arch/alpha/include/cpu.h (expand / switch to unified diff)

--- src/sys/arch/alpha/include/cpu.h 2020/09/29 01:33:00 1.98
+++ src/sys/arch/alpha/include/cpu.h 2020/10/15 01:00:01 1.99
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpu.h,v 1.98 2020/09/29 01:33:00 thorpej Exp $ */ 1/* $NetBSD: cpu.h,v 1.99 2020/10/15 01:00:01 thorpej Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center, and by Charles M. Hannum. 9 * NASA Ames Research Center, and by Charles M. Hannum.
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
@@ -219,26 +219,29 @@ void cpu_signotify(struct lwp *); @@ -219,26 +219,29 @@ void cpu_signotify(struct lwp *);
219#define aston(l) ((l)->l_md.md_astpending = 1) 219#define aston(l) ((l)->l_md.md_astpending = 1)
220#endif /* _KERNEL */ 220#endif /* _KERNEL */
221 221
222/* 222/*
223 * CTL_MACHDEP definitions. 223 * CTL_MACHDEP definitions.
224 */ 224 */
225#define CPU_CONSDEV 1 /* dev_t: console terminal device */ 225#define CPU_CONSDEV 1 /* dev_t: console terminal device */
226#define CPU_ROOT_DEVICE 2 /* string: root device name */ 226#define CPU_ROOT_DEVICE 2 /* string: root device name */
227#define CPU_UNALIGNED_PRINT 3 /* int: print unaligned accesses */ 227#define CPU_UNALIGNED_PRINT 3 /* int: print unaligned accesses */
228#define CPU_UNALIGNED_FIX 4 /* int: fix unaligned accesses */ 228#define CPU_UNALIGNED_FIX 4 /* int: fix unaligned accesses */
229#define CPU_UNALIGNED_SIGBUS 5 /* int: SIGBUS unaligned accesses */ 229#define CPU_UNALIGNED_SIGBUS 5 /* int: SIGBUS unaligned accesses */
230#define CPU_BOOTED_KERNEL 6 /* string: booted kernel name */ 230#define CPU_BOOTED_KERNEL 6 /* string: booted kernel name */
231#define CPU_FP_SYNC_COMPLETE 7 /* int: always fixup sync fp traps */ 231#define CPU_FP_SYNC_COMPLETE 7 /* int: always fixup sync fp traps */
 232#define CPU_CCTR 8 /* int: using CC timecounter */
 233#define CPU_IS_QEMU 9 /* int: running under Qemu */
 234
232 235
233#ifdef _KERNEL 236#ifdef _KERNEL
234 237
235struct pcb; 238struct pcb;
236struct proc; 239struct proc;
237struct reg; 240struct reg;
238struct rpb; 241struct rpb;
239struct trapframe; 242struct trapframe;
240 243
241int badaddr(void *, size_t); 244int badaddr(void *, size_t);
242void * cpu_uarea_alloc(bool); 245void * cpu_uarea_alloc(bool);
243bool cpu_uarea_free(void *); 246bool cpu_uarea_free(void *);
244 247
cvs diff -r1.5 -r1.6 src/sys/arch/alpha/include/cpuvar.h (expand / switch to unified diff)

--- src/sys/arch/alpha/include/cpuvar.h 2011/06/14 15:34:22 1.5
+++ src/sys/arch/alpha/include/cpuvar.h 2020/10/15 01:00:01 1.6
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpuvar.h,v 1.5 2011/06/14 15:34:22 matt Exp $ */ 1/* $NetBSD: cpuvar.h,v 1.6 2020/10/15 01:00:01 thorpej Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 4 * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe. 8 * by Jason R. Thorpe.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -23,20 +23,35 @@ @@ -23,20 +23,35 @@
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE. 29 * POSSIBILITY OF SUCH DAMAGE.
30 */ 30 */
31 31
32#include "opt_multiprocessor.h" 32#include "opt_multiprocessor.h"
33 33
34struct cpu_softc { 34struct cpu_softc {
35 device_t sc_dev; /* base device */ 35 device_t sc_dev; /* base device */
 36 struct cpu_info *sc_ci; /* our cpu_info structure */
 37
 38 /* Info exported to user-space. */
 39 uint32_t sc_major_type; /* CPU major type */
 40 uint32_t sc_minor_type; /* CPU minor type */
 41 bool sc_vax_fp; /* supports VAX FP */
 42 bool sc_ieee_fp; /* supports IEEE FP */
 43 bool sc_primary_eligible; /* CPU is primary eligible */
 44
 45 /* These are only valid if the CPU runs kernel code. */
 46 u_long sc_amask; /* AMASK bits (inverted) */
 47 u_long sc_implver; /* IMPLVER */
 48
 49 struct sysctllog *sc_sysctllog;
 50
36 struct evcnt sc_evcnt_clock; /* clock interrupts */ 51 struct evcnt sc_evcnt_clock; /* clock interrupts */
37 struct evcnt sc_evcnt_device; /* device interrupts */ 52 struct evcnt sc_evcnt_device; /* device interrupts */
38#if defined(MULTIPROCESSOR) 53#if defined(MULTIPROCESSOR)
39 struct evcnt sc_evcnt_ipi; /* interprocessor interrupts */ 54 struct evcnt sc_evcnt_ipi; /* interprocessor interrupts */
40 struct evcnt sc_evcnt_which_ipi[ALPHA_NIPIS]; 55 struct evcnt sc_evcnt_which_ipi[ALPHA_NIPIS];
41#endif 56#endif
42}; 57};