 @@ -1,1084 +1,1084 @@
-/*	$NetBSD: if_wm.c,v 1.691 2020/10/16 05:53:39 msaitoh Exp $	*/
+/*	$NetBSD: if_wm.c,v 1.692 2020/10/28 07:08:08 msaitoh Exp $	*/
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed for the NetBSD Project by
  *	Wasabi Systems, Inc.
  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  *    or promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*******************************************************************************
   Copyright (c) 2001-2005, Intel Corporation
   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
 . Redistributions of source code must retain the above copyright notice,
       this list of conditions and the following disclaimer.
 . Redistributions in binary form must reproduce the above copyright
       notice, this list of conditions and the following disclaimer in the
       documentation and/or other materials provided with the distribution.
 . Neither the name of the Intel Corporation nor the names of its
       contributors may be used to endorse or promote products derived from
       this software without specific prior written permission.
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************/
 /*
  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
+ *
  * TODO (in order of importance):
+ *
  *	- Check XXX'ed comments
  *	- TX Multi queue improvement (refine queue selection logic)
  *	- Split header buffer for newer descriptors
  *	- EEE (Energy Efficiency Ethernet) for I354
  *	- Virtual Function
  *	- Set LED correctly (based on contents in EEPROM)
  *	- Rework how parameters are loaded from the EEPROM.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.691 2020/10/16 05:53:39 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.692 2020/10/28 07:08:08 msaitoh Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_net_mpsafe.h"
 #include "opt_if_wm.h"
 #endif
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kmem.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <sys/queue.h>
 #include <sys/syslog.h>
 #include <sys/interrupt.h>
 #include <sys/cpu.h>
 #include <sys/pcq.h>
 #include <sys/sysctl.h>
 #include <sys/workqueue.h>
 #include <sys/rndsource.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/if_ether.h>
 #include <net/bpf.h>
 #include <net/rss_config.h>
 #include <netinet/in.h>			/* XXX for struct ip */
 #include <netinet/in_systm.h>		/* XXX for struct ip */
 #include <netinet/ip.h>			/* XXX for struct ip */
 #include <netinet/ip6.h>		/* XXX for struct ip6_hdr */
 #include <netinet/tcp.h>		/* XXX for struct tcphdr */
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <machine/endian.h>
 #include <dev/mii/mii.h>
 #include <dev/mii/mdio.h>
 #include <dev/mii/miivar.h>
 #include <dev/mii/miidevs.h>
 #include <dev/mii/mii_bitbang.h>
 #include <dev/mii/ikphyreg.h>
 #include <dev/mii/igphyreg.h>
 #include <dev/mii/igphyvar.h>
 #include <dev/mii/inbmphyreg.h>
 #include <dev/mii/ihphyreg.h>
 #include <dev/mii/makphyreg.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/if_wmreg.h>
 #include <dev/pci/if_wmvar.h>
 #ifdef WM_DEBUG
 #define	WM_DEBUG_LINK		__BIT(0)
 #define	WM_DEBUG_TX		__BIT(1)
 #define	WM_DEBUG_RX		__BIT(2)
 #define	WM_DEBUG_GMII		__BIT(3)
 #define	WM_DEBUG_MANAGE		__BIT(4)
 #define	WM_DEBUG_NVM		__BIT(5)
 #define	WM_DEBUG_INIT		__BIT(6)
 #define	WM_DEBUG_LOCK		__BIT(7)
 int	wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII
     | WM_DEBUG_MANAGE | WM_DEBUG_NVM | WM_DEBUG_INIT | WM_DEBUG_LOCK;
 #define	DPRINTF(x, y)	do { if (wm_debug & (x)) printf y; } while (0)
 #else
 #define	DPRINTF(x, y)	__nothing
 #endif /* WM_DEBUG */
 #ifdef NET_MPSAFE
 #define WM_MPSAFE	1
 #define WM_CALLOUT_FLAGS	CALLOUT_MPSAFE
 #define WM_SOFTINT_FLAGS	SOFTINT_MPSAFE
 #define WM_WORKQUEUE_FLAGS	WQ_PERCPU | WQ_MPSAFE
 #else
 #define WM_CALLOUT_FLAGS	0
 #define WM_SOFTINT_FLAGS	0
 #define WM_WORKQUEUE_FLAGS	WQ_PERCPU
 #endif
 #define WM_WORKQUEUE_PRI PRI_SOFTNET
 /*
  * This device driver's max interrupt numbers.
  */
 #define WM_MAX_NQUEUEINTR	16
 #define WM_MAX_NINTR		(WM_MAX_NQUEUEINTR + 1)
 #ifndef WM_DISABLE_MSI
 #define	WM_DISABLE_MSI 0
 #endif
 #ifndef WM_DISABLE_MSIX
 #define	WM_DISABLE_MSIX 0
 #endif
 int wm_disable_msi = WM_DISABLE_MSI;
 int wm_disable_msix = WM_DISABLE_MSIX;
 #ifndef WM_WATCHDOG_TIMEOUT
 #define WM_WATCHDOG_TIMEOUT 5
 #endif
 static int wm_watchdog_timeout = WM_WATCHDOG_TIMEOUT;
 /*
  * Transmit descriptor list size.  Due to errata, we can only have
  * 256 hardware descriptors in the ring on < 82544, but we use 4096
  * on >= 82544. We tell the upper layers that they can queue a lot
  * of packets, and we go ahead and manage up to 64 (16 for the i82547)
  * of them at a time.
+ *
  * We allow up to 64 DMA segments per packet.  Pathological packet
  * chains containing many small mbufs have been observed in zero-copy
  * situations with jumbo frames. If a mbuf chain has more than 64 DMA segments,
  * m_defrag() is called to reduce it.
  */
 #define	WM_NTXSEGS		64
 #define	WM_IFQUEUELEN		256
 #define	WM_TXQUEUELEN_MAX	64
 #define	WM_TXQUEUELEN_MAX_82547	16
 #define	WM_TXQUEUELEN(txq)	((txq)->txq_num)
 #define	WM_TXQUEUELEN_MASK(txq)	(WM_TXQUEUELEN(txq) - 1)
 #define	WM_TXQUEUE_GC(txq)	(WM_TXQUEUELEN(txq) / 8)
 #define	WM_NTXDESC_82542	256
 #define	WM_NTXDESC_82544	4096
 #define	WM_NTXDESC(txq)		((txq)->txq_ndesc)
 #define	WM_NTXDESC_MASK(txq)	(WM_NTXDESC(txq) - 1)
 #define	WM_TXDESCS_SIZE(txq)	(WM_NTXDESC(txq) * (txq)->txq_descsize)
 #define	WM_NEXTTX(txq, x)	(((x) + 1) & WM_NTXDESC_MASK(txq))
 #define	WM_NEXTTXS(txq, x)	(((x) + 1) & WM_TXQUEUELEN_MASK(txq))
 #define	WM_MAXTXDMA		 (2 * round_page(IP_MAXPACKET)) /* for TSO */
 #define	WM_TXINTERQSIZE		256
 #ifndef WM_TX_PROCESS_LIMIT_DEFAULT
 #define	WM_TX_PROCESS_LIMIT_DEFAULT		100U
 #endif
 #ifndef WM_TX_INTR_PROCESS_LIMIT_DEFAULT
 #define	WM_TX_INTR_PROCESS_LIMIT_DEFAULT	0U
 #endif
 /*
  * Receive descriptor list size.  We have one Rx buffer for normal
  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
  * packet.  We allocate 256 receive descriptors, each with a 2k
  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
  */
 #define	WM_NRXDESC		256U
 #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
 #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
 #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
 #ifndef WM_RX_PROCESS_LIMIT_DEFAULT
 #define	WM_RX_PROCESS_LIMIT_DEFAULT		100U
 #endif
 #ifndef WM_RX_INTR_PROCESS_LIMIT_DEFAULT
 #define	WM_RX_INTR_PROCESS_LIMIT_DEFAULT	0U
 #endif
 typedef union txdescs {
 	wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544];
 	nq_txdesc_t	 sctxu_nq_txdescs[WM_NTXDESC_82544];
 } txdescs_t;
 typedef union rxdescs {
 	wiseman_rxdesc_t sctxu_rxdescs[WM_NRXDESC];
 	ext_rxdesc_t	  sctxu_ext_rxdescs[WM_NRXDESC]; /* 82574 only */
 	nq_rxdesc_t	 sctxu_nq_rxdescs[WM_NRXDESC]; /* 82575 and newer */
 } rxdescs_t;
 #define	WM_CDTXOFF(txq, x)	((txq)->txq_descsize * (x))
 #define	WM_CDRXOFF(rxq, x)	((rxq)->rxq_descsize * (x))
 /*
  * Software state for transmit jobs.
  */
 struct wm_txsoft {
 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t txs_dmamap;	/* our DMA map */
 	int txs_firstdesc;		/* first descriptor in packet */
 	int txs_lastdesc;		/* last descriptor in packet */
 	int txs_ndesc;			/* # of descriptors used */
 };
 /*
  * Software state for receive buffers. Each descriptor gets a 2k (MCLBYTES)
  * buffer and a DMA map. For packets which fill more than one buffer, we chain
  * them together.
  */
 struct wm_rxsoft {
 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
 };
 #define WM_LINKUP_TIMEOUT	50
 static uint16_t swfwphysem[] = {
 	SWFW_PHY0_SM,
 	SWFW_PHY1_SM,
 	SWFW_PHY2_SM,
 	SWFW_PHY3_SM
 };
 static const uint32_t wm_82580_rxpbs_table[] = {
 , 72, 144, 1, 2, 4, 8, 16, 35, 70, 140
 };
 struct wm_softc;
 #ifdef WM_EVENT_COUNTERS
 #define WM_Q_EVCNT_DEFINE(qname, evname)				\
 	char qname##_##evname##_evcnt_name[sizeof("qname##XX##evname")]; \
 	struct evcnt qname##_ev_##evname;
 #define WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, evtype)	\
 	do {								\
 		snprintf((q)->qname##_##evname##_evcnt_name,		\
 		    sizeof((q)->qname##_##evname##_evcnt_name),		\
 		    "%s%02d%s", #qname, (qnum), #evname);		\
 		evcnt_attach_dynamic(&(q)->qname##_ev_##evname,		\
 		    (evtype), NULL, (xname),				\
 		    (q)->qname##_##evname##_evcnt_name);		\
 	} while (0)
 #define WM_Q_MISC_EVCNT_ATTACH(qname, evname, q, qnum, xname)		\
 	WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, EVCNT_TYPE_MISC)
 #define WM_Q_INTR_EVCNT_ATTACH(qname, evname, q, qnum, xname)		\
 	WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, EVCNT_TYPE_INTR)
 #define WM_Q_EVCNT_DETACH(qname, evname, q, qnum)	\
 	evcnt_detach(&(q)->qname##_ev_##evname);
 #endif /* WM_EVENT_COUNTERS */
 struct wm_txqueue {
 	kmutex_t *txq_lock;		/* lock for tx operations */
 	struct wm_softc *txq_sc;	/* shortcut (skip struct wm_queue) */
 	/* Software state for the transmit descriptors. */
 	int txq_num;			/* must be a power of two */
 	struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX];
 	/* TX control data structures. */
 	int txq_ndesc;			/* must be a power of two */
 	size_t txq_descsize;		/* a tx descriptor size */
 	txdescs_t *txq_descs_u;
 	bus_dmamap_t txq_desc_dmamap;	/* control data DMA map */
 	bus_dma_segment_t txq_desc_seg;	/* control data segment */
 	int txq_desc_rseg;		/* real number of control segment */
 #define	txq_desc_dma	txq_desc_dmamap->dm_segs[0].ds_addr
 #define	txq_descs	txq_descs_u->sctxu_txdescs
 #define	txq_nq_descs	txq_descs_u->sctxu_nq_txdescs
 	bus_addr_t txq_tdt_reg;		/* offset of TDT register */
 	int txq_free;			/* number of free Tx descriptors */
 	int txq_next;			/* next ready Tx descriptor */
 	int txq_sfree;			/* number of free Tx jobs */
 	int txq_snext;			/* next free Tx job */
 	int txq_sdirty;			/* dirty Tx jobs */
 	/* These 4 variables are used only on the 82547. */
 	int txq_fifo_size;		/* Tx FIFO size */
 	int txq_fifo_head;		/* current head of FIFO */
 	uint32_t txq_fifo_addr;		/* internal address of start of FIFO */
 	int txq_fifo_stall;		/* Tx FIFO is stalled */
 	/*
 	 * When ncpu > number of Tx queues, a Tx queue is shared by multiple
 	 * CPUs. This queue intermediate them without block.
 	 */
 	pcq_t *txq_interq;
 	/*
 	 * NEWQUEUE devices must use not ifp->if_flags but txq->txq_flags
 	 * to manage Tx H/W queue's busy flag.
 	 */
 	int txq_flags;			/* flags for H/W queue, see below */
 #define	WM_TXQ_NO_SPACE	0x1
 	bool txq_stopping;
 	bool txq_sending;
 	time_t txq_lastsent;
 	/* Checksum flags used for previous packet */
 	uint32_t 	txq_last_hw_cmd;
 	uint8_t 	txq_last_hw_fields;
 	uint16_t	txq_last_hw_ipcs;
 	uint16_t	txq_last_hw_tucs;
 	uint32_t txq_packets;		/* for AIM */
 	uint32_t txq_bytes;		/* for AIM */
 #ifdef WM_EVENT_COUNTERS
 	/* TX event counters */
 	WM_Q_EVCNT_DEFINE(txq, txsstall)    /* Stalled due to no txs */
 	WM_Q_EVCNT_DEFINE(txq, txdstall)    /* Stalled due to no txd */
 	WM_Q_EVCNT_DEFINE(txq, fifo_stall)  /* FIFO stalls (82547) */
 	WM_Q_EVCNT_DEFINE(txq, txdw)	    /* Tx descriptor interrupts */
 	WM_Q_EVCNT_DEFINE(txq, txqe)	    /* Tx queue empty interrupts */
 					    /* XXX not used? */
 	WM_Q_EVCNT_DEFINE(txq, ipsum)	    /* IP checksums comp. */
 	WM_Q_EVCNT_DEFINE(txq, tusum)	    /* TCP/UDP cksums comp. */
 	WM_Q_EVCNT_DEFINE(txq, tusum6)	    /* TCP/UDP v6 cksums comp. */
 	WM_Q_EVCNT_DEFINE(txq, tso)	    /* TCP seg offload (IPv4) */
 	WM_Q_EVCNT_DEFINE(txq, tso6)	    /* TCP seg offload (IPv6) */
 	WM_Q_EVCNT_DEFINE(txq, tsopain)	    /* Painful header manip. for TSO */
 	WM_Q_EVCNT_DEFINE(txq, pcqdrop)	    /* Pkt dropped in pcq */
 	WM_Q_EVCNT_DEFINE(txq, descdrop)    /* Pkt dropped in MAC desc ring */
 					    /* other than toomanyseg */
 	WM_Q_EVCNT_DEFINE(txq, toomanyseg)  /* Pkt dropped(toomany DMA segs) */
 	WM_Q_EVCNT_DEFINE(txq, defrag)	    /* m_defrag() */
 	WM_Q_EVCNT_DEFINE(txq, underrun)    /* Tx underrun */
 	WM_Q_EVCNT_DEFINE(txq, skipcontext) /* Tx skip wring cksum context */
 	char txq_txseg_evcnt_names[WM_NTXSEGS][sizeof("txqXXtxsegXXX")];
 	struct evcnt txq_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
 #endif /* WM_EVENT_COUNTERS */
 };
 struct wm_rxqueue {
 	kmutex_t *rxq_lock;		/* lock for rx operations */
 	struct wm_softc *rxq_sc;	/* shortcut (skip struct wm_queue) */
 	/* Software state for the receive descriptors. */
 	struct wm_rxsoft rxq_soft[WM_NRXDESC];
 	/* RX control data structures. */
 	int rxq_ndesc;			/* must be a power of two */
 	size_t rxq_descsize;		/* a rx descriptor size */
 	rxdescs_t *rxq_descs_u;
 	bus_dmamap_t rxq_desc_dmamap;	/* control data DMA map */
 	bus_dma_segment_t rxq_desc_seg;	/* control data segment */
 	int rxq_desc_rseg;		/* real number of control segment */
 #define	rxq_desc_dma	rxq_desc_dmamap->dm_segs[0].ds_addr
 #define	rxq_descs	rxq_descs_u->sctxu_rxdescs
 #define	rxq_ext_descs	rxq_descs_u->sctxu_ext_rxdescs
 #define	rxq_nq_descs	rxq_descs_u->sctxu_nq_rxdescs
 	bus_addr_t rxq_rdt_reg;		/* offset of RDT register */
 	int rxq_ptr;			/* next ready Rx desc/queue ent */
 	int rxq_discard;
 	int rxq_len;
 	struct mbuf *rxq_head;
 	struct mbuf *rxq_tail;
 	struct mbuf **rxq_tailp;
 	bool rxq_stopping;
 	uint32_t rxq_packets;		/* for AIM */
 	uint32_t rxq_bytes;		/* for AIM */
 #ifdef WM_EVENT_COUNTERS
 	/* RX event counters */
 	WM_Q_EVCNT_DEFINE(rxq, intr);	/* Interrupts */
 	WM_Q_EVCNT_DEFINE(rxq, defer);	/* Rx deferred processing */
 	WM_Q_EVCNT_DEFINE(rxq, ipsum);	/* IP checksums checked */
 	WM_Q_EVCNT_DEFINE(rxq, tusum);	/* TCP/UDP cksums checked */
 #endif
 };
 struct wm_queue {
 	int wmq_id;			/* index of TX/RX queues */
 	int wmq_intr_idx;		/* index of MSI-X tables */
 	uint32_t wmq_itr;		/* interrupt interval per queue. */
 	bool wmq_set_itr;
 	struct wm_txqueue wmq_txq;
 	struct wm_rxqueue wmq_rxq;
 	bool wmq_txrx_use_workqueue;
 	struct work wmq_cookie;
 	void *wmq_si;
 };
 struct wm_phyop {
 	int (*acquire)(struct wm_softc *);
 	void (*release)(struct wm_softc *);
 	int (*readreg_locked)(device_t, int, int, uint16_t *);
 	int (*writereg_locked)(device_t, int, int, uint16_t);
 	int reset_delay_us;
 	bool no_errprint;
 };
 struct wm_nvmop {
 	int (*acquire)(struct wm_softc *);
 	void (*release)(struct wm_softc *);
 	int (*read)(struct wm_softc *, int, int, uint16_t *);
 };
 /*
  * Software state per device.
  */
 struct wm_softc {
 	device_t sc_dev;		/* generic device information */
 	bus_space_tag_t sc_st;		/* bus space tag */
 	bus_space_handle_t sc_sh;	/* bus space handle */
 	bus_size_t sc_ss;		/* bus space size */
 	bus_space_tag_t sc_iot;		/* I/O space tag */
 	bus_space_handle_t sc_ioh;	/* I/O space handle */
 	bus_size_t sc_ios;		/* I/O space size */
 	bus_space_tag_t sc_flasht;	/* flash registers space tag */
 	bus_space_handle_t sc_flashh;	/* flash registers space handle */
 	bus_size_t sc_flashs;		/* flash registers space size */
 	off_t sc_flashreg_offset;	/*
 					 * offset to flash registers from
 					 * start of BAR
 					 */
 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
 	struct ethercom sc_ethercom;	/* ethernet common data */
 	struct mii_data sc_mii;		/* MII/media information */
 	pci_chipset_tag_t sc_pc;
 	pcitag_t sc_pcitag;
 	int sc_bus_speed;		/* PCI/PCIX bus speed */
 	int sc_pcixe_capoff;		/* PCI[Xe] capability reg offset */
 	uint16_t sc_pcidevid;		/* PCI device ID */
 	wm_chip_type sc_type;		/* MAC type */
 	int sc_rev;			/* MAC revision */
 	wm_phy_type sc_phytype;		/* PHY type */
 	uint8_t sc_sfptype;		/* SFP type */
 	uint32_t sc_mediatype;		/* Media type (Copper, Fiber, SERDES)*/
 #define	WM_MEDIATYPE_UNKNOWN		0x00
 #define	WM_MEDIATYPE_FIBER		0x01
 #define	WM_MEDIATYPE_COPPER		0x02
 #define	WM_MEDIATYPE_SERDES		0x03 /* Internal SERDES */
 	int sc_funcid;			/* unit number of the chip (0 to 3) */
 	int sc_flags;			/* flags; see below */
 	u_short sc_if_flags;		/* last if_flags */
 	int sc_ec_capenable;		/* last ec_capenable */
 	int sc_flowflags;		/* 802.3x flow control flags */
 	uint16_t eee_lp_ability;	/* EEE link partner's ability */
 	int sc_align_tweak;
 	void *sc_ihs[WM_MAX_NINTR];	/*
 					 * interrupt cookie.
 					 * - legacy and msi use sc_ihs[0] only
 					 * - msix use sc_ihs[0] to sc_ihs[nintrs-1]
 					 */
 	pci_intr_handle_t *sc_intrs;	/*
 					 * legacy and msi use sc_intrs[0] only
 					 * msix use sc_intrs[0] to sc_ihs[nintrs-1]
 					 */
 	int sc_nintrs;			/* number of interrupts */
 	int sc_link_intr_idx;		/* index of MSI-X tables */
 	callout_t sc_tick_ch;		/* tick callout */
 	bool sc_core_stopping;
 	int sc_nvm_ver_major;
 	int sc_nvm_ver_minor;
 	int sc_nvm_ver_build;
 	int sc_nvm_addrbits;		/* NVM address bits */
 	unsigned int sc_nvm_wordsize;	/* NVM word size */
 	int sc_ich8_flash_base;
 	int sc_ich8_flash_bank_size;
 	int sc_nvm_k1_enabled;
 	int sc_nqueues;
 	struct wm_queue *sc_queue;
 	u_int sc_tx_process_limit;	/* Tx proc. repeat limit in softint */
 	u_int sc_tx_intr_process_limit;	/* Tx proc. repeat limit in H/W intr */
 	u_int sc_rx_process_limit;	/* Rx proc. repeat limit in softint */
 	u_int sc_rx_intr_process_limit;	/* Rx proc. repeat limit in H/W intr */
 	struct workqueue *sc_queue_wq;
 	bool sc_txrx_use_workqueue;
 	int sc_affinity_offset;
 #ifdef WM_EVENT_COUNTERS
 	/* Event counters. */
 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
 	/* WM_T_82542_2_1 only */
 	struct evcnt sc_ev_tx_xoff;	/* Tx PAUSE(!0) frames */
 	struct evcnt sc_ev_tx_xon;	/* Tx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_xoff;	/* Rx PAUSE(!0) frames */
 	struct evcnt sc_ev_rx_xon;	/* Rx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_macctl;	/* Rx Unsupported */
 #endif /* WM_EVENT_COUNTERS */
 	struct sysctllog *sc_sysctllog;
 	/* This variable are used only on the 82547. */
 	callout_t sc_txfifo_ch;		/* Tx FIFO stall work-around timer */
 	uint32_t sc_ctrl;		/* prototype CTRL register */
 #if 0
 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
 #endif
 	uint32_t sc_icr;		/* prototype interrupt bits */
 	uint32_t sc_itr_init;		/* prototype intr throttling reg */
 	uint32_t sc_tctl;		/* prototype TCTL register */
 	uint32_t sc_rctl;		/* prototype RCTL register */
 	uint32_t sc_txcw;		/* prototype TXCW register */
 	uint32_t sc_tipg;		/* prototype TIPG register */
 	uint32_t sc_fcrtl;		/* prototype FCRTL register */
 	uint32_t sc_pba;		/* prototype PBA register */
 	int sc_tbi_linkup;		/* TBI link status */
 	int sc_tbi_serdes_anegticks;	/* autonegotiation ticks */
 	int sc_tbi_serdes_ticks;	/* tbi ticks */
 	int sc_mchash_type;		/* multicast filter offset */
 	krndsource_t rnd_source;	/* random source */
 	struct if_percpuq *sc_ipq;	/* softint-based input queues */
 	kmutex_t *sc_core_lock;		/* lock for softc operations */
 	kmutex_t *sc_ich_phymtx;	/*
 					 * 82574/82583/ICH/PCH specific PHY
 					 * mutex. For 82574/82583, the mutex
 					 * is used for both PHY and NVM.
 					 */
 	kmutex_t *sc_ich_nvmmtx;	/* ICH/PCH specific NVM mutex */
 	struct wm_phyop phy;
 	struct wm_nvmop nvm;
 };
 #define WM_CORE_LOCK(_sc)						\
 	if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock)
 #define WM_CORE_UNLOCK(_sc)						\
 	if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock)
 #define WM_CORE_LOCKED(_sc)						\
 	(!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock))
 #define	WM_RXCHAIN_RESET(rxq)						\
 do {									\
 	(rxq)->rxq_tailp = &(rxq)->rxq_head;				\
 	*(rxq)->rxq_tailp = NULL;					\
 	(rxq)->rxq_len = 0;						\
 } while (/*CONSTCOND*/0)
 #define	WM_RXCHAIN_LINK(rxq, m)						\
 do {									\
 	*(rxq)->rxq_tailp = (rxq)->rxq_tail = (m);			\
 	(rxq)->rxq_tailp = &(m)->m_next;				\
 } while (/*CONSTCOND*/0)
 #ifdef WM_EVENT_COUNTERS
 #define	WM_EVCNT_INCR(ev)	(ev)->ev_count++
 #define	WM_EVCNT_ADD(ev, val)	(ev)->ev_count += (val)
 #define WM_Q_EVCNT_INCR(qname, evname)			\
 	WM_EVCNT_INCR(&(qname)->qname##_ev_##evname)
 #define WM_Q_EVCNT_ADD(qname, evname, val)		\
 	WM_EVCNT_ADD(&(qname)->qname##_ev_##evname, (val))
 #else /* !WM_EVENT_COUNTERS */
 #define	WM_EVCNT_INCR(ev)	/* nothing */
 #define	WM_EVCNT_ADD(ev, val)	/* nothing */
 #define WM_Q_EVCNT_INCR(qname, evname)		/* nothing */
 #define WM_Q_EVCNT_ADD(qname, evname, val)	/* nothing */
 #endif /* !WM_EVENT_COUNTERS */
 #define	CSR_READ(sc, reg)						\
 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
 #define	CSR_WRITE(sc, reg, val)						\
 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
 #define	CSR_WRITE_FLUSH(sc)						\
 	(void)CSR_READ((sc), WMREG_STATUS)
 #define ICH8_FLASH_READ32(sc, reg)					\
 	bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset)
 #define ICH8_FLASH_WRITE32(sc, reg, data)				\
 	bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset, (data))
 #define ICH8_FLASH_READ16(sc, reg)					\
 	bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset)
 #define ICH8_FLASH_WRITE16(sc, reg, data)				\
 	bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset, (data))
 #define	WM_CDTXADDR(txq, x)	((txq)->txq_desc_dma + WM_CDTXOFF((txq), (x)))
 #define	WM_CDRXADDR(rxq, x)	((rxq)->rxq_desc_dma + WM_CDRXOFF((rxq), (x)))
 #define	WM_CDTXADDR_LO(txq, x)	(WM_CDTXADDR((txq), (x)) & 0xffffffffU)
 #define	WM_CDTXADDR_HI(txq, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0)
 #define	WM_CDRXADDR_LO(rxq, x)	(WM_CDRXADDR((rxq), (x)) & 0xffffffffU)
 #define	WM_CDRXADDR_HI(rxq, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0)
 /*
  * Register read/write functions.
  * Other than CSR_{READ|WRITE}().
  */
 #if 0
 static inline uint32_t wm_io_read(struct wm_softc *, int);
 #endif
 static inline void wm_io_write(struct wm_softc *, int, uint32_t);
 static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t,
     uint32_t, uint32_t);
 static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t);
 /*
  * Descriptor sync/init functions.
  */
 static inline void wm_cdtxsync(struct wm_txqueue *, int, int, int);
 static inline void wm_cdrxsync(struct wm_rxqueue *, int, int);
 static inline void wm_init_rxdesc(struct wm_rxqueue *, int);
 /*
  * Device driver interface functions and commonly used functions.
  * match, attach, detach, init, start, stop, ioctl, watchdog and so on.
  */
 static const struct wm_product *wm_lookup(const struct pci_attach_args *);
 static int	wm_match(device_t, cfdata_t, void *);
 static void	wm_attach(device_t, device_t, void *);
 static int	wm_detach(device_t, int);
 static bool	wm_suspend(device_t, const pmf_qual_t *);
 static bool	wm_resume(device_t, const pmf_qual_t *);
 static void	wm_watchdog(struct ifnet *);
 static void	wm_watchdog_txq(struct ifnet *, struct wm_txqueue *,
     uint16_t *);
 static void	wm_watchdog_txq_locked(struct ifnet *, struct wm_txqueue *,
     uint16_t *);
 static void	wm_tick(void *);
 static int	wm_ifflags_cb(struct ethercom *);
 static int	wm_ioctl(struct ifnet *, u_long, void *);
 /* MAC address related */
 static uint16_t	wm_check_alt_mac_addr(struct wm_softc *);
 static int	wm_read_mac_addr(struct wm_softc *, uint8_t *);
 static void	wm_set_ral(struct wm_softc *, const uint8_t *, int);
 static uint32_t	wm_mchash(struct wm_softc *, const uint8_t *);
 static int	wm_rar_count(struct wm_softc *);
 static void	wm_set_filter(struct wm_softc *);
 /* Reset and init related */
 static void	wm_set_vlan(struct wm_softc *);
 static void	wm_set_pcie_completion_timeout(struct wm_softc *);
 static void	wm_get_auto_rd_done(struct wm_softc *);
 static void	wm_lan_init_done(struct wm_softc *);
 static void	wm_get_cfg_done(struct wm_softc *);
 static int	wm_phy_post_reset(struct wm_softc *);
 static int	wm_write_smbus_addr(struct wm_softc *);
 static int	wm_init_lcd_from_nvm(struct wm_softc *);
 static int	wm_oem_bits_config_ich8lan(struct wm_softc *, bool);
 static void	wm_initialize_hardware_bits(struct wm_softc *);
 static uint32_t	wm_rxpbs_adjust_82580(uint32_t);
 static int	wm_reset_phy(struct wm_softc *);
 static void	wm_flush_desc_rings(struct wm_softc *);
 static void	wm_reset(struct wm_softc *);
 static int	wm_add_rxbuf(struct wm_rxqueue *, int);
 static void	wm_rxdrain(struct wm_rxqueue *);
 static void	wm_init_rss(struct wm_softc *);
 static void	wm_adjust_qnum(struct wm_softc *, int);
 static inline bool	wm_is_using_msix(struct wm_softc *);
 static inline bool	wm_is_using_multiqueue(struct wm_softc *);
 static int	wm_softint_establish_queue(struct wm_softc *, int, int);
 static int	wm_setup_legacy(struct wm_softc *);
 static int	wm_setup_msix(struct wm_softc *);
 static int	wm_init(struct ifnet *);
 static int	wm_init_locked(struct ifnet *);
 static void	wm_init_sysctls(struct wm_softc *);
 static void	wm_unset_stopping_flags(struct wm_softc *);
 static void	wm_set_stopping_flags(struct wm_softc *);
 static void	wm_stop(struct ifnet *, int);
 static void	wm_stop_locked(struct ifnet *, bool, bool);
 static void	wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *);
 static void	wm_82547_txfifo_stall(void *);
 static int	wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *);
 static void	wm_itrs_writereg(struct wm_softc *, struct wm_queue *);
 /* DMA related */
 static int	wm_alloc_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_free_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_regs(struct wm_softc *, struct wm_queue *,
     struct wm_txqueue *);
 static int	wm_alloc_rx_descs(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_free_rx_descs(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_init_rx_regs(struct wm_softc *, struct wm_queue *,
     struct wm_rxqueue *);
 static int	wm_alloc_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static void	wm_free_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static int	wm_alloc_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_free_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static int	wm_init_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_init_tx_queue(struct wm_softc *, struct wm_queue *,
     struct wm_txqueue *);
 static int	wm_init_rx_queue(struct wm_softc *, struct wm_queue *,
     struct wm_rxqueue *);
 static int	wm_alloc_txrx_queues(struct wm_softc *);
 static void	wm_free_txrx_queues(struct wm_softc *);
 static int	wm_init_txrx_queues(struct wm_softc *);
 /* Start */
 static void	wm_tx_offload(struct wm_softc *, struct wm_txqueue *,
     struct wm_txsoft *, uint32_t *, uint8_t *);
 static inline int	wm_select_txqueue(struct ifnet *, struct mbuf *);
 static void	wm_start(struct ifnet *);
 static void	wm_start_locked(struct ifnet *);
 static int	wm_transmit(struct ifnet *, struct mbuf *);
 static void	wm_transmit_locked(struct ifnet *, struct wm_txqueue *);
 static void	wm_send_common_locked(struct ifnet *, struct wm_txqueue *,
 		    bool);
 static void	wm_nq_tx_offload(struct wm_softc *, struct wm_txqueue *,
     struct wm_txsoft *, uint32_t *, uint32_t *, bool *);
 static void	wm_nq_start(struct ifnet *);
 static void	wm_nq_start_locked(struct ifnet *);
 static int	wm_nq_transmit(struct ifnet *, struct mbuf *);
 static void	wm_nq_transmit_locked(struct ifnet *, struct wm_txqueue *);
 static void	wm_nq_send_common_locked(struct ifnet *, struct wm_txqueue *,
 		    bool);
 static void	wm_deferred_start_locked(struct wm_txqueue *);
 static void	wm_handle_queue(void *);
 static void	wm_handle_queue_work(struct work *, void *);
 /* Interrupt */
 static bool	wm_txeof(struct wm_txqueue *, u_int);
 static bool	wm_rxeof(struct wm_rxqueue *, u_int);
 static void	wm_linkintr_gmii(struct wm_softc *, uint32_t);
 static void	wm_linkintr_tbi(struct wm_softc *, uint32_t);
 static void	wm_linkintr_serdes(struct wm_softc *, uint32_t);
 static void	wm_linkintr(struct wm_softc *, uint32_t);
 static int	wm_intr_legacy(void *);
 static inline void	wm_txrxintr_disable(struct wm_queue *);
 static inline void	wm_txrxintr_enable(struct wm_queue *);
 static void	wm_itrs_calculate(struct wm_softc *, struct wm_queue *);
 static int	wm_txrxintr_msix(void *);
 static int	wm_linkintr_msix(void *);
 /*
  * Media related.
  * GMII, SGMII, TBI, SERDES and SFP.
  */
 /* Common */
 static void	wm_tbi_serdes_set_linkled(struct wm_softc *);
 /* GMII related */
 static void	wm_gmii_reset(struct wm_softc *);
 static void	wm_gmii_setup_phytype(struct wm_softc *, uint32_t, uint16_t);
 static int	wm_get_phy_id_82575(struct wm_softc *);
 static void	wm_gmii_mediainit(struct wm_softc *, pci_product_id_t);
 static int	wm_gmii_mediachange(struct ifnet *);
 static void	wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
 static void	wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int);
 static uint16_t	wm_i82543_mii_recvbits(struct wm_softc *);
 static int	wm_gmii_i82543_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_i82543_writereg(device_t, int, int, uint16_t);
 static int	wm_gmii_mdic_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_mdic_writereg(device_t, int, int, uint16_t);
 static int	wm_gmii_i82544_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_i82544_readreg_locked(device_t, int, int, uint16_t *);
 static int	wm_gmii_i82544_writereg(device_t, int, int, uint16_t);
 static int	wm_gmii_i82544_writereg_locked(device_t, int, int, uint16_t);
 static int	wm_gmii_i80003_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_i80003_writereg(device_t, int, int, uint16_t);
 static int	wm_gmii_bm_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_bm_writereg(device_t, int, int, uint16_t);
 static int	wm_enable_phy_wakeup_reg_access_bm(device_t, uint16_t *);
 static int	wm_disable_phy_wakeup_reg_access_bm(device_t, uint16_t *);
 static int	wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int,
 	bool);
 static int	wm_gmii_hv_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_hv_readreg_locked(device_t, int, int, uint16_t *);
 static int	wm_gmii_hv_writereg(device_t, int, int, uint16_t);
 static int	wm_gmii_hv_writereg_locked(device_t, int, int, uint16_t);
 static int	wm_gmii_82580_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_82580_writereg(device_t, int, int, uint16_t);
 static int	wm_gmii_gs40g_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_gs40g_writereg(device_t, int, int, uint16_t);
 static void	wm_gmii_statchg(struct ifnet *);
 /*
  * kumeran related (80003, ICH* and PCH*).
  * These functions are not for accessing MII registers but for accessing
  * kumeran specific registers.
  */
 static int	wm_kmrn_readreg(struct wm_softc *, int, uint16_t *);
 static int	wm_kmrn_readreg_locked(struct wm_softc *, int, uint16_t *);
 static int	wm_kmrn_writereg(struct wm_softc *, int, uint16_t);
 static int	wm_kmrn_writereg_locked(struct wm_softc *, int, uint16_t);
 /* EMI register related */
 static int	wm_access_emi_reg_locked(device_t, int, uint16_t *, bool);
 static int	wm_read_emi_reg_locked(device_t, int, uint16_t *);
 static int	wm_write_emi_reg_locked(device_t, int, uint16_t);
 /* SGMII */
 static bool	wm_sgmii_uses_mdio(struct wm_softc *);
 static void	wm_sgmii_sfp_preconfig(struct wm_softc *);
 static int	wm_sgmii_readreg(device_t, int, int, uint16_t *);
 static int	wm_sgmii_readreg_locked(device_t, int, int, uint16_t *);
 static int	wm_sgmii_writereg(device_t, int, int, uint16_t);
 static int	wm_sgmii_writereg_locked(device_t, int, int, uint16_t);
 /* TBI related */
 static bool	wm_tbi_havesignal(struct wm_softc *, uint32_t);
 static void	wm_tbi_mediainit(struct wm_softc *);
 static int	wm_tbi_mediachange(struct ifnet *);
 static void	wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
 static int	wm_check_for_link(struct wm_softc *);
 static void	wm_tbi_tick(struct wm_softc *);
 /* SERDES related */
 static void	wm_serdes_power_up_link_82575(struct wm_softc *);
 static int	wm_serdes_mediachange(struct ifnet *);
 static void	wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *);
 static void	wm_serdes_tick(struct wm_softc *);
 /* SFP related */
 static int	wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *);
 static uint32_t	wm_sfp_get_media_type(struct wm_softc *);
 /*
  * NVM related.
  * Microwire, SPI (w/wo EERD) and Flash.
  */
 /* Misc functions */
 static void	wm_eeprom_sendbits(struct wm_softc *, uint32_t, int);
 static void	wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int);
 static int	wm_nvm_set_addrbits_size_eecd(struct wm_softc *);
 /* Microwire */
 static int	wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *);
 /* SPI */
 static int	wm_nvm_ready_spi(struct wm_softc *);
 static int	wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *);
 /* Using with EERD */
 static int	wm_poll_eerd_eewr_done(struct wm_softc *, int);
 static int	wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *);
 /* Flash */
 static int	wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *,
     unsigned int *);
 static int32_t	wm_ich8_cycle_init(struct wm_softc *);
 static int32_t	wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
 static int32_t	wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t,
     uint32_t *);
 static int32_t	wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *);
 static int32_t	wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *);
 static int32_t	wm_read_ich8_dword(struct wm_softc *, uint32_t, uint32_t *);
 static int	wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *);
 static int	wm_nvm_read_spt(struct wm_softc *, int, int, uint16_t *);
 /* iNVM */
 static int	wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *);
 static int	wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *);
 /* Lock, detecting NVM type, validate checksum and read */
 static int	wm_nvm_is_onboard_eeprom(struct wm_softc *);
 static int	wm_nvm_flash_presence_i210(struct wm_softc *);
 static int	wm_nvm_validate_checksum(struct wm_softc *);
 static void	wm_nvm_version_invm(struct wm_softc *);
 static void	wm_nvm_version(struct wm_softc *);
 static int	wm_nvm_read(struct wm_softc *, int, int, uint16_t *);
 /*
  * Hardware semaphores.
  * Very complexed...
  */
 static int	wm_get_null(struct wm_softc *);
 static void	wm_put_null(struct wm_softc *);
 static int	wm_get_eecd(struct wm_softc *);
 static void	wm_put_eecd(struct wm_softc *);
 static int	wm_get_swsm_semaphore(struct wm_softc *); /* 8257[123] */
 static void	wm_put_swsm_semaphore(struct wm_softc *);
 static int	wm_get_swfw_semaphore(struct wm_softc *, uint16_t);
 static void	wm_put_swfw_semaphore(struct wm_softc *, uint16_t);
 static int	wm_get_nvm_80003(struct wm_softc *);
 static void	wm_put_nvm_80003(struct wm_softc *);
 static int	wm_get_nvm_82571(struct wm_softc *);
 static void	wm_put_nvm_82571(struct wm_softc *);
 static int	wm_get_phy_82575(struct wm_softc *);
 static void	wm_put_phy_82575(struct wm_softc *);
 static int	wm_get_swfwhw_semaphore(struct wm_softc *); /* For 574/583 */
 static void	wm_put_swfwhw_semaphore(struct wm_softc *);
 static int	wm_get_swflag_ich8lan(struct wm_softc *);	/* For PHY */
 static void	wm_put_swflag_ich8lan(struct wm_softc *);
 static int	wm_get_nvm_ich8lan(struct wm_softc *);
 static void	wm_put_nvm_ich8lan(struct wm_softc *);
 static int	wm_get_hw_semaphore_82573(struct wm_softc *);
 static void	wm_put_hw_semaphore_82573(struct wm_softc *);
 /*
  * Management mode and power management related subroutines.
  * BMC, AMT, suspend/resume and EEE.
  */
 #if 0
 static int	wm_check_mng_mode(struct wm_softc *);
 static int	wm_check_mng_mode_ich8lan(struct wm_softc *);
 static int	wm_check_mng_mode_82574(struct wm_softc *);
 static int	wm_check_mng_mode_generic(struct wm_softc *);
 #endif
 static int	wm_enable_mng_pass_thru(struct wm_softc *);
 static bool	wm_phy_resetisblocked(struct wm_softc *);
 static void	wm_get_hw_control(struct wm_softc *);
 static void	wm_release_hw_control(struct wm_softc *);
 static void	wm_gate_hw_phy_config_ich8lan(struct wm_softc *, bool);
 static int	wm_init_phy_workarounds_pchlan(struct wm_softc *);
 static void	wm_init_manageability(struct wm_softc *);
 static void	wm_release_manageability(struct wm_softc *);
 static void	wm_get_wakeup(struct wm_softc *);
 static int	wm_ulp_disable(struct wm_softc *);
 static int	wm_enable_phy_wakeup(struct wm_softc *);
 static void	wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *);
 static void	wm_suspend_workarounds_ich8lan(struct wm_softc *);
 static int	wm_resume_workarounds_pchlan(struct wm_softc *);
 static void	wm_enable_wakeup(struct wm_softc *);
 static void	wm_disable_aspm(struct wm_softc *);
 /* LPLU (Low Power Link Up) */
 static void	wm_lplu_d0_disable(struct wm_softc *);
 /* EEE */
 static int	wm_set_eee_i350(struct wm_softc *);
 static int	wm_set_eee_pchlan(struct wm_softc *);
 static int	wm_set_eee(struct wm_softc *);
 /*
  * Workarounds (mainly PHY related).
  * Basically, PHY's workarounds are in the PHY drivers.
  */
 static int	wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *);
 static void	wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
 static int	wm_hv_phy_workarounds_ich8lan(struct wm_softc *);
 static void	wm_copy_rx_addrs_to_phy_ich8lan(struct wm_softc *);
 static void	wm_copy_rx_addrs_to_phy_ich8lan_locked(struct wm_softc *);
 static int	wm_lv_jumbo_workaround_ich8lan(struct wm_softc *, bool);
 static int	wm_lv_phy_workarounds_ich8lan(struct wm_softc *);
 static int	wm_k1_workaround_lpt_lp(struct wm_softc *, bool);
 static int	wm_k1_gig_workaround_hv(struct wm_softc *, int);
 static int	wm_k1_workaround_lv(struct wm_softc *);
 static int	wm_link_stall_workaround_hv(struct wm_softc *);
 static int	wm_set_mdio_slow_mode_hv(struct wm_softc *);
 static void	wm_configure_k1_ich8lan(struct wm_softc *, int);
 static void	wm_reset_init_script_82575(struct wm_softc *);
 static void	wm_reset_mdicnfg_82580(struct wm_softc *);
 static bool	wm_phy_is_accessible_pchlan(struct wm_softc *);
 static void	wm_toggle_lanphypc_pch_lpt(struct wm_softc *);
 static int	wm_platform_pm_pch_lpt(struct wm_softc *, bool);
 static int	wm_pll_workaround_i210(struct wm_softc *);
 static void	wm_legacy_irq_quirk_spt(struct wm_softc *);
 CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc),
     wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
 /*
  * Devices supported by this driver.
  */
 static const struct wm_product {
 	pci_vendor_id_t		wmp_vendor;
 	pci_product_id_t	wmp_product;
 	const char		*wmp_name;
 	wm_chip_type		wmp_type;
 	uint32_t		wmp_flags;
 #define	WMP_F_UNKNOWN		WM_MEDIATYPE_UNKNOWN
 #define	WMP_F_FIBER		WM_MEDIATYPE_FIBER
 #define	WMP_F_COPPER		WM_MEDIATYPE_COPPER
 #define	WMP_F_SERDES		WM_MEDIATYPE_SERDES
 #define WMP_MEDIATYPE(x)	((x) & 0x03)
 } wm_products[] = {
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82542,
 	  "Intel i82542 1000BASE-X Ethernet",
 	  WM_T_82542_2_1,	WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_FIBER,
 	  "Intel i82543GC 1000BASE-X Ethernet",
 	  WM_T_82543,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_COPPER,
 	  "Intel i82543GC 1000BASE-T Ethernet",
 	  WM_T_82543,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_COPPER,
 	  "Intel i82544EI 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_FIBER,
 	  "Intel i82544EI 1000BASE-X Ethernet",
 	  WM_T_82544,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_COPPER,
 	  "Intel i82544GC 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_LOM,
 	  "Intel i82544GC (LOM) 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM,
 	  "Intel i82540EM 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 @@ -5527,2008 +5527,2013 @@ wm_setup_legacy(struct wm_softc *sc)
 	sc->sc_nintrs = 1;
 	return wm_softint_establish_queue(sc, 0, 0);
+}
 static int
 wm_setup_msix(struct wm_softc *sc)
+{
 	void *vih;
 	kcpuset_t *affinity;
 	int qidx, error, intr_idx, txrx_established;
 	pci_chipset_tag_t pc = sc->sc_pc;
 	const char *intrstr = NULL;
 	char intrbuf[PCI_INTRSTR_LEN];
 	char intr_xname[INTRDEVNAMEBUF];
 	if (sc->sc_nqueues < ncpu) {
 		/*
 		 * To avoid other devices' interrupts, the affinity of Tx/Rx
 		 * interrupts start from CPU#1.
 		 */
 		sc->sc_affinity_offset = 1;
 	} else {
 		/*
 		 * In this case, this device use all CPUs. So, we unify
 		 * affinitied cpu_index to msix vector number for readability.
 		 */
 		sc->sc_affinity_offset = 0;
+	}
 	error = wm_alloc_txrx_queues(sc);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "cannot allocate queues %d\n",
 		    error);
 		return ENOMEM;
+	}
 	kcpuset_create(&affinity, false);
 	intr_idx = 0;
 	/*
 	 * TX and RX
 	 */
 	txrx_established = 0;
 	for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
 		struct wm_queue *wmq = &sc->sc_queue[qidx];
 		int affinity_to = (sc->sc_affinity_offset + intr_idx) % ncpu;
 		intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
 		    sizeof(intrbuf));
 #ifdef WM_MPSAFE
 		pci_intr_setattr(pc, &sc->sc_intrs[intr_idx],
 		    PCI_INTR_MPSAFE, true);
 #endif
 		memset(intr_xname, 0, sizeof(intr_xname));
 		snprintf(intr_xname, sizeof(intr_xname), "%sTXRX%d",
 		    device_xname(sc->sc_dev), qidx);
 		vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx],
 		    IPL_NET, wm_txrxintr_msix, wmq, intr_xname);
 		if (vih == NULL) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to establish MSI-X(for TX and RX)%s%s\n",
 			    intrstr ? " at " : "",
 			    intrstr ? intrstr : "");
 			goto fail;
+		}
 		kcpuset_zero(affinity);
 		/* Round-robin affinity */
 		kcpuset_set(affinity, affinity_to);
 		error = interrupt_distribute(vih, affinity, NULL);
 		if (error == 0) {
 			aprint_normal_dev(sc->sc_dev,
 			    "for TX and RX interrupting at %s affinity to %u\n",
 			    intrstr, affinity_to);
 		} else {
 			aprint_normal_dev(sc->sc_dev,
 			    "for TX and RX interrupting at %s\n", intrstr);
+		}
 		sc->sc_ihs[intr_idx] = vih;
 		if (wm_softint_establish_queue(sc, qidx, intr_idx) != 0)
 			goto fail;
 		txrx_established++;
 		intr_idx++;
+	}
 	/* LINK */
 	intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
 	    sizeof(intrbuf));
 #ifdef WM_MPSAFE
 	pci_intr_setattr(pc, &sc->sc_intrs[intr_idx], PCI_INTR_MPSAFE, true);
 #endif
 	memset(intr_xname, 0, sizeof(intr_xname));
 	snprintf(intr_xname, sizeof(intr_xname), "%sLINK",
 	    device_xname(sc->sc_dev));
 	vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx],
 	    IPL_NET, wm_linkintr_msix, sc, intr_xname);
 	if (vih == NULL) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to establish MSI-X(for LINK)%s%s\n",
 		    intrstr ? " at " : "",
 		    intrstr ? intrstr : "");
 		goto fail;
+	}
 	/* Keep default affinity to LINK interrupt */
 	aprint_normal_dev(sc->sc_dev,
 	    "for LINK interrupting at %s\n", intrstr);
 	sc->sc_ihs[intr_idx] = vih;
 	sc->sc_link_intr_idx = intr_idx;
 	sc->sc_nintrs = sc->sc_nqueues + 1;
 	kcpuset_destroy(affinity);
 	return 0;
  fail:
 	for (qidx = 0; qidx < txrx_established; qidx++) {
 		struct wm_queue *wmq = &sc->sc_queue[qidx];
 		pci_intr_disestablish(sc->sc_pc,sc->sc_ihs[wmq->wmq_intr_idx]);
 		sc->sc_ihs[wmq->wmq_intr_idx] = NULL;
+	}
 	kcpuset_destroy(affinity);
 	return ENOMEM;
+}
 static void
 wm_unset_stopping_flags(struct wm_softc *sc)
+{
 	int i;
 	KASSERT(WM_CORE_LOCKED(sc));
 	/* Must unset stopping flags in ascending order. */
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 		mutex_enter(txq->txq_lock);
 		txq->txq_stopping = false;
 		mutex_exit(txq->txq_lock);
 		mutex_enter(rxq->rxq_lock);
 		rxq->rxq_stopping = false;
 		mutex_exit(rxq->rxq_lock);
+	}
 	sc->sc_core_stopping = false;
+}
 static void
 wm_set_stopping_flags(struct wm_softc *sc)
+{
 	int i;
 	KASSERT(WM_CORE_LOCKED(sc));
 	sc->sc_core_stopping = true;
 	/* Must set stopping flags in ascending order. */
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
 		mutex_enter(rxq->rxq_lock);
 		rxq->rxq_stopping = true;
 		mutex_exit(rxq->rxq_lock);
 		mutex_enter(txq->txq_lock);
 		txq->txq_stopping = true;
 		mutex_exit(txq->txq_lock);
+	}
+}
 /*
  * Write interrupt interval value to ITR or EITR
  */
 static void
 wm_itrs_writereg(struct wm_softc *sc, struct wm_queue *wmq)
+{
 	if (!wmq->wmq_set_itr)
 		return;
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		uint32_t eitr = __SHIFTIN(wmq->wmq_itr, EITR_ITR_INT_MASK);
 		/*
 		 * 82575 doesn't have CNT_INGR field.
 		 * So, overwrite counter field by software.
 		 */
 		if (sc->sc_type == WM_T_82575)
 			eitr |= __SHIFTIN(wmq->wmq_itr, EITR_COUNTER_MASK_82575);
 		else
 			eitr |= EITR_CNT_INGR;
 		CSR_WRITE(sc, WMREG_EITR(wmq->wmq_intr_idx), eitr);
 	} else if (sc->sc_type == WM_T_82574 && wm_is_using_msix(sc)) {
 		/*
 		 * 82574 has both ITR and EITR. SET EITR when we use
 		 * the multi queue function with MSI-X.
 		 */
 		CSR_WRITE(sc, WMREG_EITR_82574(wmq->wmq_intr_idx),
 		    wmq->wmq_itr & EITR_ITR_INT_MASK_82574);
 	} else {
 		KASSERT(wmq->wmq_id == 0);
 		CSR_WRITE(sc, WMREG_ITR, wmq->wmq_itr);
+	}
 	wmq->wmq_set_itr = false;
+}
 /*
  * TODO
  * Below dynamic calculation of itr is almost the same as linux igb,
  * however it does not fit to wm(4). So, we will have been disable AIM
  * until we will find appropriate calculation of itr.
  */
 /*
  * calculate interrupt interval value to be going to write register in
  * wm_itrs_writereg(). This function does not write ITR/EITR register.
  */
 static void
 wm_itrs_calculate(struct wm_softc *sc, struct wm_queue *wmq)
+{
 #ifdef NOTYET
 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
 	struct wm_txqueue *txq = &wmq->wmq_txq;
 	uint32_t avg_size = 0;
 	uint32_t new_itr;
 	if (rxq->rxq_packets)
 		avg_size =  rxq->rxq_bytes / rxq->rxq_packets;
 	if (txq->txq_packets)
 		avg_size = uimax(avg_size, txq->txq_bytes / txq->txq_packets);
 	if (avg_size == 0) {
 		new_itr = 450; /* restore default value */
 		goto out;
+	}
 	/* Add 24 bytes to size to account for CRC, preamble, and gap */
 	avg_size += 24;
 	/* Don't starve jumbo frames */
 	avg_size = uimin(avg_size, 3000);
 	/* Give a little boost to mid-size frames */
 	if ((avg_size > 300) && (avg_size < 1200))
 		new_itr = avg_size / 3;
 	else
 		new_itr = avg_size / 2;
 out:
 	/*
 	 * The usage of 82574 and 82575 EITR is different from otther NEWQUEUE
 	 * controllers. See sc->sc_itr_init setting in wm_init_locked().
 	 */
 	if ((sc->sc_flags & WM_F_NEWQUEUE) == 0 || sc->sc_type != WM_T_82575)
 		new_itr *= 4;
 	if (new_itr != wmq->wmq_itr) {
 		wmq->wmq_itr = new_itr;
 		wmq->wmq_set_itr = true;
 	} else
 		wmq->wmq_set_itr = false;
 	rxq->rxq_packets = 0;
 	rxq->rxq_bytes = 0;
 	txq->txq_packets = 0;
 	txq->txq_bytes = 0;
 #endif
+}
 static void
 wm_init_sysctls(struct wm_softc *sc)
+{
 	struct sysctllog **log;
 	const struct sysctlnode *rnode, *cnode;
 	int rv;
 	const char *dvname;
 	log = &sc->sc_sysctllog;
 	dvname = device_xname(sc->sc_dev);
 	rv = sysctl_createv(log, 0, NULL, &rnode,
 , CTLTYPE_NODE, dvname,
 	    SYSCTL_DESCR("wm information and settings"),
 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
 	if (rv != 0)
 		goto err;
 	rv = sysctl_createv(log, 0, &rnode, &cnode, CTLFLAG_READWRITE,
 	    CTLTYPE_BOOL, "txrx_workqueue", SYSCTL_DESCR("Use workqueue for packet processing"),
 	    NULL, 0, &sc->sc_txrx_use_workqueue, 0, CTL_CREATE, CTL_EOL);
 	if (rv != 0)
 		goto teardown;
 	return;
 teardown:
 	sysctl_teardown(log);
 err:
 	sc->sc_sysctllog = NULL;
 	device_printf(sc->sc_dev, "%s: sysctl_createv failed, rv = %d\n",
 	    __func__, rv);
+}
 /*
  * wm_init:		[ifnet interface function]
+ *
  *	Initialize the interface.
  */
 static int
 wm_init(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	int ret;
 	WM_CORE_LOCK(sc);
 	ret = wm_init_locked(ifp);
 	WM_CORE_UNLOCK(sc);
 	return ret;
+}
 static int
 wm_init_locked(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct ethercom *ec = &sc->sc_ethercom;
 	int i, j, trynum, error = 0;
 	uint32_t reg, sfp_mask = 0;
 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	KASSERT(WM_CORE_LOCKED(sc));
 	/*
 	 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
 	 * There is a small but measurable benefit to avoiding the adjusment
 	 * of the descriptor so that the headers are aligned, for normal mtu,
 	 * on such platforms.  One possibility is that the DMA itself is
 	 * slightly more efficient if the front of the entire packet (instead
 	 * of the front of the headers) is aligned.
+	 *
 	 * Note we must always set align_tweak to 0 if we are using
 	 * jumbo frames.
 	 */
 #ifdef __NO_STRICT_ALIGNMENT
 	sc->sc_align_tweak = 0;
 #else
 	if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
 		sc->sc_align_tweak = 0;
 	else
 		sc->sc_align_tweak = 2;
 #endif /* __NO_STRICT_ALIGNMENT */
 	/* Cancel any pending I/O. */
 	wm_stop_locked(ifp, false, false);
 	/* Update statistics before reset */
 	if_statadd2(ifp, if_collisions, CSR_READ(sc, WMREG_COLC),
 	    if_ierrors, CSR_READ(sc, WMREG_RXERRC));
 	/* PCH_SPT hardware workaround */
 	if (sc->sc_type == WM_T_PCH_SPT)
 		wm_flush_desc_rings(sc);
 	/* Reset the chip to a known state. */
 	wm_reset(sc);
 	/*
 	 * AMT based hardware can now take control from firmware
 	 * Do this after reset.
 	 */
 	if ((sc->sc_flags & WM_F_HAS_AMT) != 0)
 		wm_get_hw_control(sc);
 	if ((sc->sc_type >= WM_T_PCH_SPT) &&
 	    pci_intr_type(sc->sc_pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_INTX)
 		wm_legacy_irq_quirk_spt(sc);
 	/* Init hardware bits */
 	wm_initialize_hardware_bits(sc);
 	/* Reset the PHY. */
 	if (sc->sc_flags & WM_F_HAS_MII)
 		wm_gmii_reset(sc);
 	if (sc->sc_type >= WM_T_ICH8) {
 		reg = CSR_READ(sc, WMREG_GCR);
 		/*
 		 * ICH8 No-snoop bits are opposite polarity. Set to snoop by
 		 * default after reset.
 		 */
 		if (sc->sc_type == WM_T_ICH8)
 			reg |= GCR_NO_SNOOP_ALL;
 		else
 			reg &= ~GCR_NO_SNOOP_ALL;
 		CSR_WRITE(sc, WMREG_GCR, reg);
+	}
 	if ((sc->sc_type >= WM_T_ICH8)
 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER)
 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3)) {
 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
 		reg |= CTRL_EXT_RO_DIS;
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
+	}
 	/* Calculate (E)ITR value */
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0 && sc->sc_type != WM_T_82575) {
 		/*
 		 * For NEWQUEUE's EITR (except for 82575).
 		 * 82575's EITR should be set same throttling value as other
 		 * old controllers' ITR because the interrupt/sec calculation
 		 * is the same, that is, 1,000,000,000 / (N * 256).
+		 *
 		 * 82574's EITR should be set same throttling value as ITR.
+		 *
 		 * For N interrupts/sec, set this value to:
 		 * 1,000,000 / N in contrast to ITR throttoling value.
 		 */
 		sc->sc_itr_init = 450;
 	} else if (sc->sc_type >= WM_T_82543) {
 		/*
 		 * Set up the interrupt throttling register (units of 256ns)
 		 * Note that a footnote in Intel's documentation says this
 		 * ticker runs at 1/4 the rate when the chip is in 100Mbit
 		 * or 10Mbit mode.  Empirically, it appears to be the case
 		 * that that is also true for the 1024ns units of the other
 		 * interrupt-related timer registers -- so, really, we ought
 		 * to divide this value by 4 when the link speed is low.
+		 *
 		 * XXX implement this division at link speed change!
 		 */
 		/*
 		 * For N interrupts/sec, set this value to:
 		 * 1,000,000,000 / (N * 256).  Note that we set the
 		 * absolute and packet timer values to this value
 		 * divided by 4 to get "simple timer" behavior.
 		 */
 		sc->sc_itr_init = 1500;		/* 2604 ints/sec */
+	}
 	error = wm_init_txrx_queues(sc);
 	if (error)
 		goto out;
 	if (((sc->sc_flags & WM_F_SGMII) == 0) &&
 	    (sc->sc_mediatype == WM_MEDIATYPE_SERDES) &&
 	    (sc->sc_type >= WM_T_82575))
 		wm_serdes_power_up_link_82575(sc);
 	/* Clear out the VLAN table -- we don't use it (yet). */
 	CSR_WRITE(sc, WMREG_VET, 0);
 	if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
 		trynum = 10; /* Due to hw errata */
 	else
 		trynum = 1;
 	for (i = 0; i < WM_VLAN_TABSIZE; i++)
 		for (j = 0; j < trynum; j++)
 			CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0);
 	/*
 	 * Set up flow-control parameters.
+	 *
 	 * XXX Values could probably stand some tuning.
 	 */
 	if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
 	    && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH)
 	    && (sc->sc_type != WM_T_PCH2) && (sc->sc_type != WM_T_PCH_LPT)
 	    && (sc->sc_type != WM_T_PCH_SPT) && (sc->sc_type != WM_T_PCH_CNP)){
 		CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
 		CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
 		CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
+	}
 	sc->sc_fcrtl = FCRTL_DFLT;
 	if (sc->sc_type < WM_T_82543) {
 		CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT);
 		CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl);
 	} else {
 		CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT);
 		CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl);
+	}
 	if (sc->sc_type == WM_T_80003)
 		CSR_WRITE(sc, WMREG_FCTTV, 0xffff);
 	else
 		CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT);
 	/* Writes the control register. */
 	wm_set_vlan(sc);
 	if (sc->sc_flags & WM_F_HAS_MII) {
 		uint16_t kmreg;
 		switch (sc->sc_type) {
 		case WM_T_80003:
 		case WM_T_ICH8:
 		case WM_T_ICH9:
 		case WM_T_ICH10:
 		case WM_T_PCH:
 		case WM_T_PCH2:
 		case WM_T_PCH_LPT:
 		case WM_T_PCH_SPT:
 		case WM_T_PCH_CNP:
 			/*
 			 * Set the mac to wait the maximum time between each
 			 * iteration and increase the max iterations when
 			 * polling the phy; this fixes erroneous timeouts at
 			 * 10Mbps.
 			 */
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS,
 xFFFF);
 			wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_INB_PARAM,
 			    &kmreg);
 			kmreg |= 0x3F;
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_PARAM,
 			    kmreg);
 			break;
 		default:
 			break;
+		}
 		if (sc->sc_type == WM_T_80003) {
 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
 			reg &= ~CTRL_EXT_LINK_MODE_MASK;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			/* Bypass RX and TX FIFO's */
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL,
 			    KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
 			    | KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL,
 			    KUMCTRLSTA_INB_CTRL_DIS_PADDING |
 			    KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT);
+		}
+	}
 #if 0
 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
 #endif
 	/* Set up checksum offload parameters. */
 	reg = CSR_READ(sc, WMREG_RXCSUM);
 	reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);
 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
 		reg |= RXCSUM_IPOFL;
 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
 		reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx))
 		reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;
 	CSR_WRITE(sc, WMREG_RXCSUM, reg);
 	/* Set registers about MSI-X */
 	if (wm_is_using_msix(sc)) {
 		uint32_t ivar, qintr_idx;
 		struct wm_queue *wmq;
 		unsigned int qid;
 		if (sc->sc_type == WM_T_82575) {
 			/* Interrupt control */
 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
 			reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME | CTRL_EXT_NSICR;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			/* TX and RX */
 			for (i = 0; i < sc->sc_nqueues; i++) {
 				wmq = &sc->sc_queue[i];
 				CSR_WRITE(sc, WMREG_MSIXBM(wmq->wmq_intr_idx),
 				    EITR_TX_QUEUE(wmq->wmq_id)
 				    | EITR_RX_QUEUE(wmq->wmq_id));
+			}
 			/* Link status */
 			CSR_WRITE(sc, WMREG_MSIXBM(sc->sc_link_intr_idx),
 			    EITR_OTHER);
 		} else if (sc->sc_type == WM_T_82574) {
 			/* Interrupt control */
 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
 			reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			/*
 			 * Workaround issue with spurious interrupts
 			 * in MSI-X mode.
 			 * At wm_initialize_hardware_bits(), sc_nintrs has not
 			 * initialized yet. So re-initialize WMREG_RFCTL here.
 			 */
 			reg = CSR_READ(sc, WMREG_RFCTL);
 			reg |= WMREG_RFCTL_ACKDIS;
 			CSR_WRITE(sc, WMREG_RFCTL, reg);
 			ivar = 0;
 			/* TX and RX */
 			for (i = 0; i < sc->sc_nqueues; i++) {
 				wmq = &sc->sc_queue[i];
 				qid = wmq->wmq_id;
 				qintr_idx = wmq->wmq_intr_idx;
 				ivar |= __SHIFTIN((IVAR_VALID_82574|qintr_idx),
 				    IVAR_TX_MASK_Q_82574(qid));
 				ivar |= __SHIFTIN((IVAR_VALID_82574|qintr_idx),
 				    IVAR_RX_MASK_Q_82574(qid));
+			}
 			/* Link status */
 			ivar |= __SHIFTIN((IVAR_VALID_82574
 				| sc->sc_link_intr_idx), IVAR_OTHER_MASK);
 			CSR_WRITE(sc, WMREG_IVAR, ivar | IVAR_INT_ON_ALL_WB);
 		} else {
 			/* Interrupt control */
 			CSR_WRITE(sc, WMREG_GPIE, GPIE_NSICR | GPIE_MULTI_MSIX
 			    | GPIE_EIAME | GPIE_PBA);
 			switch (sc->sc_type) {
 			case WM_T_82580:
 			case WM_T_I350:
 			case WM_T_I354:
 			case WM_T_I210:
 			case WM_T_I211:
 				/* TX and RX */
 				for (i = 0; i < sc->sc_nqueues; i++) {
 					wmq = &sc->sc_queue[i];
 					qid = wmq->wmq_id;
 					qintr_idx = wmq->wmq_intr_idx;
 					ivar = CSR_READ(sc, WMREG_IVAR_Q(qid));
 					ivar &= ~IVAR_TX_MASK_Q(qid);
 					ivar |= __SHIFTIN((qintr_idx
 						| IVAR_VALID),
 					    IVAR_TX_MASK_Q(qid));
 					ivar &= ~IVAR_RX_MASK_Q(qid);
 					ivar |= __SHIFTIN((qintr_idx
 						| IVAR_VALID),
 					    IVAR_RX_MASK_Q(qid));
 					CSR_WRITE(sc, WMREG_IVAR_Q(qid), ivar);
+				}
 				break;
 			case WM_T_82576:
 				/* TX and RX */
 				for (i = 0; i < sc->sc_nqueues; i++) {
 					wmq = &sc->sc_queue[i];
 					qid = wmq->wmq_id;
 					qintr_idx = wmq->wmq_intr_idx;
 					ivar = CSR_READ(sc,
 					    WMREG_IVAR_Q_82576(qid));
 					ivar &= ~IVAR_TX_MASK_Q_82576(qid);
 					ivar |= __SHIFTIN((qintr_idx
 						| IVAR_VALID),
 					    IVAR_TX_MASK_Q_82576(qid));
 					ivar &= ~IVAR_RX_MASK_Q_82576(qid);
 					ivar |= __SHIFTIN((qintr_idx
 						| IVAR_VALID),
 					    IVAR_RX_MASK_Q_82576(qid));
 					CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid),
 					    ivar);
+				}
 				break;
 			default:
 				break;
+			}
 			/* Link status */
 			ivar = __SHIFTIN((sc->sc_link_intr_idx | IVAR_VALID),
 			    IVAR_MISC_OTHER);
 			CSR_WRITE(sc, WMREG_IVAR_MISC, ivar);
+		}
 		if (wm_is_using_multiqueue(sc)) {
 			wm_init_rss(sc);
 			/*
 			** NOTE: Receive Full-Packet Checksum Offload
 			** is mutually exclusive with Multiqueue. However
 			** this is not the same as TCP/IP checksums which
 			** still work.
 			*/
 			reg = CSR_READ(sc, WMREG_RXCSUM);
 			reg |= RXCSUM_PCSD;
 			CSR_WRITE(sc, WMREG_RXCSUM, reg);
+		}
+	}
 	/* Set up the interrupt registers. */
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
 	/* Enable SFP module insertion interrupt if it's required */
 	if ((sc->sc_flags & WM_F_SFP) != 0) {
 		sc->sc_ctrl |= CTRL_EXTLINK_EN;
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		sfp_mask = ICR_GPI(0);
+	}
 	if (wm_is_using_msix(sc)) {
 		uint32_t mask;
 		struct wm_queue *wmq;
 		switch (sc->sc_type) {
 		case WM_T_82574:
 			mask = 0;
 			for (i = 0; i < sc->sc_nqueues; i++) {
 				wmq = &sc->sc_queue[i];
 				mask |= ICR_TXQ(wmq->wmq_id);
 				mask |= ICR_RXQ(wmq->wmq_id);
+			}
 			mask |= ICR_OTHER;
 			CSR_WRITE(sc, WMREG_EIAC_82574, mask);
 			CSR_WRITE(sc, WMREG_IMS, mask | ICR_LSC);
 			break;
 		default:
 			if (sc->sc_type == WM_T_82575) {
 				mask = 0;
 				for (i = 0; i < sc->sc_nqueues; i++) {
 					wmq = &sc->sc_queue[i];
 					mask |= EITR_TX_QUEUE(wmq->wmq_id);
 					mask |= EITR_RX_QUEUE(wmq->wmq_id);
+				}
 				mask |= EITR_OTHER;
 			} else {
 				mask = 0;
 				for (i = 0; i < sc->sc_nqueues; i++) {
 					wmq = &sc->sc_queue[i];
 					mask |= 1 << wmq->wmq_intr_idx;
+				}
 				mask |= 1 << sc->sc_link_intr_idx;
+			}
 			CSR_WRITE(sc, WMREG_EIAC, mask);
 			CSR_WRITE(sc, WMREG_EIAM, mask);
 			CSR_WRITE(sc, WMREG_EIMS, mask);
 			/* For other interrupts */
 			CSR_WRITE(sc, WMREG_IMS, ICR_LSC | sfp_mask);
 			break;
+		}
 	} else {
 		sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
 		    ICR_RXO | ICR_RXT0 | sfp_mask;
 		CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
+	}
 	/* Set up the inter-packet gap. */
 	CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
 	if (sc->sc_type >= WM_T_82543) {
 		for (int qidx = 0; qidx < sc->sc_nqueues; qidx++) {
 			struct wm_queue *wmq = &sc->sc_queue[qidx];
 			wm_itrs_writereg(sc, wmq);
+		}
 		/*
 		 * Link interrupts occur much less than TX
 		 * interrupts and RX interrupts. So, we don't
 		 * tune EINTR(WM_MSIX_LINKINTR_IDX) value like
 		 * FreeBSD's if_igb.
 		 */
+	}
 	/* Set the VLAN ethernetype. */
 	CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN);
 	/*
 	 * Set up the transmit control register; we start out with
 	 * a collision distance suitable for FDX, but update it whe
 	 * we resolve the media type.
 	 */
 	sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_RTLC
 	    | TCTL_CT(TX_COLLISION_THRESHOLD)
 	    | TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
 	if (sc->sc_type >= WM_T_82571)
 		sc->sc_tctl |= TCTL_MULR;
 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		/* Write TDT after TCTL.EN is set. See the document. */
 		CSR_WRITE(sc, WMREG_TDT(0), 0);
+	}
 	if (sc->sc_type == WM_T_80003) {
 		reg = CSR_READ(sc, WMREG_TCTL_EXT);
 		reg &= ~TCTL_EXT_GCEX_MASK;
 		reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
 		CSR_WRITE(sc, WMREG_TCTL_EXT, reg);
+	}
 	/* Set the media. */
 	if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0)
 		goto out;
 	/* Configure for OS presence */
 	wm_init_manageability(sc);
 	/*
 	 * Set up the receive control register; we actually program the
 	 * register when we set the receive filter. Use multicast address
 	 * offset type 0.
+	 *
 	 * Only the i82544 has the ability to strip the incoming CRC, so we
 	 * don't enable that feature.
 	 */
 	sc->sc_mchash_type = 0;
 	sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF
 	    | __SHIFTIN(sc->sc_mchash_type, RCTL_MO);
 	/* 82574 use one buffer extended Rx descriptor. */
 	if (sc->sc_type == WM_T_82574)
 		sc->sc_rctl |= RCTL_DTYP_ONEBUF;
 	if ((sc->sc_flags & WM_F_CRC_STRIP) != 0)
 		sc->sc_rctl |= RCTL_SECRC;
 	if (((ec->ec_capabilities & ETHERCAP_JUMBO_MTU) != 0)
 	    && (ifp->if_mtu > ETHERMTU)) {
 		sc->sc_rctl |= RCTL_LPE;
 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 			CSR_WRITE(sc, WMREG_RLPML, ETHER_MAX_LEN_JUMBO);
+	}
 	if (MCLBYTES == 2048)
 		sc->sc_rctl |= RCTL_2k;
 	else {
 		if (sc->sc_type >= WM_T_82543) {
 			switch (MCLBYTES) {
 			case 4096:
 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
 				break;
 			case 8192:
 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
 				break;
 			case 16384:
 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
 				break;
 			default:
 				panic("wm_init: MCLBYTES %d unsupported",
 				    MCLBYTES);
 				break;
+			}
 		} else
 			panic("wm_init: i82542 requires MCLBYTES = 2048");
+	}
 	/* Enable ECC */
 	switch (sc->sc_type) {
 	case WM_T_82571:
 		reg = CSR_READ(sc, WMREG_PBA_ECC);
 		reg |= PBA_ECC_CORR_EN;
 		CSR_WRITE(sc, WMREG_PBA_ECC, reg);
 		break;
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 		reg = CSR_READ(sc, WMREG_PBECCSTS);
 		reg |= PBECCSTS_UNCORR_ECC_ENABLE;
 		CSR_WRITE(sc, WMREG_PBECCSTS, reg);
 		sc->sc_ctrl |= CTRL_MEHE;
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		break;
 	default:
 		break;
+	}
 	/*
 	 * Set the receive filter.
+	 *
 	 * For 82575 and 82576, the RX descriptors must be initialized after
 	 * the setting of RCTL.EN in wm_set_filter()
 	 */
 	wm_set_filter(sc);
 	/* On 575 and later set RDT only if RX enabled */
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		int qidx;
 		for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
 			struct wm_rxqueue *rxq = &sc->sc_queue[qidx].wmq_rxq;
 			for (i = 0; i < WM_NRXDESC; i++) {
 				mutex_enter(rxq->rxq_lock);
 				wm_init_rxdesc(rxq, i);
 				mutex_exit(rxq->rxq_lock);
+			}
+		}
+	}
 	wm_unset_stopping_flags(sc);
 	/* Start the one second link check clock. */
 	callout_schedule(&sc->sc_tick_ch, hz);
 	/* ...all done! */
 	ifp->if_flags |= IFF_RUNNING;
  out:
 	/* Save last flags for the callback */
 	sc->sc_if_flags = ifp->if_flags;
 	sc->sc_ec_capenable = ec->ec_capenable;
 	if (error)
 		log(LOG_ERR, "%s: interface not running\n",
 		    device_xname(sc->sc_dev));
 	return error;
+}
 /*
  * wm_stop:		[ifnet interface function]
+ *
  *	Stop transmission on the interface.
  */
 static void
 wm_stop(struct ifnet *ifp, int disable)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	ASSERT_SLEEPABLE();
 	WM_CORE_LOCK(sc);
 	wm_stop_locked(ifp, disable ? true : false, true);
 	WM_CORE_UNLOCK(sc);
 	/*
 	 * After wm_set_stopping_flags(), it is guaranteed
 	 * wm_handle_queue_work() does not call workqueue_enqueue().
 	 * However, workqueue_wait() cannot call in wm_stop_locked()
 	 * because it can sleep...
 	 * so, call workqueue_wait() here.
 	 */
 	for (int i = 0; i < sc->sc_nqueues; i++)
 		workqueue_wait(sc->sc_queue_wq, &sc->sc_queue[i].wmq_cookie);
+}
 static void
 wm_stop_locked(struct ifnet *ifp, bool disable, bool wait)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct wm_txsoft *txs;
 	int i, qidx;
 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	KASSERT(WM_CORE_LOCKED(sc));
 	wm_set_stopping_flags(sc);
 	if (sc->sc_flags & WM_F_HAS_MII) {
 		/* Down the MII. */
 		mii_down(&sc->sc_mii);
 	} else {
 #if 0
 		/* Should we clear PHY's status properly? */
 		wm_reset(sc);
 #endif
+	}
 	/* Stop the transmit and receive processes. */
 	CSR_WRITE(sc, WMREG_TCTL, 0);
 	CSR_WRITE(sc, WMREG_RCTL, 0);
 	sc->sc_rctl &= ~RCTL_EN;
 	/*
 	 * Clear the interrupt mask to ensure the device cannot assert its
 	 * interrupt line.
 	 * Clear sc->sc_icr to ensure wm_intr_legacy() makes no attempt to
 	 * service any currently pending or shared interrupt.
 	 */
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
 	sc->sc_icr = 0;
 	if (wm_is_using_msix(sc)) {
 		if (sc->sc_type != WM_T_82574) {
 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
 			CSR_WRITE(sc, WMREG_EIAC, 0);
 		} else
 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
+	}
 	/*
 	 * Stop callouts after interrupts are disabled; if we have
 	 * to wait for them, we will be releasing the CORE_LOCK
 	 * briefly, which will unblock interrupts on the current CPU.
 	 */
 	/* Stop the one second clock. */
 	if (wait)
 		callout_halt(&sc->sc_tick_ch, sc->sc_core_lock);
 	else
 		callout_stop(&sc->sc_tick_ch);
 	/* Stop the 82547 Tx FIFO stall check timer. */
 	if (sc->sc_type == WM_T_82547) {
 		if (wait)
 			callout_halt(&sc->sc_txfifo_ch, sc->sc_core_lock);
 		else
 			callout_stop(&sc->sc_txfifo_ch);
+	}
 	/* Release any queued transmit buffers. */
 	for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
 		struct wm_queue *wmq = &sc->sc_queue[qidx];
 		struct wm_txqueue *txq = &wmq->wmq_txq;
 		struct mbuf *m;
 		mutex_enter(txq->txq_lock);
 		txq->txq_sending = false; /* Ensure watchdog disabled */
 		for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
 			txs = &txq->txq_soft[i];
 			if (txs->txs_mbuf != NULL) {
 				bus_dmamap_unload(sc->sc_dmat,txs->txs_dmamap);
 				m_freem(txs->txs_mbuf);
 				txs->txs_mbuf = NULL;
+			}
+		}
 		/* Drain txq_interq */
 		while ((m = pcq_get(txq->txq_interq)) != NULL)
 			m_freem(m);
 		mutex_exit(txq->txq_lock);
+	}
 	/* Mark the interface as down and cancel the watchdog timer. */
 	ifp->if_flags &= ~IFF_RUNNING;
 	if (disable) {
 		for (i = 0; i < sc->sc_nqueues; i++) {
 			struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 			mutex_enter(rxq->rxq_lock);
 			wm_rxdrain(rxq);
 			mutex_exit(rxq->rxq_lock);
+		}
+	}
 #if 0 /* notyet */
 	if (sc->sc_type >= WM_T_82544)
 		CSR_WRITE(sc, WMREG_WUC, 0);
 #endif
+}
 static void
 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0)
+{
 	struct mbuf *m;
 	int i;
 	log(LOG_DEBUG, "%s: mbuf chain:\n", device_xname(sc->sc_dev));
 	for (m = m0, i = 0; m != NULL; m = m->m_next, i++)
 		log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, "
 		    "m_flags = 0x%08x\n", device_xname(sc->sc_dev),
 		    m->m_data, m->m_len, m->m_flags);
 	log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", device_xname(sc->sc_dev),
 	    i, i == 1 ? "" : "s");
+}
 /*
  * wm_82547_txfifo_stall:
+ *
  *	Callout used to wait for the 82547 Tx FIFO to drain,
  *	reset the FIFO pointers, and restart packet transmission.
  */
 static void
 wm_82547_txfifo_stall(void *arg)
+{
 	struct wm_softc *sc = arg;
 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
 	mutex_enter(txq->txq_lock);
 	if (txq->txq_stopping)
 		goto out;
 	if (txq->txq_fifo_stall) {
 		if (CSR_READ(sc, WMREG_TDT(0)) == CSR_READ(sc, WMREG_TDH(0)) &&
 		    CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) &&
 		    CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) {
 			/*
 			 * Packets have drained.  Stop transmitter, reset
 			 * FIFO pointers, restart transmitter, and kick
 			 * the packet queue.
 			 */
 			uint32_t tctl = CSR_READ(sc, WMREG_TCTL);
 			CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN);
 			CSR_WRITE(sc, WMREG_TDFT, txq->txq_fifo_addr);
 			CSR_WRITE(sc, WMREG_TDFH, txq->txq_fifo_addr);
 			CSR_WRITE(sc, WMREG_TDFTS, txq->txq_fifo_addr);
 			CSR_WRITE(sc, WMREG_TDFHS, txq->txq_fifo_addr);
 			CSR_WRITE(sc, WMREG_TCTL, tctl);
 			CSR_WRITE_FLUSH(sc);
 			txq->txq_fifo_head = 0;
 			txq->txq_fifo_stall = 0;
 			wm_start_locked(&sc->sc_ethercom.ec_if);
 		} else {
 			/*
 			 * Still waiting for packets to drain; try again in
 			 * another tick.
 			 */
 			callout_schedule(&sc->sc_txfifo_ch, 1);
+		}
+	}
 out:
 	mutex_exit(txq->txq_lock);
+}
 /*
  * wm_82547_txfifo_bugchk:
+ *
  *	Check for bug condition in the 82547 Tx FIFO.  We need to
  *	prevent enqueueing a packet that would wrap around the end
  *	if the Tx FIFO ring buffer, otherwise the chip will croak.
+ *
  *	We do this by checking the amount of space before the end
  *	of the Tx FIFO buffer. If the packet will not fit, we "stall"
  *	the Tx FIFO, wait for all remaining packets to drain, reset
  *	the internal FIFO pointers to the beginning, and restart
  *	transmission on the interface.
  */
 #define	WM_FIFO_HDR		0x10
 #define	WM_82547_PAD_LEN	0x3e0
 static int
 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0)
+{
 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
 	int space = txq->txq_fifo_size - txq->txq_fifo_head;
 	int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR);
 	/* Just return if already stalled. */
 	if (txq->txq_fifo_stall)
 		return 1;
 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
 		/* Stall only occurs in half-duplex mode. */
 		goto send_packet;
+	}
 	if (len >= WM_82547_PAD_LEN + space) {
 		txq->txq_fifo_stall = 1;
 		callout_schedule(&sc->sc_txfifo_ch, 1);
 		return 1;
+	}
  send_packet:
 	txq->txq_fifo_head += len;
 	if (txq->txq_fifo_head >= txq->txq_fifo_size)
 		txq->txq_fifo_head -= txq->txq_fifo_size;
 	return 0;
+}
 static int
 wm_alloc_tx_descs(struct wm_softc *sc, struct wm_txqueue *txq)
+{
 	int error;
 	/*
 	 * Allocate the control data structures, and create and load the
 	 * DMA map for it.
+	 *
 	 * NOTE: All Tx descriptors must be in the same 4G segment of
 	 * memory.  So must Rx descriptors.  We simplify by allocating
 	 * both sets within the same 4G segment.
 	 */
 	if (sc->sc_type < WM_T_82544)
 		WM_NTXDESC(txq) = WM_NTXDESC_82542;
 	else
 		WM_NTXDESC(txq) = WM_NTXDESC_82544;
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 		txq->txq_descsize = sizeof(nq_txdesc_t);
 	else
 		txq->txq_descsize = sizeof(wiseman_txdesc_t);
 	if ((error = bus_dmamem_alloc(sc->sc_dmat, WM_TXDESCS_SIZE(txq),
 		    PAGE_SIZE, (bus_size_t) 0x100000000ULL, &txq->txq_desc_seg,
 , &txq->txq_desc_rseg, 0)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to allocate TX control data, error = %d\n",
 		    error);
 		goto fail_0;
+	}
 	if ((error = bus_dmamem_map(sc->sc_dmat, &txq->txq_desc_seg,
 		    txq->txq_desc_rseg, WM_TXDESCS_SIZE(txq),
 		    (void **)&txq->txq_descs_u, BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to map TX control data, error = %d\n", error);
 		goto fail_1;
+	}
 	if ((error = bus_dmamap_create(sc->sc_dmat, WM_TXDESCS_SIZE(txq), 1,
 		    WM_TXDESCS_SIZE(txq), 0, 0, &txq->txq_desc_dmamap)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to create TX control data DMA map, error = %d\n",
 		    error);
 		goto fail_2;
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmat, txq->txq_desc_dmamap,
 		    txq->txq_descs_u, WM_TXDESCS_SIZE(txq), NULL, 0)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to load TX control data DMA map, error = %d\n",
 		    error);
 		goto fail_3;
+	}
 	return 0;
  fail_3:
 	bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap);
  fail_2:
 	bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u,
 	    WM_TXDESCS_SIZE(txq));
  fail_1:
 	bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg);
  fail_0:
 	return error;
+}
 static void
 wm_free_tx_descs(struct wm_softc *sc, struct wm_txqueue *txq)
+{
 	bus_dmamap_unload(sc->sc_dmat, txq->txq_desc_dmamap);
 	bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap);
 	bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u,
 	    WM_TXDESCS_SIZE(txq));
 	bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg);
+}
 static int
 wm_alloc_rx_descs(struct wm_softc *sc, struct wm_rxqueue *rxq)
+{
 	int error;
 	size_t rxq_descs_size;
 	/*
 	 * Allocate the control data structures, and create and load the
 	 * DMA map for it.
+	 *
 	 * NOTE: All Tx descriptors must be in the same 4G segment of
 	 * memory.  So must Rx descriptors.  We simplify by allocating
 	 * both sets within the same 4G segment.
 	 */
 	rxq->rxq_ndesc = WM_NRXDESC;
 	if (sc->sc_type == WM_T_82574)
 		rxq->rxq_descsize = sizeof(ext_rxdesc_t);
 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 		rxq->rxq_descsize = sizeof(nq_rxdesc_t);
 	else
 		rxq->rxq_descsize = sizeof(wiseman_rxdesc_t);
 	rxq_descs_size = rxq->rxq_descsize * rxq->rxq_ndesc;
 	if ((error = bus_dmamem_alloc(sc->sc_dmat, rxq_descs_size,
 		    PAGE_SIZE, (bus_size_t) 0x100000000ULL, &rxq->rxq_desc_seg,
 , &rxq->rxq_desc_rseg, 0)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to allocate RX control data, error = %d\n",
 		    error);
 		goto fail_0;
+	}
 	if ((error = bus_dmamem_map(sc->sc_dmat, &rxq->rxq_desc_seg,
 		    rxq->rxq_desc_rseg, rxq_descs_size,
 		    (void **)&rxq->rxq_descs_u, BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to map RX control data, error = %d\n", error);
 		goto fail_1;
+	}
 	if ((error = bus_dmamap_create(sc->sc_dmat, rxq_descs_size, 1,
 		    rxq_descs_size, 0, 0, &rxq->rxq_desc_dmamap)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to create RX control data DMA map, error = %d\n",
 		    error);
 		goto fail_2;
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmat, rxq->rxq_desc_dmamap,
 		    rxq->rxq_descs_u, rxq_descs_size, NULL, 0)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to load RX control data DMA map, error = %d\n",
 		    error);
 		goto fail_3;
+	}
 	return 0;
  fail_3:
 	bus_dmamap_destroy(sc->sc_dmat, rxq->rxq_desc_dmamap);
  fail_2:
 	bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->rxq_descs_u,
 	    rxq_descs_size);
  fail_1:
 	bus_dmamem_free(sc->sc_dmat, &rxq->rxq_desc_seg, rxq->rxq_desc_rseg);
  fail_0:
 	return error;
+}
 static void
 wm_free_rx_descs(struct wm_softc *sc, struct wm_rxqueue *rxq)
+{
 	bus_dmamap_unload(sc->sc_dmat, rxq->rxq_desc_dmamap);
 	bus_dmamap_destroy(sc->sc_dmat, rxq->rxq_desc_dmamap);
 	bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->rxq_descs_u,
 	    rxq->rxq_descsize * rxq->rxq_ndesc);
 	bus_dmamem_free(sc->sc_dmat, &rxq->rxq_desc_seg, rxq->rxq_desc_rseg);
+}
 static int
 wm_alloc_tx_buffer(struct wm_softc *sc, struct wm_txqueue *txq)
+{
 	int i, error;
 	/* Create the transmit buffer DMA maps. */
 	WM_TXQUEUELEN(txq) =
 	    (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ?
 	    WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX;
 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
 		if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA,
 			    WM_NTXSEGS, WTX_MAX_LEN, 0, 0,
 			    &txq->txq_soft[i].txs_dmamap)) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to create Tx DMA map %d, error = %d\n",
 			    i, error);
 			goto fail;
+		}
+	}
 	return 0;
  fail:
 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
 		if (txq->txq_soft[i].txs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    txq->txq_soft[i].txs_dmamap);
+	}
 	return error;
+}
 static void
 wm_free_tx_buffer(struct wm_softc *sc, struct wm_txqueue *txq)
+{
 	int i;
 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
 		if (txq->txq_soft[i].txs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    txq->txq_soft[i].txs_dmamap);
+	}
+}
 static int
 wm_alloc_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
+{
 	int i, error;
 	/* Create the receive buffer DMA maps. */
 	for (i = 0; i < rxq->rxq_ndesc; i++) {
 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
 			    MCLBYTES, 0, 0,
 			    &rxq->rxq_soft[i].rxs_dmamap)) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to create Rx DMA map %d error = %d\n",
 			    i, error);
 			goto fail;
+		}
 		rxq->rxq_soft[i].rxs_mbuf = NULL;
+	}
 	return 0;
  fail:
 	for (i = 0; i < rxq->rxq_ndesc; i++) {
 		if (rxq->rxq_soft[i].rxs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    rxq->rxq_soft[i].rxs_dmamap);
+	}
 	return error;
+}
 static void
 wm_free_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
+{
 	int i;
 	for (i = 0; i < rxq->rxq_ndesc; i++) {
 		if (rxq->rxq_soft[i].rxs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    rxq->rxq_soft[i].rxs_dmamap);
+	}
+}
 /*
  * wm_alloc_quques:
  *	Allocate {tx,rx}descs and {tx,rx} buffers
  */
 static int
 wm_alloc_txrx_queues(struct wm_softc *sc)
+{
 	int i, error, tx_done, rx_done;
 	sc->sc_queue = kmem_zalloc(sizeof(struct wm_queue) * sc->sc_nqueues,
 	    KM_SLEEP);
 	if (sc->sc_queue == NULL) {
 		aprint_error_dev(sc->sc_dev,"unable to allocate wm_queue\n");
 		error = ENOMEM;
 		goto fail_0;
+	}
 	/* For transmission */
 	error = 0;
 	tx_done = 0;
 	for (i = 0; i < sc->sc_nqueues; i++) {
 #ifdef WM_EVENT_COUNTERS
 		int j;
 		const char *xname;
 #endif
 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
 		txq->txq_sc = sc;
 		txq->txq_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
 		error = wm_alloc_tx_descs(sc, txq);
 		if (error)
 			break;
 		error = wm_alloc_tx_buffer(sc, txq);
 		if (error) {
 			wm_free_tx_descs(sc, txq);
 			break;
+		}
 		txq->txq_interq = pcq_create(WM_TXINTERQSIZE, KM_SLEEP);
 		if (txq->txq_interq == NULL) {
 			wm_free_tx_descs(sc, txq);
 			wm_free_tx_buffer(sc, txq);
 			error = ENOMEM;
 			break;
+		}
 #ifdef WM_EVENT_COUNTERS
 		xname = device_xname(sc->sc_dev);
 		WM_Q_MISC_EVCNT_ATTACH(txq, txsstall, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, txdstall, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, fifo_stall, txq, i, xname);
 		WM_Q_INTR_EVCNT_ATTACH(txq, txdw, txq, i, xname);
 		WM_Q_INTR_EVCNT_ATTACH(txq, txqe, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, ipsum, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, tusum, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, tusum6, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, tso, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, tso6, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, tsopain, txq, i, xname);
 		for (j = 0; j < WM_NTXSEGS; j++) {
 			snprintf(txq->txq_txseg_evcnt_names[j],
 			    sizeof(txq->txq_txseg_evcnt_names[j]), "txq%02dtxseg%d", i, j);
 			evcnt_attach_dynamic(&txq->txq_ev_txseg[j], EVCNT_TYPE_MISC,
 			    NULL, xname, txq->txq_txseg_evcnt_names[j]);
+		}
 		WM_Q_MISC_EVCNT_ATTACH(txq, pcqdrop, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, descdrop, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, toomanyseg, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, defrag, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, underrun, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, skipcontext, txq, i, xname);
 #endif /* WM_EVENT_COUNTERS */
 		tx_done++;
+	}
 	if (error)
 		goto fail_1;
 	/* For receive */
 	error = 0;
 	rx_done = 0;
 	for (i = 0; i < sc->sc_nqueues; i++) {
 #ifdef WM_EVENT_COUNTERS
 		const char *xname;
 #endif
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 		rxq->rxq_sc = sc;
 		rxq->rxq_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
 		error = wm_alloc_rx_descs(sc, rxq);
 		if (error)
 			break;
 		error = wm_alloc_rx_buffer(sc, rxq);
 		if (error) {
 			wm_free_rx_descs(sc, rxq);
 			break;
+		}
 #ifdef WM_EVENT_COUNTERS
 		xname = device_xname(sc->sc_dev);
 		WM_Q_INTR_EVCNT_ATTACH(rxq, intr, rxq, i, xname);
 		WM_Q_INTR_EVCNT_ATTACH(rxq, defer, rxq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(rxq, ipsum, rxq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(rxq, tusum, rxq, i, xname);
 #endif /* WM_EVENT_COUNTERS */
 		rx_done++;
+	}
 	if (error)
 		goto fail_2;
 	return 0;
  fail_2:
 	for (i = 0; i < rx_done; i++) {
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 		wm_free_rx_buffer(sc, rxq);
 		wm_free_rx_descs(sc, rxq);
 		if (rxq->rxq_lock)
 			mutex_obj_free(rxq->rxq_lock);
+	}
  fail_1:
 	for (i = 0; i < tx_done; i++) {
 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
 		pcq_destroy(txq->txq_interq);
 		wm_free_tx_buffer(sc, txq);
 		wm_free_tx_descs(sc, txq);
 		if (txq->txq_lock)
 			mutex_obj_free(txq->txq_lock);
+	}
 	kmem_free(sc->sc_queue,
 	    sizeof(struct wm_queue) * sc->sc_nqueues);
  fail_0:
 	return error;
+}
 /*
  * wm_free_quques:
  *	Free {tx,rx}descs and {tx,rx} buffers
  */
 static void
 wm_free_txrx_queues(struct wm_softc *sc)
+{
 	int i;
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 #ifdef WM_EVENT_COUNTERS
 		WM_Q_EVCNT_DETACH(rxq, intr, rxq, i);
 		WM_Q_EVCNT_DETACH(rxq, defer, rxq, i);
 		WM_Q_EVCNT_DETACH(rxq, ipsum, rxq, i);
 		WM_Q_EVCNT_DETACH(rxq, tusum, rxq, i);
 #endif /* WM_EVENT_COUNTERS */
 		wm_free_rx_buffer(sc, rxq);
 		wm_free_rx_descs(sc, rxq);
 		if (rxq->rxq_lock)
 			mutex_obj_free(rxq->rxq_lock);
+	}
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
 		struct mbuf *m;
 #ifdef WM_EVENT_COUNTERS
 		int j;
 		WM_Q_EVCNT_DETACH(txq, txsstall, txq, i);
 		WM_Q_EVCNT_DETACH(txq, txdstall, txq, i);
 		WM_Q_EVCNT_DETACH(txq, fifo_stall, txq, i);
 		WM_Q_EVCNT_DETACH(txq, txdw, txq, i);
 		WM_Q_EVCNT_DETACH(txq, txqe, txq, i);
 		WM_Q_EVCNT_DETACH(txq, ipsum, txq, i);
 		WM_Q_EVCNT_DETACH(txq, tusum, txq, i);
 		WM_Q_EVCNT_DETACH(txq, tusum6, txq, i);
 		WM_Q_EVCNT_DETACH(txq, tso, txq, i);
 		WM_Q_EVCNT_DETACH(txq, tso6, txq, i);
 		WM_Q_EVCNT_DETACH(txq, tsopain, txq, i);
 		for (j = 0; j < WM_NTXSEGS; j++)
 			evcnt_detach(&txq->txq_ev_txseg[j]);
 		WM_Q_EVCNT_DETACH(txq, pcqdrop, txq, i);
 		WM_Q_EVCNT_DETACH(txq, descdrop, txq, i);
 		WM_Q_EVCNT_DETACH(txq, toomanyseg, txq, i);
 		WM_Q_EVCNT_DETACH(txq, defrag, txq, i);
 		WM_Q_EVCNT_DETACH(txq, underrun, txq, i);
 		WM_Q_EVCNT_DETACH(txq, skipcontext, txq, i);
 #endif /* WM_EVENT_COUNTERS */
 		/* Drain txq_interq */
 		while ((m = pcq_get(txq->txq_interq)) != NULL)
 			m_freem(m);
 		pcq_destroy(txq->txq_interq);
 		wm_free_tx_buffer(sc, txq);
 		wm_free_tx_descs(sc, txq);
 		if (txq->txq_lock)
 			mutex_obj_free(txq->txq_lock);
+	}
 	kmem_free(sc->sc_queue, sizeof(struct wm_queue) * sc->sc_nqueues);
+}
 static void
 wm_init_tx_descs(struct wm_softc *sc __unused, struct wm_txqueue *txq)
+{
 	KASSERT(mutex_owned(txq->txq_lock));
 	/* Initialize the transmit descriptor ring. */
 	memset(txq->txq_descs, 0, WM_TXDESCS_SIZE(txq));
 	wm_cdtxsync(txq, 0, WM_NTXDESC(txq),
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	txq->txq_free = WM_NTXDESC(txq);
 	txq->txq_next = 0;
+}
 static void
 wm_init_tx_regs(struct wm_softc *sc, struct wm_queue *wmq,
     struct wm_txqueue *txq)
+{
 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	KASSERT(mutex_owned(txq->txq_lock));
 	if (sc->sc_type < WM_T_82543) {
 		CSR_WRITE(sc, WMREG_OLD_TDBAH, WM_CDTXADDR_HI(txq, 0));
 		CSR_WRITE(sc, WMREG_OLD_TDBAL, WM_CDTXADDR_LO(txq, 0));
 		CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCS_SIZE(txq));
 		CSR_WRITE(sc, WMREG_OLD_TDH, 0);
 		CSR_WRITE(sc, WMREG_OLD_TDT, 0);
 		CSR_WRITE(sc, WMREG_OLD_TIDV, 128);
 	} else {
 		int qid = wmq->wmq_id;
 		CSR_WRITE(sc, WMREG_TDBAH(qid), WM_CDTXADDR_HI(txq, 0));
 		CSR_WRITE(sc, WMREG_TDBAL(qid), WM_CDTXADDR_LO(txq, 0));
 		CSR_WRITE(sc, WMREG_TDLEN(qid), WM_TXDESCS_SIZE(txq));
 		CSR_WRITE(sc, WMREG_TDH(qid), 0);
 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 			/*
 			 * Don't write TDT before TCTL.EN is set.
 			 * See the document.
 			 */
 			CSR_WRITE(sc, WMREG_TXDCTL(qid), TXDCTL_QUEUE_ENABLE
 			    | TXDCTL_PTHRESH(0) | TXDCTL_HTHRESH(0)
 			    | TXDCTL_WTHRESH(0));
 		else {
 			/* XXX should update with AIM? */
 			CSR_WRITE(sc, WMREG_TIDV, wmq->wmq_itr / 4);
 			if (sc->sc_type >= WM_T_82540) {
 				/* Should be the same */
 				CSR_WRITE(sc, WMREG_TADV, wmq->wmq_itr / 4);
+			}
 			CSR_WRITE(sc, WMREG_TDT(qid), 0);
 			CSR_WRITE(sc, WMREG_TXDCTL(qid), TXDCTL_PTHRESH(0) |
 			    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
+		}
+	}
+}
 static void
 wm_init_tx_buffer(struct wm_softc *sc __unused, struct wm_txqueue *txq)
+{
 	int i;
 	KASSERT(mutex_owned(txq->txq_lock));
 	/* Initialize the transmit job descriptors. */
 	for (i = 0; i < WM_TXQUEUELEN(txq); i++)
 		txq->txq_soft[i].txs_mbuf = NULL;
 	txq->txq_sfree = WM_TXQUEUELEN(txq);
 	txq->txq_snext = 0;
 	txq->txq_sdirty = 0;
+}
 static void
 wm_init_tx_queue(struct wm_softc *sc, struct wm_queue *wmq,
     struct wm_txqueue *txq)
+{
 	KASSERT(mutex_owned(txq->txq_lock));
 	/*
 	 * Set up some register offsets that are different between
 	 * the i82542 and the i82543 and later chips.
 	 */
 	if (sc->sc_type < WM_T_82543)
 		txq->txq_tdt_reg = WMREG_OLD_TDT;
 	else
 		txq->txq_tdt_reg = WMREG_TDT(wmq->wmq_id);
 	wm_init_tx_descs(sc, txq);
 	wm_init_tx_regs(sc, wmq, txq);
 	wm_init_tx_buffer(sc, txq);
 	txq->txq_flags = 0; /* Clear WM_TXQ_NO_SPACE */
 	txq->txq_sending = false;
+}
 static void
 wm_init_rx_regs(struct wm_softc *sc, struct wm_queue *wmq,
     struct wm_rxqueue *rxq)
+{
 	KASSERT(mutex_owned(rxq->rxq_lock));
 	/*
 	 * Initialize the receive descriptor and receive job
 	 * descriptor rings.
 	 */
 	if (sc->sc_type < WM_T_82543) {
 		CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(rxq, 0));
 		CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(rxq, 0));
 		CSR_WRITE(sc, WMREG_OLD_RDLEN0,
 		    rxq->rxq_descsize * rxq->rxq_ndesc);
 		CSR_WRITE(sc, WMREG_OLD_RDH0, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDT0, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD);
 		CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDH1, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDT1, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDTR1, 0);
 	} else {
 		int qid = wmq->wmq_id;
 		CSR_WRITE(sc, WMREG_RDBAH(qid), WM_CDRXADDR_HI(rxq, 0));
 		CSR_WRITE(sc, WMREG_RDBAL(qid), WM_CDRXADDR_LO(rxq, 0));
 		CSR_WRITE(sc, WMREG_RDLEN(qid),
 		    rxq->rxq_descsize * rxq->rxq_ndesc);
 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 			if (MCLBYTES & ((1 << SRRCTL_BSIZEPKT_SHIFT) - 1))
 				panic("%s: MCLBYTES %d unsupported for 82575 or higher\n", __func__, MCLBYTES);
 			/* Currently, support SRRCTL_DESCTYPE_ADV_ONEBUF only. */
 			CSR_WRITE(sc, WMREG_SRRCTL(qid), SRRCTL_DESCTYPE_ADV_ONEBUF
 			    | (MCLBYTES >> SRRCTL_BSIZEPKT_SHIFT));
 			CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_QUEUE_ENABLE
 			    | RXDCTL_PTHRESH(16) | RXDCTL_HTHRESH(8)
 			    | RXDCTL_WTHRESH(1));
 			CSR_WRITE(sc, WMREG_RDH(qid), 0);
 			CSR_WRITE(sc, WMREG_RDT(qid), 0);
 		} else {
 			CSR_WRITE(sc, WMREG_RDH(qid), 0);
 			CSR_WRITE(sc, WMREG_RDT(qid), 0);
 			/* XXX should update with AIM? */
 			CSR_WRITE(sc, WMREG_RDTR,
 			    (wmq->wmq_itr / 4) | RDTR_FPD);
 			/* MUST be same */
 			CSR_WRITE(sc, WMREG_RADV, wmq->wmq_itr / 4);
 			CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_PTHRESH(0) |
 			    RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1));
+		}
+	}
+}
 static int
 wm_init_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
+{
 	struct wm_rxsoft *rxs;
 	int error, i;
 	KASSERT(mutex_owned(rxq->rxq_lock));
 	for (i = 0; i < rxq->rxq_ndesc; i++) {
 		rxs = &rxq->rxq_soft[i];
 		if (rxs->rxs_mbuf == NULL) {
 			if ((error = wm_add_rxbuf(rxq, i)) != 0) {
 				log(LOG_ERR, "%s: unable to allocate or map "
 				    "rx buffer %d, error = %d\n",
 				    device_xname(sc->sc_dev), i, error);
 				/*
 				 * XXX Should attempt to run with fewer receive
 				 * XXX buffers instead of just failing.
 				 */
 				wm_rxdrain(rxq);
 				return ENOMEM;
+			}
 		} else {
 			/*
 			 * For 82575 and 82576, the RX descriptors must be
 			 * initialized after the setting of RCTL.EN in
 			 * wm_set_filter()
 			 */
 			if ((sc->sc_flags & WM_F_NEWQUEUE) == 0)
 				wm_init_rxdesc(rxq, i);
+		}
+	}
 	rxq->rxq_ptr = 0;
 	rxq->rxq_discard = 0;
 	WM_RXCHAIN_RESET(rxq);
 	return 0;
+}
 static int
 wm_init_rx_queue(struct wm_softc *sc, struct wm_queue *wmq,
     struct wm_rxqueue *rxq)
+{
 	KASSERT(mutex_owned(rxq->rxq_lock));
 	/*
 	 * Set up some register offsets that are different between
 	 * the i82542 and the i82543 and later chips.
 	 */
 	if (sc->sc_type < WM_T_82543)
 		rxq->rxq_rdt_reg = WMREG_OLD_RDT0;
 	else
 		rxq->rxq_rdt_reg = WMREG_RDT(wmq->wmq_id);
 	wm_init_rx_regs(sc, wmq, rxq);
 	return wm_init_rx_buffer(sc, rxq);
+}
 /*
  * wm_init_quques:
  *	Initialize {tx,rx}descs and {tx,rx} buffers
  */
 static int
 wm_init_txrx_queues(struct wm_softc *sc)
+{
 	int i, error = 0;
 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_queue *wmq = &sc->sc_queue[i];
 		struct wm_txqueue *txq = &wmq->wmq_txq;
 		struct wm_rxqueue *rxq = &wmq->wmq_rxq;
 		/*
 		 * TODO
 		 * Currently, use constant variable instead of AIM.
 		 * Furthermore, the interrupt interval of multiqueue which use
 		 * polling mode is less than default value.
 		 * More tuning and AIM are required.
 		 */
 		if (wm_is_using_multiqueue(sc))
 			wmq->wmq_itr = 50;
 		else
 			wmq->wmq_itr = sc->sc_itr_init;
 		wmq->wmq_set_itr = true;
 		mutex_enter(txq->txq_lock);
 		wm_init_tx_queue(sc, wmq, txq);
 		mutex_exit(txq->txq_lock);
 		mutex_enter(rxq->rxq_lock);
 		error = wm_init_rx_queue(sc, wmq, rxq);
 		mutex_exit(rxq->rxq_lock);
 		if (error)
 			break;
+	}
 	return error;
+}
 /*
  * wm_tx_offload:
+ *
  *	Set up TCP/IP checksumming parameters for the
  *	specified packet.
  */
 static void
 wm_tx_offload(struct wm_softc *sc, struct wm_txqueue *txq,
     struct wm_txsoft *txs, uint32_t *cmdp, uint8_t *fieldsp)
+{
 	struct mbuf *m0 = txs->txs_mbuf;
 	struct livengood_tcpip_ctxdesc *t;
 	uint32_t ipcs, tucs, cmd, cmdlen, seg;
 	uint32_t ipcse;
 	struct ether_header *eh;
 	int offset, iphl;
 	uint8_t fields;
 	/*
 	 * XXX It would be nice if the mbuf pkthdr had offset
 	 * fields for the protocol headers.
 	 */
 	eh = mtod(m0, struct ether_header *);
 	switch (htons(eh->ether_type)) {
 	case ETHERTYPE_IP:
 	case ETHERTYPE_IPV6:
 		offset = ETHER_HDR_LEN;
 		break;
 	case ETHERTYPE_VLAN:
 		offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
 		break;
 	default:
 		/* Don't support this protocol or encapsulation. */
  		txq->txq_last_hw_cmd = txq->txq_last_hw_fields = 0;
  		txq->txq_last_hw_ipcs = 0;
  		txq->txq_last_hw_tucs = 0;
 		*fieldsp = 0;
 		*cmdp = 0;
 		return;
+	}
 	if ((m0->m_pkthdr.csum_flags &
 	    (M_CSUM_TSOv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_IPv4)) != 0) {
 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
 	} else
 		iphl = M_CSUM_DATA_IPv6_IPHL(m0->m_pkthdr.csum_data);
 	ipcse = offset + iphl - 1;
 	cmd = WTX_CMD_DEXT | WTX_DTYP_D;
 	cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE;
 	seg = 0;
 	fields = 0;
 	if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
 		int hlen = offset + iphl;
 		bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
 		if (__predict_false(m0->m_len <
 				    (hlen + sizeof(struct tcphdr)))) {
 			/*
 			 * TCP/IP headers are not in the first mbuf; we need
 			 * to do this the slow and painful way. Let's just
 			 * hope this doesn't happen very often.
 			 */
 			struct tcphdr th;
 			WM_Q_EVCNT_INCR(txq, tsopain);
 			m_copydata(m0, hlen, sizeof(th), &th);
 			if (v4) {
 				struct ip ip;
 				m_copydata(m0, offset, sizeof(ip), &ip);
 				ip.ip_len = 0;
 				m_copyback(m0,
 				    offset + offsetof(struct ip, ip_len),
 				    sizeof(ip.ip_len), &ip.ip_len);
 				th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
 				    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
 			} else {
 				struct ip6_hdr ip6;
 				m_copydata(m0, offset, sizeof(ip6), &ip6);
 				ip6.ip6_plen = 0;
 				m_copyback(m0,
 				    offset + offsetof(struct ip6_hdr, ip6_plen),
 				    sizeof(ip6.ip6_plen), &ip6.ip6_plen);
 				th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
 				    &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
+			}
 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
 			    sizeof(th.th_sum), &th.th_sum);
 			hlen += th.th_off << 2;
 		} else {
 			/*
 			 * TCP/IP headers are in the first mbuf; we can do
 			 * this the easy way.
 			 */
 			struct tcphdr *th;
 			if (v4) {
 				struct ip *ip =
 				    (void *)(mtod(m0, char *) + offset);
 				th = (void *)(mtod(m0, char *) + hlen);
 				ip->ip_len = 0;
 				th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
 				    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
 			} else {
 				struct ip6_hdr *ip6 =
 				    (void *)(mtod(m0, char *) + offset);
 				th = (void *)(mtod(m0, char *) + hlen);
 				ip6->ip6_plen = 0;
 				th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
 				    &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
+			}
 			hlen += th->th_off << 2;
+		}
 		if (v4) {
 			WM_Q_EVCNT_INCR(txq, tso);
 			cmdlen |= WTX_TCPIP_CMD_IP;
 		} else {
 			WM_Q_EVCNT_INCR(txq, tso6);
 			ipcse = 0;
+		}
 		cmd |= WTX_TCPIP_CMD_TSE;
 		cmdlen |= WTX_TCPIP_CMD_TSE |
 		    WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen);
 		seg = WTX_TCPIP_SEG_HDRLEN(hlen) |
 		    WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz);
+	}
 	/*
 	 * NOTE: Even if we're not using the IP or TCP/UDP checksum
 	 * offload feature, if we load the context descriptor, we
 	 * MUST provide valid values for IPCSS and TUCSS fields.
 	 */
 	ipcs = WTX_TCPIP_IPCSS(offset) |
 	    WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) |
 	    WTX_TCPIP_IPCSE(ipcse);
 	if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4 | M_CSUM_TSOv4)) {
 		WM_Q_EVCNT_INCR(txq, ipsum);