 @@ -1,14 +1,14 @@
-/*	$NetBSD: libnvmm_x86.c,v 1.40 2020/09/05 07:22:25 maxv Exp $	*/
+/*	$NetBSD: libnvmm_x86.c,v 1.41 2020/10/30 21:06:13 reinoud Exp $	*/
 /*
  * Copyright (c) 2018-2020 Maxime Villard, m00nbsd.net
  * All rights reserved.
+ *
  * This code is part of the NVMM hypervisor.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -1041,26 +1041,27 @@ struct x86_decode_fsm {
 	uint8_t *buf;
 	uint8_t *end;
 };
 struct x86_opcode {
 	bool valid:1;
 	bool regmodrm:1;
 	bool regtorm:1;
 	bool dmo:1;
 	bool todmo:1;
 	bool movs:1;
 	bool stos:1;
 	bool lods:1;
 	bool cmps:1;
 	bool szoverride:1;
 	bool group1:1;
 	bool group3:1;
 	bool group11:1;
 	bool immediate:1;
 	uint8_t defsize;
 	uint8_t flags;
 	const struct x86_emul *emul;
 };
 struct x86_group_entry {
 	const struct x86_emul *emul;
 };
 @@ -1453,26 +1454,46 @@ static const struct x86_opcode primary_o
 		.defsize = OPSIZE_BYTE,
 		.emul = &x86_emul_movs
 	},
 	[0xA5] = {
 		/* Yv, Xv */
 		.valid = true,
 		.movs = true,
 		.szoverride = true,
 		.defsize = -1,
 		.emul = &x86_emul_movs
 	},
 	/*
 	 * CMPS
 	 */
 	[0xA6] = {
 		/* Yb, Xb */
 		.valid = true,
 		.cmps = true,
 		.szoverride = false,
 		.defsize = OPSIZE_BYTE,
 		.emul = &x86_emul_cmp
 	},
 	[0xA7] = {
 		/* Yv, Xv */
 		.valid = true,
 		.cmps = true,
 		.szoverride = true,
 		.defsize = -1,
 		.emul = &x86_emul_cmp
 	},
 	/*
 	 * STOS
 	 */
 	[0xAA] = {
 		/* Yb, AL */
 		.valid = true,
 		.stos = true,
 		.szoverride = false,
 		.defsize = OPSIZE_BYTE,
 		.emul = &x86_emul_stos
 	},
 	[0xAB] = {
 		/* Yv, rAX */
 		.valid = true,
 @@ -1861,26 +1882,55 @@ node_movs(struct x86_decode_fsm *fsm, st
 	/* ES:RDI, force ES */
 	instr->dst.type = STORE_REG;
 	instr->dst.u.reg = &gpr_map__special[1][3][adrsize-1];
 	instr->dst.disp.type = DISP_0;
 	instr->dst.hardseg = NVMM_X64_SEG_ES;
 	fsm_advance(fsm, 0, NULL);
 	return 0;
+}
 /*
  * Special node, for CMPS. Fake two displacements of zero on the source and
  * destination registers.
  * XXX coded as clone of movs as its similar in register usage
  * XXX might be merged with node_movs()
  */
 static int
 node_cmps(struct x86_decode_fsm *fsm, struct x86_instr *instr)
+{
 	size_t adrsize;
 	adrsize = instr->address_size;
 	/* DS:RSI */
 	instr->src.type = STORE_REG;
 	instr->src.u.reg = &gpr_map__special[1][2][adrsize-1];
 	instr->src.disp.type = DISP_0;
 	/* ES:RDI, force ES */
 	instr->dst.type = STORE_REG;
 	instr->dst.u.reg = &gpr_map__special[1][3][adrsize-1];
 	instr->dst.disp.type = DISP_0;
 	instr->dst.hardseg = NVMM_X64_SEG_ES;
 	fsm_advance(fsm, 0, NULL);
 	return 0;
+}
 /*
  * Special node, for STOS and LODS. Fake a displacement of zero on the
  * destination register.
  */
 static int
 node_stlo(struct x86_decode_fsm *fsm, struct x86_instr *instr)
+{
 	const struct x86_opcode *opcode = instr->opcode;
 	struct x86_store *stlo, *streg;
 	size_t adrsize, regsize;
 	adrsize = instr->address_size;
 	regsize = instr->operand_size;
 @@ -2460,26 +2510,28 @@ node_primary_opcode(struct x86_decode_fs
 		/* Zero-extend to 64 bits. */
 		instr->zeroextend_mask = ~size_to_mask(4);
+	}
 	if (opcode->regmodrm) {
 		fsm_advance(fsm, 1, node_regmodrm);
 	} else if (opcode->dmo) {
 		/* Direct-Memory Offsets */
 		fsm_advance(fsm, 1, node_dmo);
 	} else if (opcode->stos || opcode->lods) {
 		fsm_advance(fsm, 1, node_stlo);
 	} else if (opcode->movs) {
 		fsm_advance(fsm, 1, node_movs);
 	} else if (opcode->cmps) {
 		fsm_advance(fsm, 1, node_cmps);
 	} else {
 		return -1;
+	}
 	return 0;
+}
 static int
 node_secondary_opcode(struct x86_decode_fsm *fsm, struct x86_instr *instr)
+{
 	const struct x86_opcode *opcode;
 	uint8_t byte;
 @@ -2636,28 +2688,36 @@ x86_decode(uint8_t *inst_bytes, size_t i
 	instr->src.hardseg = -1;
 	instr->dst.hardseg = -1;
 	fsm.is64bit = is_64bit(state);
 	fsm.is32bit = is_32bit(state);
 	fsm.is16bit = is_16bit(state);
 	fsm.fn = node_legacy_prefix;
 	fsm.buf = inst_bytes;
 	fsm.end = inst_bytes + inst_len;
 	while (fsm.fn != NULL) {
 		ret = (*fsm.fn)(&fsm, instr);
-		if (ret == -1)
+		if (ret == -1) {
 			printf("\nNVMM: %s missing support for instruction " \
 			       "with max length %ld : [ ", __func__,
 			       inst_len);
 			for (uint i = 0; i < inst_len; i++)
 				printf("%02x ", inst_bytes[i]);
 			printf("], please report to NetBSD!\n\n");
 			fflush(stdout);
 			return -1;
+		}
+	}
 	instr->len = fsm.buf - inst_bytes;
 	return 0;
+}
 /* -------------------------------------------------------------------------- */
 #define EXEC_INSTR(sz, instr)						\
 static uint##sz##_t							\
 exec_##instr##sz(uint##sz##_t op1, uint##sz##_t op2, uint64_t *rflags)	\
 {									\