 @@ -1,1107 +1,1111 @@
-/*	$NetBSD: pxa2x0_apm.c,v 1.4 2012/11/12 18:00:38 skrll Exp $	*/
+/*	$NetBSD: pxa2x0_apm.c,v 1.5 2020/10/30 22:20:38 christos Exp $	*/
 /*	$OpenBSD: pxa2x0_apm.c,v 1.28 2007/03/29 18:42:38 uwe Exp $	*/
 /*-
  * Copyright (c) 2001 Alexander Guy.  All rights reserved.
  * Copyright (c) 1998-2001 Michael Shalayeff. All rights reserved.
  * Copyright (c) 1995 John T. Kohl.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by the University of
  *	California, Berkeley and its contributors.
  * 4. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  */
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/kthread.h>
 #include <sys/lock.h>
 #include <sys/mount.h>		/* for vfs_syncwait() */
 #include <sys/proc.h>
 #include <sys/device.h>
 #include <sys/fcntl.h>
 #include <sys/ioctl.h>
 #include <sys/event.h>
 #include <machine/cpu.h>
 #include <machine/apmvar.h>
 #include <arm/xscale/pxa2x0reg.h>
 #include <arm/xscale/pxa2x0var.h>
 #include <arm/xscale/pxa2x0_apm.h>
 #include <arm/xscale/pxa2x0_gpio.h>
 #if defined(APMDEBUG)
 #define DPRINTF(x)	printf x
 #else
 #define	DPRINTF(x)	/**/
 #endif
 #define APM_LOCK(sc)    lockmgr(&(sc)->sc_lock, LK_EXCLUSIVE, NULL)
 #define APM_UNLOCK(sc)  lockmgr(&(sc)->sc_lock, LK_RELEASE, NULL)
 #define	APMUNIT(dev)	(minor(dev)&0xf0)
 #define	APMDEV(dev)	(minor(dev)&0x0f)
 #define APMDEV_NORMAL	0
 #define APMDEV_CTL	8
 int	apm_userstandbys;
 int	apm_suspends;
 int	apm_battlow;
 extern struct cfdriver zapm_cd;
 /* battery percentage at which we get verbose in our warnings.  This
    value can be changed using sysctl(8), value machdep.apmwarn.
    Setting it to zero kills all warnings */
 int	cpu_apmwarn = 10;
 void	apm_power_print(struct pxa2x0_apm_softc *, struct apm_power_info *);
 void	apm_power_info(struct pxa2x0_apm_softc *, struct apm_power_info *);
 void	apm_suspend(struct pxa2x0_apm_softc *);
 void	apm_resume(struct pxa2x0_apm_softc *);
 int	apm_get_event(struct pxa2x0_apm_softc *, u_int *);
 int	apm_handle_event(struct pxa2x0_apm_softc *, u_int);
 void	apm_thread_create(void *);
 void	apm_thread(void *);
 #if 0
 extern int perflevel;
 #endif
 int	freq;
 void	pxa2x0_setperf(int speed);
 int	pxa2x0_cpuspeed(int *speed);
 int	apm_record_event(struct pxa2x0_apm_softc *, u_int);
 #if 0
 void	filt_apmrdetach(struct knote *kn);
 int	filt_apmread(struct knote *kn, long hint);
 int	apmkqfilter(dev_t dev, struct knote *kn);
-struct filterops apmread_filtops =
+static const struct filterops apmread_filtops = {
-	{ 1, NULL, filt_apmrdetach, filt_apmread};
+	.f_isfd = 1,
 	.f_attach = NULL,
 	.f_detach = filt_apmrdetach,
 	.f_event = filt_apmread,
 };
 #endif
 /*
  * Flags to control kernel display
  *	SCFLAG_NOPRINT:		do not output APM power messages due to
  *				a power change event.
+ *
  *	SCFLAG_PCTPRINT:	do not output APM power messages due to
  *				to a power change event unless the battery
  *				percentage changes.
  */
 #define SCFLAG_NOPRINT	0x0008000
 #define SCFLAG_PCTPRINT	0x0004000
 #define SCFLAG_PRINT	(SCFLAG_NOPRINT|SCFLAG_PCTPRINT)
 #define	SCFLAG_OREAD 	(1 << 0)
 #define	SCFLAG_OWRITE	(1 << 1)
 #define	SCFLAG_OPEN	(SCFLAG_OREAD|SCFLAG_OWRITE)
 /* This structure must be kept in sync with pxa2x0_apm_asm.S. */
 struct pxa2x0_memcfg {
 	/* SDRAM refresh */
 	uint32_t mdrefr_high;		/* 0x00 */
 	uint32_t mdrefr_low;		/* 0x04 */
 	uint32_t mdrefr_low2;		/* 0x08 */
 	/* Synchronous, static, or VLIO interfaces */
 	uint32_t msc_high[3];		/* 0x0c */
 	uint32_t msc_low[3];		/* 0x18 */
 	/* XXX move up */
 	uint32_t mdrefr_91;		/* 0x24 */
 };
 /* XXX */
 #define MDREFR_C3000	(MDREFR_K0DB2 | MDREFR_E1PIN | MDREFR_K1RUN |	\
 	    MDREFR_K1DB2 | MDREFR_K2DB2 | MDREFR_APD)
 #define MSC0_HIGH							\
 	( 7 << MSC_RRR_SHIFT << 16) |					\
 	(15 << MSC_RDN_SHIFT << 16) |					\
 	(15 << MSC_RDF_SHIFT << 16) |					\
 	(MSC_RT_NONBURST     << 16) |					\
 	( 2 << MSC_RRR_SHIFT)       |					\
 	(13 << MSC_RDN_SHIFT)       |					\
 	(13 << MSC_RDF_SHIFT)       |					\
 	MSC_RBW	/* PXA271 */        |					\
 	MSC_RT_NONBURST
 #define MSC1_HIGH							\
 	( 7 << MSC_RRR_SHIFT << 16) |					\
 	(15 << MSC_RDN_SHIFT << 16) |					\
 	(15 << MSC_RDF_SHIFT << 16) |					\
 	(MSC_RT_VLIO         << 16) |					\
 	( 3 << MSC_RRR_SHIFT)       |					\
 	( 4 << MSC_RDN_SHIFT)       |					\
 	(13 << MSC_RDF_SHIFT)       |					\
 	MSC_RT_VLIO
 #define MSC2_HIGH							\
 	( 7 << MSC_RRR_SHIFT << 16) |					\
 	(15 << MSC_RDN_SHIFT << 16) |					\
 	(15 << MSC_RDF_SHIFT << 16) |					\
 	(MSC_RT_NONBURST     << 16) |					\
 	( 3 << MSC_RRR_SHIFT)       |					\
 	( 4 << MSC_RDN_SHIFT)       |					\
 	(13 << MSC_RDF_SHIFT)       |					\
 	MSC_RT_VLIO
 #define MSC0_LOW							\
 	( 7 << MSC_RRR_SHIFT << 16) |					\
 	(15 << MSC_RDN_SHIFT << 16) |					\
 	(15 << MSC_RDF_SHIFT << 16) |					\
 	(MSC_RT_NONBURST     << 16) |					\
 	( 1 << MSC_RRR_SHIFT)       |					\
 	( 8 << MSC_RDN_SHIFT)       |					\
 	( 8 << MSC_RDF_SHIFT)       |					\
 	MSC_RBW	/* PXA271 */        |					\
 	MSC_RT_NONBURST
 #define MSC1_LOW							\
 	( 7 << MSC_RRR_SHIFT << 16) |					\
 	(15 << MSC_RDN_SHIFT << 16) |					\
 	(15 << MSC_RDF_SHIFT << 16) |					\
 	(MSC_RT_VLIO         << 16) |					\
 	( 1 << MSC_RRR_SHIFT)       |					\
 	( 2 << MSC_RDN_SHIFT)       |					\
 	( 6 << MSC_RDF_SHIFT)       |					\
 	MSC_RT_VLIO
 #define MSC2_LOW							\
 	( 7 << MSC_RRR_SHIFT << 16) |					\
 	(15 << MSC_RDN_SHIFT << 16) |					\
 	(15 << MSC_RDF_SHIFT << 16) |					\
 	(MSC_RT_NONBURST     << 16) |					\
 	( 1 << MSC_RRR_SHIFT)       |					\
 	( 2 << MSC_RDN_SHIFT)       |					\
 	( 6 << MSC_RDF_SHIFT)       |					\
 	MSC_RT_VLIO
 struct pxa2x0_memcfg pxa2x0_memcfg = {
 	(MDREFR_C3000 | 0x030),
 		(MDREFR_C3000 | 0x00b),
 		(MDREFR_C3000 | 0x017),
 	{ MSC0_HIGH, MSC1_HIGH, MSC2_HIGH },
 	{ MSC1_LOW, MSC1_LOW, MSC2_LOW },
 		(MDREFR_C3000 | 0x013)
 };
 #define PI2C_RETRY_COUNT	10
 /* XXX varies depending on voltage regulator IC. */
 #define PI2C_VOLTAGE_LOW	0x13	/* 1.00V */
 #define PI2C_VOLTAGE_HIGH	0x1a	/* 1.35V */
 void	pxa2x0_pi2c_open(bus_space_tag_t, bus_space_handle_t);
 void	pxa2x0_pi2c_close(bus_space_tag_t, bus_space_handle_t);
 int	pxa2x0_pi2c_read(bus_space_tag_t, bus_space_handle_t, u_char, u_char *);
 int	pxa2x0_pi2c_write(bus_space_tag_t, bus_space_handle_t, u_char, u_char);
 int	pxa2x0_pi2c_getvoltage(bus_space_tag_t, bus_space_handle_t, u_char *);
 int	pxa2x0_pi2c_setvoltage(bus_space_tag_t, bus_space_handle_t, u_char);
 #if 0
 void	pxa2x0_pi2c_print(struct pxa2x0_apm_softc *);
 #endif
 /* XXX used in pxa2x0_apm_asm.S */
 bus_space_handle_t pxa2x0_gpio_ioh;
 bus_space_handle_t pxa2x0_clkman_ioh;
 bus_space_handle_t pxa2x0_memctl_ioh;
 /* pxa2x0_apm_asm.S */
 void	pxa27x_run_mode(void);
 void	pxa27x_fastbus_run_mode(int, uint32_t);
 void	pxa27x_frequency_change(int, int, struct pxa2x0_memcfg *);
 void	pxa2x0_cpu_suspend(void);
 void	pxa2x0_cpu_resume(void);
 void	pxa27x_cpu_speed_high(void);
 void	pxa27x_cpu_speed_low(void);
 void	pxa27x_cpu_speed_91(void);
 void	pxa27x_cpu_speed_208(void);
 void
 apm_power_print(struct pxa2x0_apm_softc *sc, struct apm_power_info *powerp)
+{
 	if (powerp->battery_life != APM_BATT_LIFE_UNKNOWN)
 		printf("%s: battery life expectancy %d%%\n",
 		    device_xname(sc->sc_dev), powerp->battery_life);
 	printf("%s: AC ", device_xname(sc->sc_dev));
 	switch (powerp->ac_state) {
 	case APM_AC_OFF:
 		printf("off,");
 		break;
 	case APM_AC_ON:
 		printf("on,");
 		break;
 	case APM_AC_BACKUP:
 		printf("backup power,");
 		break;
 	default:
 	case APM_AC_UNKNOWN:
 		printf("unknown,");
 		break;
+	}
 	printf(" battery is ");
 	switch (powerp->battery_state) {
 	case APM_BATT_HIGH:
 		printf("high");
 		break;
 	case APM_BATT_LOW:
 		printf("low");
 		break;
 	case APM_BATT_CRITICAL:
 		printf("CRITICAL");
 		break;
 	case APM_BATT_CHARGING:
 		printf("charging");
 		break;
 	case APM_BATT_UNKNOWN:
 		printf("unknown");
 		break;
 	default:
 		printf("undecoded (%x)", powerp->battery_state);
 		break;
+	}
 	printf("\n");
+}
 void
 apm_power_info(struct pxa2x0_apm_softc *sc,
     struct apm_power_info *power)
+{
 	power->ac_state = APM_AC_UNKNOWN;
 	power->battery_state = APM_BATT_UNKNOWN;
 	power->battery_life = 0 /* APM_BATT_LIFE_UNKNOWN */;
 	power->minutes_left = 0;
 	if (sc->sc_power_info != NULL)
 		sc->sc_power_info(sc, power);
+}
 void
 apm_suspend(struct pxa2x0_apm_softc *sc)
+{
 	resettodr();
 	dopowerhooks(PWR_SUSPEND);
 #if 0
 	if (cold)
 		vfs_syncwait(0);
 #endif
 	if (sc->sc_suspend == NULL)
 		pxa2x0_wakeup_config(PXA2X0_WAKEUP_ALL, 1);
 	else
 		sc->sc_suspend(sc);
 	pxa2x0_apm_sleep(sc);
+}
 void
 apm_resume(struct pxa2x0_apm_softc *sc)
+{
 	dopowerhooks(PWR_RESUME);
 	inittodr(0);
 	/*
 	 * Clear the OTG Peripheral hold after running the pxaudc and pxaohci
 	 * powerhooks to re-enable their operation. See 3.8.1.2
 	 */
 	/* XXX ifdef NPXAUDC > 0 */
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PSSR, PSSR_OTGPH);
+}
 #if 0
 int
 apm_get_event(struct pxa2x0_apm_softc *sc, u_int *typep)
+{
 	if (sc->sc_get_event != NULL)
 		return (sc->sc_get_event(sc, typep));
 	*typep = APM_NOEVENT;
 	return (1);
+}
 int
 apm_handle_event(struct pxa2x0_apm_softc *sc, u_int type)
+{
 	struct	apm_power_info power;
 	int	ret = 0;
 	switch (type) {
 	case APM_NOEVENT:
 		ret = 1;
 		break;
 	case APM_CRIT_SUSPEND_REQ:
 		DPRINTF(("suspend required immediately\n"));
 #if 0
 		/* XXX apmd would make us suspend again after resume. */
 		(void)apm_record_event(sc, type);
 #endif
 		/*
 		 * We ignore APM_CRIT_RESUME and just suspend here as usual
 		 * to simplify the actual apm_get_event() implementation.
 		 */
 		apm_suspends++;
 		ret = 1;
 		break;
 	case APM_USER_SUSPEND_REQ:
 	case APM_SUSPEND_REQ:
 		DPRINTF(("suspend requested\n"));
 		if (apm_record_event(sc, type)) {
 			DPRINTF(("suspend ourselves\n"));
 			apm_suspends++;
+		}
 		break;
 	case APM_POWER_CHANGE:
 		DPRINTF(("power status change\n"));
 		apm_power_info(sc, &power);
 		if (power.battery_life != APM_BATT_LIFE_UNKNOWN &&
 		    power.battery_life < cpu_apmwarn &&
 		    (sc->sc_flags & SCFLAG_PRINT) != SCFLAG_NOPRINT &&
 		    ((sc->sc_flags & SCFLAG_PRINT) != SCFLAG_PCTPRINT ||
 			sc->sc_batt_life != power.battery_life)) {
 			sc->sc_batt_life = power.battery_life;
 			apm_power_print(sc, &power);
+		}
 		apm_record_event(sc, type);
 		break;
 	case APM_BATTERY_LOW:
 		DPRINTF(("Battery low!\n"));
 		apm_battlow++;
 		apm_record_event(sc, type);
 		break;
 	default:
 		DPRINTF(("apm_handle_event: unsupported event, code %d\n",
 			type));
+	}
 	return (ret);
+}
 void
 apm_thread_create(void *v)
+{
 	struct pxa2x0_apm_softc *sc = v;
 	if (kthread_create(apm_thread, sc, &sc->sc_thread,
 		"%s", device_xname(sc->sc_dev))) {
 		/* apm_disconnect(sc); */
 		printf("%s: failed to create kernel thread, disabled",
 		    device_xname(sc->sc_dev));
+	}
+}
 void
 apm_thread(void *v)
+{
 	struct pxa2x0_apm_softc *sc = v;
 	u_int	type;
 	for (;;) {
 		APM_LOCK(sc);
 		while (1) {
 			if (apm_get_event(sc, &type) != 0)
 				break;
 			if (apm_handle_event(sc, type) != 0)
 				break;
+		}
 		if (apm_suspends || apm_userstandbys /* || apm_battlow*/) {
 			apm_suspend(sc);
 			apm_resume(sc);
+		}
 		apm_battlow = apm_suspends = apm_userstandbys = 0;
 		APM_UNLOCK(sc);
 		kpause("apmev", false, hz, NULL);
+	}
+}
 int
 apmopen(dev_t dev, int flag, int mode, struct proc *p)
+{
 	struct pxa2x0_apm_softc *sc;
 	int error = 0;
 	/* apm0 only */
 	if (!zapm_cd.cd_ndevs || APMUNIT(dev) != 0 ||
 	    !(sc = zapm_cd.cd_devs[APMUNIT(dev)]))
 		return (ENXIO);
 	DPRINTF(("apmopen: dev %d pid %d flag %x mode %x\n",
 		APMDEV(dev), p->p_pid, flag, mode));
 	switch (APMDEV(dev)) {
 	case APMDEV_CTL:
 		if (!(flag & FWRITE)) {
 			error = EINVAL;
 			break;
+		}
 		if (sc->sc_flags & SCFLAG_OWRITE) {
 			error = EBUSY;
 			break;
+		}
 		sc->sc_flags |= SCFLAG_OWRITE;
 		break;
 	case APMDEV_NORMAL:
 		if (!(flag & FREAD) || (flag & FWRITE)) {
 			error = EINVAL;
 			break;
+		}
 		sc->sc_flags |= SCFLAG_OREAD;
 		break;
 	default:
 		error = ENXIO;
 		break;
+	}
 	return (error);
+}
 int
 apmclose(dev_t dev, int flag, int mode, struct proc *p)
+{
 	struct pxa2x0_apm_softc *sc;
 	/* apm0 only */
 	if (!apm_cd.cd_ndevs || APMUNIT(dev) != 0 ||
 	    !(sc = apm_cd.cd_devs[APMUNIT(dev)]))
 		return (ENXIO);
 	DPRINTF(("apmclose: pid %d flag %x mode %x\n", p->p_pid, flag, mode));
 	switch (APMDEV(dev)) {
 	case APMDEV_CTL:
 		sc->sc_flags &= ~SCFLAG_OWRITE;
 		break;
 	case APMDEV_NORMAL:
 		sc->sc_flags &= ~SCFLAG_OREAD;
 		break;
+	}
 	return (0);
+}
 int
 apmioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
+{
 	struct pxa2x0_apm_softc *sc;
 	struct apm_power_info *power;
 	int error = 0;
 	/* apm0 only */
 	if (!apm_cd.cd_ndevs || APMUNIT(dev) != 0 ||
 	    !(sc = apm_cd.cd_devs[APMUNIT(dev)]))
 		return (ENXIO);
 	switch (cmd) {
 		/* some ioctl names from linux */
 	case APM_IOC_STANDBY:
 		if ((flag & FWRITE) == 0)
 			error = EBADF;
 		else
 			apm_userstandbys++;
 		break;
 	case APM_IOC_SUSPEND:
 		if ((flag & FWRITE) == 0)
 			error = EBADF;
 		else
 			apm_suspends++;	/* XXX */
 		break;
 	case APM_IOC_PRN_CTL:
 		if ((flag & FWRITE) == 0)
 			error = EBADF;
 		else {
 			int flag = *(int *)data;
 			DPRINTF(( "APM_IOC_PRN_CTL: %d\n", flag ));
 			switch (flag) {
 			case APM_PRINT_ON:	/* enable printing */
 				sc->sc_flags &= ~SCFLAG_PRINT;
 				break;
 			case APM_PRINT_OFF: /* disable printing */
 				sc->sc_flags &= ~SCFLAG_PRINT;
 				sc->sc_flags |= SCFLAG_NOPRINT;
 				break;
 			case APM_PRINT_PCT: /* disable some printing */
 				sc->sc_flags &= ~SCFLAG_PRINT;
 				sc->sc_flags |= SCFLAG_PCTPRINT;
 				break;
 			default:
 				error = EINVAL;
 				break;
+			}
+		}
 		break;
 	case APM_IOC_DEV_CTL:
 		if ((flag & FWRITE) == 0)
 			error = EBADF;
 		break;
 	case APM_IOC_GETPOWER:
 	        power = (struct apm_power_info *)data;
 		apm_power_info(sc, power);
 		break;
 	default:
 		error = ENOTTY;
+	}
 	return (error);
+}
 int
 apm_record_event(struct pxa2x0_apm_softc *sc, u_int type)
+{
 	static int apm_evindex;
 	/* skip if no user waiting */
 	if ((sc->sc_flags & SCFLAG_OPEN) == 0)
 		return (1);
 	apm_evindex++;
 	KNOTE(&sc->sc_note, APM_EVENT_COMPOSE(type, apm_evindex));
 	return (0);
+}
 void
 filt_apmrdetach(struct knote *kn)
+{
 	struct pxa2x0_apm_softc *sc =
 	    (struct pxa2x0_apm_softc *)kn->kn_hook;
 	SLIST_REMOVE(&sc->sc_note, kn, knote, kn_selnext);
+}
 int
 filt_apmread(struct knote *kn, long hint)
+{
 	/* XXX weird kqueue_scan() semantics */
 	if (hint && !kn->kn_data)
 		kn->kn_data = (int)hint;
 	return (1);
+}
 int
 apmkqfilter(dev_t dev, struct knote *kn)
+{
 	struct pxa2x0_apm_softc *sc;
 	/* apm0 only */
 	if (!apm_cd.cd_ndevs || APMUNIT(dev) != 0 ||
 	    !(sc = apm_cd.cd_devs[APMUNIT(dev)]))
 		return (ENXIO);
 	switch (kn->kn_filter) {
 	case EVFILT_READ:
 		kn->kn_fop = &apmread_filtops;
 		break;
 	default:
 		return (1);
+	}
 	kn->kn_hook = (caddr_t)sc;
 	SLIST_INSERT_HEAD(&sc->sc_note, kn, kn_selnext);
 	return (0);
+}
 void
 pxa2x0_apm_attach_sub(struct pxa2x0_apm_softc *sc)
+{
 	sc->sc_iot = &pxa2x0_bs_tag;
 	if (bus_space_map(sc->sc_iot, PXA2X0_POWMAN_BASE,
 		PXA2X0_POWMAN_SIZE, 0, &sc->sc_pm_ioh)) {
 		printf("pxa2x0_apm_attach_sub: failed to map POWMAN\n");
 		return;
+	}
 	lockinit(&sc->sc_lock, PWAIT, "apmlk", 0, 0);
 	kthread_create_deferred(apm_thread_create, sc);
 	printf("\n");
 	if (bus_space_map(sc->sc_iot, PXA2X0_CLKMAN_BASE, PXA2X0_CLKMAN_SIZE,
 , &pxa2x0_clkman_ioh)) {
 		printf("%s: failed to map CLKMAN\n", device_xname(sc->sc_dev));
 		return;
+	}
 	if (bus_space_map(sc->sc_iot, PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE,
 , &pxa2x0_memctl_ioh)) {
 		printf("%s: failed to map MEMCTL\n", device_xname(sc->sc_dev));
 		return;
+	}
 	sc->sc_memctl_ioh = pxa2x0_memctl_ioh;
 	if (bus_space_map(sc->sc_iot, PXA2X0_GPIO_BASE, PXA2X0_GPIO_SIZE,
 , &pxa2x0_gpio_ioh)) {
 		printf("%s: can't map GPIO\n", device_xname(sc->sc_dev));
 		return;
+	}
 	/* Clear all reset status flags. */
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_RCSR,
 	    RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR);
+}
 #endif /* 0 */
 void
 pxa2x0_wakeup_config(u_int wsrc, int enable)
+{
 	struct pxa2x0_apm_softc *sc;
 	uint32_t prer;
 	uint32_t pfer;
 	uint32_t pkwr;
 	if (zapm_cd.cd_ndevs < 1 || zapm_cd.cd_devs[0] == NULL)
 		return;
 	sc = device_private(zapm_cd.cd_devs[0]);
 	prer = pfer = pkwr = 0;
 	if ((wsrc & PXA2X0_WAKEUP_POWERON) != 0) {
 		prer |= (1<<0);
 		pfer |= (1<<0);
 		pkwr |= (1<<12); /* XXX */
+	}
 	if ((wsrc & PXA2X0_WAKEUP_GPIORST) != 0)
 		pfer |= (1<<1);
 	if ((wsrc & PXA2X0_WAKEUP_SD) != 0)
 		prer |= (1<<9);
 	if ((wsrc & PXA2X0_WAKEUP_RC) != 0)
 		prer |= (1<<13);
 	if ((wsrc & PXA2X0_WAKEUP_SYNC) != 0)
 		pkwr |= (1<<1);
 	if ((wsrc & PXA2X0_WAKEUP_KEYNS0) != 0)
 		prer |= (1<<12);
 	if ((wsrc & PXA2X0_WAKEUP_KEYNS1) != 0)
 		pkwr |= (1<<2);
 	if ((wsrc & PXA2X0_WAKEUP_KEYNS2) != 0)
 		pkwr |= (1<<9);
 	if ((wsrc & PXA2X0_WAKEUP_KEYNS3) != 0)
 		pkwr |= (1<<3);
 	if ((wsrc & PXA2X0_WAKEUP_KEYNS4) != 0)
 		pkwr |= (1<<4);
 	if ((wsrc & PXA2X0_WAKEUP_KEYNS5) != 0)
 		pkwr |= (1<<6);
 	if ((wsrc & PXA2X0_WAKEUP_KEYNS6) != 0)
 		pkwr |= (1<<7);
 	if ((wsrc & PXA2X0_WAKEUP_CF0) != 0)
 		pkwr |= (1<<11);
 	if ((wsrc & PXA2X0_WAKEUP_CF1) != 0)
 		pkwr |= (1<<10);
 	if ((wsrc & PXA2X0_WAKEUP_USBD) != 0)
 		prer |= (1<<24);
 	if ((wsrc & PXA2X0_WAKEUP_LOCKSW) != 0) {
 		prer |= (1<<15);
 		pfer |= (1<<15);
+	}
 	if ((wsrc & PXA2X0_WAKEUP_JACKIN) != 0) {
 		prer |= (1<<23);
 		pfer |= (1<<23);
+	}
 	if ((wsrc & PXA2X0_WAKEUP_CHRGFULL) != 0)
 		pkwr |= (1<<18);
 	if ((wsrc & PXA2X0_WAKEUP_RTC) != 0)
 		prer |= (1<<31);
 	if (enable) {
 		sc->sc_wakeon |= wsrc;
 		prer |= bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh,
 		    POWMAN_PRER);
 		pfer |= bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh,
 		    POWMAN_PFER);
 		pkwr |= bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh,
 		    POWMAN_PKWR);
 	} else {
 		sc->sc_wakeon &= ~wsrc;
 		prer = bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh,
 		    POWMAN_PRER) & ~prer;
 		pfer = bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh,
 		    POWMAN_PFER) & ~pfer;
 		pkwr = bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh,
 		    POWMAN_PKWR) & ~pkwr;
+	}
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PKWR, pkwr);
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PRER, prer);
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PFER, pfer);
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PWER,
 	    prer | pfer);
+}
 u_int
 pxa2x0_wakeup_status(void)
+{
 	struct pxa2x0_apm_softc *sc;
 	uint32_t rv;
 	u_int	wsrc;
 	if (zapm_cd.cd_ndevs < 1 || zapm_cd.cd_devs[0] == NULL)
 		return (0);
 	sc = device_private(zapm_cd.cd_devs[0]);
 	wsrc = 0;
 	rv = bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PEDR);
 	if ((rv & (1<<0)) != 0)
 		wsrc |= PXA2X0_WAKEUP_POWERON;
 	if ((rv & (1<<1)) != 0)
 		wsrc |= PXA2X0_WAKEUP_GPIORST;
 	if ((rv & (1<<9)) != 0)
 		wsrc |= PXA2X0_WAKEUP_SD;
 	if ((rv & (1<<12)) != 0)
 		wsrc |= PXA2X0_WAKEUP_KEYNS0;
 	if ((rv & (1<<13)) != 0)
 		wsrc |= PXA2X0_WAKEUP_RC;
 	if ((rv & (1<<15)) != 0)
 		wsrc |= PXA2X0_WAKEUP_LOCKSW;
 	if ((rv & (1<<23)) != 0)
 		wsrc |= PXA2X0_WAKEUP_JACKIN;
 	if ((rv & (1<<24)) != 0)
 		wsrc |= PXA2X0_WAKEUP_USBD;
 	if ((rv & (1<<31)) != 0)
 		wsrc |= PXA2X0_WAKEUP_RTC;
 	rv = bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PKSR);
 	if ((rv & (1<<1)) != 0)
 		wsrc |= PXA2X0_WAKEUP_SYNC;
 	if ((rv & (1<<2)) != 0)
 		wsrc |= PXA2X0_WAKEUP_KEYNS1;
 	if ((rv & (1<<9)) != 0)
 		wsrc |= PXA2X0_WAKEUP_KEYNS2;
 	if ((rv & (1<<3)) != 0)
 		wsrc |= PXA2X0_WAKEUP_KEYNS3;
 	if ((rv & (1<<4)) != 0)
 		wsrc |= PXA2X0_WAKEUP_KEYNS4;
 	if ((rv & (1<<6)) != 0)
 		wsrc |= PXA2X0_WAKEUP_KEYNS5;
 	if ((rv & (1<<7)) != 0)
 		wsrc |= PXA2X0_WAKEUP_KEYNS6;
 	if ((rv & (1<<10)) != 0)
 		wsrc |= PXA2X0_WAKEUP_CF1;
 	if ((rv & (1<<11)) != 0)
 		wsrc |= PXA2X0_WAKEUP_CF0;
 	if ((rv & (1<<12)) != 0)
 		wsrc |= PXA2X0_WAKEUP_POWERON;
 	if ((rv & (1<<18)) != 0)
 		wsrc |= PXA2X0_WAKEUP_CHRGFULL;
 	return (wsrc);
+}
 struct pxa2x0_sleep_data {
 	/* OS timer registers */
 	uint32_t sd_osmr0, sd_osmr1, sd_osmr2, sd_osmr3;
 	uint32_t sd_oscr0;
 	uint32_t sd_osmr4, sd_osmr5;
 	uint32_t sd_oscr4;
 	uint32_t sd_omcr4, sd_omcr5;
 	uint32_t sd_oier;
 	/* GPIO registers */
 	uint32_t sd_gpdr0, sd_gpdr1, sd_gpdr2, sd_gpdr3;
 	uint32_t sd_grer0, sd_grer1, sd_grer2, sd_grer3;
 	uint32_t sd_gfer0, sd_gfer1, sd_gfer2, sd_gfer3;
 	uint32_t sd_gafr0_l, sd_gafr1_l, sd_gafr2_l, sd_gafr3_l;
 	uint32_t sd_gafr0_u, sd_gafr1_u, sd_gafr2_u, sd_gafr3_u;
 	uint32_t sd_gplr0, sd_gplr1, sd_gplr2, sd_gplr3;
 	/* Interrupt controller registers */
 	uint32_t sd_iclr;
 	uint32_t sd_icmr;
 	uint32_t sd_iccr;
 	/* Memory controller registers */
 	uint32_t sd_mecr;
 	uint32_t sd_mcmem0, sd_mcmem1;
 	uint32_t sd_mcatt0, sd_mcatt1;
 	uint32_t sd_mcio0, sd_mcio1;
 	/* Clocks manager registers */
 	uint32_t sd_cken;
 };
 void
 pxa2x0_apm_sleep(struct pxa2x0_apm_softc *sc)
+{
 	struct pxa2x0_sleep_data sd;
 	bus_space_handle_t ost_ioh;
 	int save;
 	uint32_t rv;
 	ost_ioh = (bus_space_handle_t)0;
 	if (bus_space_map(sc->sc_iot, PXA2X0_OST_BASE, PXA2X0_OST_SIZE, 0,
 		&ost_ioh)) {
 		printf("pxa2x0_apm_sleep: can't map OST\n");
 		goto out;
+	}
 	save = disable_interrupts(I32_bit|F32_bit);
 	sd.sd_oscr0 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSCR0);
 	sd.sd_oscr4 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSCR4);
 	sd.sd_omcr4 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OMCR4);
 	sd.sd_omcr5 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OMCR5);
 	sd.sd_osmr0 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR0);
 	sd.sd_osmr1 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR1);
 	sd.sd_osmr2 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR2);
 	sd.sd_osmr3 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR3);
 	sd.sd_osmr4 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR4);
 	sd.sd_osmr5 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR5);
 	sd.sd_oier = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OIER);
 	/* Bring the PXA27x into 416MHz turbo mode. */
         if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA27X &&
 	    bus_space_read_4(sc->sc_iot, pxa2x0_clkman_ioh, CLKMAN_CCCR) !=
 	    (CCCR_A | CCCR_TURBO_X2 | CCCR_RUN_X16)) {
 #if 0
 		pxa27x_cpu_speed_high();
 #else
 #define CLKCFG_T		(1<<0)	/* turbo */
 #define CLKCFG_F		(1<<1)	/* frequency change */
 #define CLKCFG_B		(1<<3)	/* fast-bus */
 		pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X2 |
 		    CCCR_RUN_X16, CLKCFG_B | CLKCFG_F | CLKCFG_T,
 		    &pxa2x0_memcfg);
 #endif
 		delay(500000); /* XXX */
+	}
 suspend_again:
 	/* Clear wake-up status. */
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PEDR,
 xffffffff);
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PKSR,
 xffffffff);
 	/* XXX control battery charging in sleep mode. */
 	/* XXX schedule RTC alarm to check the battery, or schedule
 	   XXX wake-up shortly before an already programmed alarm? */
 	pxa27x_run_mode();
 #define MDREFR_LOW		(MDREFR_C3000 | 0x00b)
 	pxa27x_fastbus_run_mode(0, MDREFR_LOW);
 	delay(1);
 #if 1
 	pxa27x_cpu_speed_91();
 #else
 	pxa27x_frequency_change(CCCR_TURBO_X1 | CCCR_RUN_X7, CLKCFG_F,
 	    &pxa2x0_memcfg);
 #endif
 	pxa2x0_pi2c_setvoltage(sc->sc_iot, sc->sc_pm_ioh, PI2C_VOLTAGE_LOW);
 	sd.sd_gpdr0 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR0);
 	sd.sd_gpdr1 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR1);
 	sd.sd_gpdr2 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR2);
 	sd.sd_gpdr3 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR3);
 	sd.sd_grer0 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER0);
 	sd.sd_grer1 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER1);
 	sd.sd_grer2 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER2);
 	sd.sd_grer3 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER3);
 	sd.sd_gfer0 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER0);
 	sd.sd_gfer1 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER1);
 	sd.sd_gfer2 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER2);
 	sd.sd_gfer3 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER3);
 	sd.sd_gafr0_l = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR0_L);
 	sd.sd_gafr1_l = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR1_L);
 	sd.sd_gafr2_l = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR2_L);
 	sd.sd_gafr3_l = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR3_L);
 	sd.sd_gafr0_u = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR0_U);
 	sd.sd_gafr1_u = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR1_U);
 	sd.sd_gafr2_u = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR2_U);
 	sd.sd_gafr3_u = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR3_U);
 	sd.sd_gplr0 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPLR0);
 	sd.sd_gplr1 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPLR1);
 	sd.sd_gplr2 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPLR2);
 	sd.sd_gplr3 = bus_space_read_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPLR3);
 	sd.sd_iclr = read_icu(INTCTL_ICLR);
 	sd.sd_icmr = read_icu(INTCTL_ICMR);
 	sd.sd_iccr = read_icu(INTCTL_ICCR);
 	write_icu(INTCTL_ICMR, 0);
 	sd.sd_mecr = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh,
 	    MEMCTL_MECR);
 	sd.sd_mcmem0 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh,
 	    MEMCTL_MCMEM(0));
 	sd.sd_mcmem1 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh,
 	    MEMCTL_MCMEM(1));
 	sd.sd_mcatt0 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh,
 	    MEMCTL_MCATT(0));
 	sd.sd_mcatt1 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh,
 	    MEMCTL_MCATT(1));
 	sd.sd_mcio0 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh,
 	    MEMCTL_MCIO(0));
 	sd.sd_mcio1 = bus_space_read_4(sc->sc_iot, pxa2x0_memctl_ioh,
 	    MEMCTL_MCIO(1));
 	sd.sd_cken = bus_space_read_4(sc->sc_iot, pxa2x0_clkman_ioh,
 	    CLKMAN_CKEN);
 	/*
 	 * Stop clocks to all units except to the memory controller, and
 	 * to the keypad controller if it is enabled as a wake-up source.
 	 */
 	rv = CKEN_MEM;
 	if ((sc->sc_wakeon & PXA2X0_WAKEUP_KEYNS_ALL) != 0)
 		rv |= CKEN_KEY;
 	bus_space_write_4(sc->sc_iot, pxa2x0_clkman_ioh, CLKMAN_CKEN, rv);
 	/* Disable nRESET_OUT. */
 	rv = bus_space_read_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PSLR);
 #define  PSLR_SL_ROD	(1<<20)
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PSLR,
 	    rv | PSLR_SL_ROD);
 	/* Clear all reset status flags. */
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_RCSR,
 	    RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR);
 	/* Stop 3/13MHz oscillator; do not float PCMCIA and chip-selects. */
 	rv = PCFR_OPDE;
         if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA27X)
 		/* Enable nRESET_GPIO as a GPIO reset input. */
 		rv |= PCFR_GPR_EN;
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PCFR, rv);
 	/* XXX C3000 */
 #define	GPIO_G0_STROBE_BIT		0x0f800000
 #define	GPIO_G1_STROBE_BIT		0x00100000
 #define	GPIO_G2_STROBE_BIT		0x01000000
 #define	GPIO_G3_STROBE_BIT		0x00041880
 #define	GPIO_KEY_STROBE0		88
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR0,
 x00144018);
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR1,
 x00ef0000);
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR2,
 x0121c000);
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR3,
 x00600000);
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR0,
 x00144018 & ~GPIO_G0_STROBE_BIT);
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR1,
 x00ef0000 & ~GPIO_G1_STROBE_BIT);
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR2,
 x0121c000 & ~GPIO_G2_STROBE_BIT);
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR3,
 x00600000 & ~GPIO_G3_STROBE_BIT);
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PGSR2,
 	    (0x0121c000 & ~GPIO_G2_STROBE_BIT) |
 	    GPIO_BIT(GPIO_KEY_STROBE0));
 	/* C3000 */
 #define GPIO_EXT_BUS_READY	18
 	pxa2x0_gpio_set_function(GPIO_EXT_BUS_READY, GPIO_SET | GPIO_OUT);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR0, 0xd01c4418);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR1, 0xfcefbd21);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR2, 0x13a5ffff);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR3, 0x01e3e10c);
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PSPR,
 	    (uint32_t)&pxa2x0_cpu_resume - 0xc0200000 + 0xa0200000);
 	pxa2x0_cpu_suspend();
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_PSPR, 0);
 	pxa2x0_clkman_config(CKEN_SSP|CKEN_PWM0|CKEN_PWM1, 1);
 	pxa2x0_clkman_config(CKEN_KEY, 0);
 #if 1
 	/* Clear all GPIO interrupt sources. */
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GEDR0, 0xffffffff);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GEDR1, 0xffffffff);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GEDR2, 0xffffffff);
 #endif
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR0, sd.sd_gpdr0);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR1, sd.sd_gpdr1);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR2, sd.sd_gpdr2);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER0, sd.sd_grer0);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER1, sd.sd_grer1);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER2, sd.sd_grer2);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER0, sd.sd_gfer0);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER1, sd.sd_gfer1);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER2, sd.sd_gfer2);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR0_L, sd.sd_gafr0_l);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR1_L, sd.sd_gafr1_l);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR2_L, sd.sd_gafr2_l);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR0_U, sd.sd_gafr0_u);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR1_U, sd.sd_gafr1_u);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR2_U, sd.sd_gafr2_u);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPSR0, sd.sd_gplr0 &
 	    sd.sd_gpdr0);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPSR1, sd.sd_gplr1 &
 	    sd.sd_gpdr1);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPSR2, sd.sd_gplr2 &
 	    sd.sd_gpdr2);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPCR0, ~sd.sd_gplr0 &
 	    sd.sd_gpdr0);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPCR1, ~sd.sd_gplr1 &
 	    sd.sd_gpdr1);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPCR2, ~sd.sd_gplr2 &
 	    sd.sd_gpdr2);
 	/* PXA27x */
 #if 0
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GEDR3, 0xffffffff);
 #endif
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPDR3, sd.sd_gpdr3);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GRER3, sd.sd_grer3);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GFER3, sd.sd_gfer3);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR3_L, sd.sd_gafr3_l);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GAFR3_U, sd.sd_gafr3_u);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPSR3, sd.sd_gplr3 &
 	    sd.sd_gpdr3);
 	bus_space_write_4(sc->sc_iot, pxa2x0_gpio_ioh, GPIO_GPCR3, ~sd.sd_gplr3 &
 	    sd.sd_gpdr3);
 	bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MECR,
 	    sd.sd_mecr);
 	bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCMEM(0),
 	    sd.sd_mcmem0);
 	bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCMEM(1),
 	    sd.sd_mcmem1);
 	bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCATT(0),
 	    sd.sd_mcatt0);
 	bus_space_write_4(sc->sc_iot, pxa2x0_memctl_ioh, MEMCTL_MCATT(1),

 @@ -1,459 +1,463 @@
-/*	$NetBSD: apm.c,v 1.27 2014/07/25 08:10:34 dholland Exp $	*/
+/*	$NetBSD: apm.c,v 1.28 2020/10/30 22:20:38 christos Exp $	*/
 /*	$OpenBSD: apm.c,v 1.5 2002/06/07 07:13:59 miod Exp $	*/
 /*-
  * Copyright (c) 2001 Alexander Guy.  All rights reserved.
  * Copyright (c) 1998-2001 Michael Shalayeff. All rights reserved.
  * Copyright (c) 1995 John T. Kohl.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. Neither the names of the authors nor the names of contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: apm.c,v 1.27 2014/07/25 08:10:34 dholland Exp $");
+__KERNEL_RCSID(0, "$NetBSD: apm.c,v 1.28 2020/10/30 22:20:38 christos Exp $");
 #include "apm.h"
 #if NAPM > 1
 #error only one APM emulation device may be configured
 #endif
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/proc.h>
 #include <sys/device.h>
 #include <sys/fcntl.h>
 #include <sys/ioctl.h>
 #include <sys/mutex.h>
 #ifdef __OpenBSD__
 #include <sys/event.h>
 #endif
 #ifdef __NetBSD__
 #include <sys/select.h>
 #include <sys/poll.h>
 #include <sys/conf.h>
 #endif
 #ifdef __OpenBSD__
 #include <machine/conf.h>
 #endif
 #include <machine/cpu.h>
 #include <machine/apmvar.h>
 #include <macppc/dev/adbvar.h>
 #include <macppc/dev/pm_direct.h>
 #if defined(APMDEBUG)
 #define DPRINTF(x)	printf x
 #else
 #define	DPRINTF(x)	/**/
 #endif
 #define APM_NEVENTS 16
 struct apm_softc {
 	struct selinfo sc_rsel;
 #ifdef __OpenBSD__
 	struct klist sc_note;
 #endif
 	int    sc_flags;
 	int	event_count;
 	int	event_ptr;
 	kmutex_t sc_lock;
 	struct	apm_event_info event_list[APM_NEVENTS];
 };
 /*
  * A brief note on the locking protocol: it's very simple; we
  * assert an exclusive lock any time thread context enters the
  * APM module.  This is both the APM thread itself, as well as
  * user context.
  */
 #ifdef __NetBSD__
 #define	APM_LOCK(apmsc)		mutex_enter(&(apmsc)->sc_lock)
 #define	APM_UNLOCK(apmsc)	mutex_exit(&(apmsc)->sc_lock)
 #else
 #define APM_LOCK(apmsc)
 #define APM_UNLOCK(apmsc)
 #endif
 int apmmatch(device_t, cfdata_t, void *);
 void apmattach(device_t, device_t, void *);
 #ifdef __NetBSD__
 #if 0
 static int	apm_record_event(struct apm_softc *, u_int);
 #endif
 #endif
 CFATTACH_DECL_NEW(apm, sizeof(struct apm_softc),
     apmmatch, apmattach, NULL, NULL);
 #ifdef __OpenBSD__
 struct cfdriver apm_cd = {
 	NULL, "apm", DV_DULL
 };
 #else
 extern struct cfdriver apm_cd;
 dev_type_open(apmopen);
 dev_type_close(apmclose);
 dev_type_ioctl(apmioctl);
 dev_type_poll(apmpoll);
 dev_type_kqfilter(apmkqfilter);
 const struct cdevsw apm_cdevsw = {
 	.d_open = apmopen,
 	.d_close = apmclose,
 	.d_read = noread,
 	.d_write = nowrite,
 	.d_ioctl = apmioctl,
 	.d_stop = nostop,
 	.d_tty = notty,
 	.d_poll = apmpoll,
 	.d_mmap = nommap,
 	.d_kqfilter = apmkqfilter,
 	.d_discard = nodiscard,
 	.d_flag = 0
 };
 #endif
 int	apm_evindex;
 #define	APMUNIT(dev)	(minor(dev)&0xf0)
 #define	APMDEV(dev)	(minor(dev)&0x0f)
 #define APMDEV_NORMAL	0
 #define APMDEV_CTL	8
 /*
  * Flags to control kernel display
  *	SCFLAG_NOPRINT:		do not output APM power messages due to
  *				a power change event.
+ *
  *	SCFLAG_PCTPRINT:	do not output APM power messages due to
  *				to a power change event unless the battery
  *				percentage changes.
  */
 #define SCFLAG_NOPRINT	0x0008000
 #define SCFLAG_PCTPRINT	0x0004000
 #define SCFLAG_PRINT	(SCFLAG_NOPRINT|SCFLAG_PCTPRINT)
 #define	SCFLAG_OREAD 	(1 << 0)
 #define	SCFLAG_OWRITE	(1 << 1)
 #define	SCFLAG_OPEN	(SCFLAG_OREAD|SCFLAG_OWRITE)
 int
 apmmatch(device_t parent, cfdata_t match, void *aux)
+{
 	struct adb_attach_args *aa = (void *)aux;
 	if (aa->origaddr != ADBADDR_APM ||
 	    aa->handler_id != ADBADDR_APM ||
 	    aa->adbaddr != ADBADDR_APM)
 		return 0;
 	if (adbHardware != ADB_HW_PMU)
 		return 0;
 	return 1;
+}
 void
 apmattach(device_t parent, device_t self, void *aux)
+{
 	struct apm_softc *sc = device_private(self);
 	struct pmu_battery_info info;
 	pm_battery_info(0, &info);
 	printf(": battery flags 0x%X, ", info.flags);
 	printf("%d%% charged\n", ((info.cur_charge * 100) / info.max_charge));
 	sc->sc_flags = 0;
 	sc->event_ptr = 0;
 	sc->event_count = 0;
 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
 	selinit(&sc->sc_rsel);
+}
 int
 apmopen(dev_t dev, int flag, int mode, struct lwp *l)
+{
 	struct apm_softc *sc;
 	int error = 0;
 	/* apm0 only */
 	sc = device_lookup_private(&apm_cd, APMUNIT(dev));
 	if (sc == NULL)
 		return ENXIO;
 	DPRINTF(("apmopen: dev %d pid %d flag %x mode %x\n",
 	    APMDEV(dev), l->l_proc->p_pid, flag, mode));
 	APM_LOCK(sc);
 	switch (APMDEV(dev)) {
 	case APMDEV_CTL:
 		if (!(flag & FWRITE)) {
 			error = EINVAL;
 			break;
+		}
 		if (sc->sc_flags & SCFLAG_OWRITE) {
 			error = EBUSY;
 			break;
+		}
 		sc->sc_flags |= SCFLAG_OWRITE;
 		break;
 	case APMDEV_NORMAL:
 		if (!(flag & FREAD) || (flag & FWRITE)) {
 			error = EINVAL;
 			break;
+		}
 		sc->sc_flags |= SCFLAG_OREAD;
 		break;
 	default:
 		error = ENXIO;
 		break;
+	}
 	APM_UNLOCK(sc);
 	return error;
+}
 int
 apmclose(dev_t dev, int flag, int mode, struct lwp *l)
+{
 	struct apm_softc *sc;
 	/* apm0 only */
 	sc = device_lookup_private(&apm_cd, APMUNIT(dev));
 	if (sc == NULL)
 		return ENXIO;
 	DPRINTF(("apmclose: pid %d flag %x mode %x\n", l->l_proc->p_pid, flag, mode));
 	APM_LOCK(sc);
 	switch (APMDEV(dev)) {
 	case APMDEV_CTL:
 		sc->sc_flags &= ~SCFLAG_OWRITE;
 		break;
 	case APMDEV_NORMAL:
 		sc->sc_flags &= ~SCFLAG_OREAD;
 		break;
+	}
 	APM_UNLOCK(sc);
 	return 0;
+}
 int
 apmioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
+{
 	struct apm_softc *sc;
 	struct pmu_battery_info batt;
 	struct apm_power_info *power;
 	int error = 0;
 	/* apm0 only */
 	sc = device_lookup_private(&apm_cd, APMUNIT(dev));
 	if (sc == NULL)
 		return ENXIO;
 	APM_LOCK(sc);
 	switch (cmd) {
 		/* some ioctl names from linux */
 	case APM_IOC_STANDBY:
 		if ((flag & FWRITE) == 0)
 			error = EBADF;
 	case APM_IOC_SUSPEND:
 		if ((flag & FWRITE) == 0)
 			error = EBADF;
 		break;
 	case APM_IOC_PRN_CTL:
 		if ((flag & FWRITE) == 0)
 			error = EBADF;
 		else {
 			int op = *(int *)data;
 			DPRINTF(( "APM_IOC_PRN_CTL: %d\n", op ));
 			switch (op) {
 			case APM_PRINT_ON:	/* enable printing */
 				sc->sc_flags &= ~SCFLAG_PRINT;
 				break;
 			case APM_PRINT_OFF: /* disable printing */
 				sc->sc_flags &= ~SCFLAG_PRINT;
 				sc->sc_flags |= SCFLAG_NOPRINT;
 				break;
 			case APM_PRINT_PCT: /* disable some printing */
 				sc->sc_flags &= ~SCFLAG_PRINT;
 				sc->sc_flags |= SCFLAG_PCTPRINT;
 				break;
 			default:
 				error = EINVAL;
 				break;
+			}
+		}
 		break;
 	case APM_IOC_DEV_CTL:
 		if ((flag & FWRITE) == 0)
 			error = EBADF;
 		break;
 	case APM_IOC_GETPOWER:
 	        power = (struct apm_power_info *)data;
 		pm_battery_info(0, &batt);
 		power->ac_state = ((batt.flags & PMU_PWR_AC_PRESENT) ?
 		    APM_AC_ON : APM_AC_OFF);
 		power->battery_life =
 		    ((batt.cur_charge * 100) / batt.max_charge);
 		/*
 		 * If the battery is charging, return the minutes left until
 		 * charging is complete. apmd knows this.
 		 */
 		if (!(batt.flags & PMU_PWR_BATT_PRESENT)) {
 			power->battery_state = APM_BATT_UNKNOWN;
 			power->minutes_left = 0;
 			power->battery_life = 0;
 		} else if ((power->ac_state == APM_AC_ON) &&
 			   (batt.draw > 0)) {
 			power->minutes_left = batt.secs_remaining / 60;
 			power->battery_state = APM_BATT_CHARGING;
 		} else {
 			power->minutes_left = batt.secs_remaining / 60;
 			/* XXX - Arbitrary */
 			if (power->battery_life > 60) {
 				power->battery_state = APM_BATT_HIGH;
 			} else if (power->battery_life < 10) {
 				power->battery_state = APM_BATT_CRITICAL;
 			} else {
 				power->battery_state = APM_BATT_LOW;
+			}
+		}
 		break;
 	default:
 		error = ENOTTY;
+	}
 	APM_UNLOCK(sc);
 	return error;
+}
 #ifdef __NetBSD__
 #if 0
 /*
  * return 0 if the user will notice and handle the event,
  * return 1 if the kernel driver should do so.
  */
 static int
 apm_record_event(struct apm_softc *sc, u_int event_type)
+{
 	struct apm_event_info *evp;
 	if ((sc->sc_flags & SCFLAG_OPEN) == 0)
 		return 1;		/* no user waiting */
 	if (sc->event_count == APM_NEVENTS) {
 		DPRINTF(("apm_record_event: queue full!\n"));
 		return 1;			/* overflow */
+	}
 	evp = &sc->event_list[sc->event_ptr];
 	sc->event_count++;
 	sc->event_ptr++;
 	sc->event_ptr %= APM_NEVENTS;
 	evp->type = event_type;
 	evp->index = ++apm_evindex;
 	selnotify(&sc->sc_rsel, 0, 0);
 	return (sc->sc_flags & SCFLAG_OWRITE) ? 0 : 1; /* user may handle */
+}
 #endif
 int
 apmpoll(dev_t dev, int events, struct lwp *l)
+{
 	struct apm_softc *sc = device_lookup_private(&apm_cd,APMUNIT(dev));
 	int revents = 0;
 	APM_LOCK(sc);
 	if (events & (POLLIN | POLLRDNORM)) {
 		if (sc->event_count)
 			revents |= events & (POLLIN | POLLRDNORM);
 		else
 			selrecord(l, &sc->sc_rsel);
+	}
 	APM_UNLOCK(sc);
 	return (revents);
+}
 #endif
 static void
 filt_apmrdetach(struct knote *kn)
+{
 	struct apm_softc *sc = (struct apm_softc *)kn->kn_hook;
 	APM_LOCK(sc);
 	SLIST_REMOVE(&sc->sc_rsel.sel_klist, kn, knote, kn_selnext);
 	APM_UNLOCK(sc);
+}
 static int
 filt_apmread(struct knote *kn, long hint)
+{
 	struct apm_softc *sc = kn->kn_hook;
 	kn->kn_data = sc->event_count;
 	return (kn->kn_data > 0);
+}
-static struct filterops apmread_filtops =
+static struct filterops apmread_filtops = {
-	{ 1, NULL, filt_apmrdetach, filt_apmread};
+	.f_isfd = 1,
 	.f_attach = NULL,
 	.f_detach = filt_apmrdetach,
 	.f_event = filt_apmread,
 };
 int
 apmkqfilter(dev_t dev, struct knote *kn)
+{
 	struct apm_softc *sc = device_lookup_private(&apm_cd,APMUNIT(dev));
 	struct klist *klist;
 	switch (kn->kn_filter) {
 	case EVFILT_READ:
 		klist = &sc->sc_rsel.sel_klist;
 		kn->kn_fop = &apmread_filtops;
 		break;
 	default:
 		return (1);
+	}
 	kn->kn_hook = sc;
 	APM_LOCK(sc);
 	SLIST_INSERT_HEAD(klist, kn, kn_selnext);
 	APM_UNLOCK(sc);
 	return (0);
+}

 @@ -1,1500 +1,1500 @@
-/*	$NetBSD: ralink_gpio.c,v 1.8 2020/03/10 11:07:39 martin Exp $	*/
+/*	$NetBSD: ralink_gpio.c,v 1.9 2020/10/30 22:20:38 christos Exp $	*/
 /*-
  * Copyright (c) 2011 CradlePoint Technology, Inc.
  * All rights reserved.
+ *
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /* ra_gpio.c -- Ralink 3052 gpio driver */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ralink_gpio.c,v 1.8 2020/03/10 11:07:39 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ralink_gpio.c,v 1.9 2020/10/30 22:20:38 christos Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/callout.h>
 #include <sys/device.h>
 #include <sys/event.h>
 #include <sys/intr.h>
 #include <sys/kernel.h>
 #include <sys/systm.h>
 #include <dev/cons.h>
 #include <mips/cpuregs.h>
 #include <sys/gpio.h>
 #include <dev/gpio/gpiovar.h>
 #include <mips/ralink/ralink_reg.h>
 #include <mips/ralink/ralink_var.h>
 #if !defined(MT7628)
 #define SLICKROCK
 #endif
 #include <mips/ralink/ralink_gpio.h>
 #if 0
 #define ENABLE_RALINK_DEBUG_ERROR 1
 #define ENABLE_RALINK_DEBUG_MISC  1
 #define ENABLE_RALINK_DEBUG_INFO  1
 #define ENABLE_RALINK_DEBUG_FORCE 1
 #define ENABLE_RALINK_DEBUG_FUNC 1
 #endif
 #include <mips/ralink/ralink_debug.h>
 /*
  * From the RT3052 datasheet, the GPIO pins are
  * shared with a number of other functions.  Not
  * all will be available for GPIO.  To make sure
  * pins are in GPIO mode, the GPIOMODE purpose
  * select register must be set (reset defaults all pins
  * as GPIO except for JTAG)
+ *
  * Note, GPIO0 is not shared, it is the single dedicated
  * GPIO pin.
+ *
  * 52 pins:
+ *
  *	40 - 51 RGMII  (GE0_* pins)
  *	24 - 39 SDRAM  (MD31:MD16 pins)
  *	22 - 23 MDIO   (MDC/MDIO pins)
  *	17 - 21 JTAG   (JTAG_* pins)
  *	15 - 16 UART Light  (RXD2/TXD2 pins)
  *	7  - 14 UART Full   (8 pins)
  *	(7 - 14)  UARTF_7 (3'b111 in Share mode reg)
  *	(11 - 14) UARTF_5 (3'b110 in Share mode reg, same with 6)
  *	(7 - 9)   UARTF_4 (3'b100 in Share mode reg)
  *	3  -  6 SPI    (SPI_* pins)
  *	1  -  2 I2C    (I2C_SCLK/I2C_SD pins)
  */
 #ifdef MT7628
 #define GPIO_PINS 96
 #define SPECIAL_COMMANDS	0
 #else
 #if defined(SLICKROCK)
 #define GPIO_PINS 96
 #else
 #define GPIO_PINS 52
 #endif
 /*
  * Special commands are pseudo pin numbers used to pass data to bootloader,
  */
 #define BOOT_COUNT		GPIO_PINS
 #define UPGRADE			(BOOT_COUNT + 1)
 #define SPECIAL_COMMANDS	(UPGRADE + 1 - GPIO_PINS)
 #endif
 /*
  * The pin_share array maps to the highest pin used for each of the 10
  * GPIO mode bit settings.
  */
 #if defined(MT7628)
 const static struct {
 	int pin_start;
 	int pin_end;
 	uint32_t sysreg;
 	uint32_t regmask;
 	uint32_t mode;
 } gpio_mux_map[] = {
 	{ 0,	3,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_I2S,		1 },
 	{ 4,	5,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_I2C,		1 },
 	{ 6,	6,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_SPI_CS1,	1 },
 	{ 7,	10,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_SPI,		1 },
 	{ 11,	11,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_GPIO,		1 },
 	{ 12,	13,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_UART0,	1 },
 	{ 14,	17,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_SPIS,		1 },
 	{ 18,	18,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_PWM0,		1 },
 	{ 19,	19,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_PWM1,		1 },
 	{ 20,	21,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_UART2,	1 },
 	{ 22,	29,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_SD,		1 },
 	{ 30,	30,	RA_SYSCTL_GPIO2MODE,	GPIO2MODE_P4_LED_KN,	1 },
 	{ 31,	31,	RA_SYSCTL_GPIO2MODE,	GPIO2MODE_P3_LED_KN,	1 },
 	{ 32,	32,	RA_SYSCTL_GPIO2MODE,	GPIO2MODE_P2_LED_KN,	1 },
 	{ 33,	33,	RA_SYSCTL_GPIO2MODE,	GPIO2MODE_P1_LED_KN,	1 },
 	{ 34,	34,	RA_SYSCTL_GPIO2MODE,	GPIO2MODE_P0_LED_KN,	1 },
 	{ 35,	35,	RA_SYSCTL_GPIO2MODE,	GPIO2MODE_WLED_KN,	1 },
 	{ 36,	36,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_PERST,	1 },
 	{ 37,	37,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_REFCLK,	1 },
 	{ 38,	38,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_WDT,		1 },
 	{ 39,	39,	RA_SYSCTL_GPIO2MODE,	GPIO2MODE_P4_LED_AN,	1 },
 	{ 40,	40,	RA_SYSCTL_GPIO2MODE,	GPIO2MODE_P3_LED_AN,	1 },
 	{ 41,	41,	RA_SYSCTL_GPIO2MODE,	GPIO2MODE_P2_LED_AN,	1 },
 	{ 42,	42,	RA_SYSCTL_GPIO2MODE,	GPIO2MODE_P1_LED_AN,	1 },
 	{ 43,	43,	RA_SYSCTL_GPIO2MODE,	GPIO2MODE_P0_LED_AN,	1 },
 	{ 44,	44,	RA_SYSCTL_GPIO2MODE,	GPIO2MODE_WLED_AN,	1 },
 	{ 45,	45,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_UART1,	1 },
 	{ 46,	46,	RA_SYSCTL_GPIO1MODE,	GPIO1MODE_UART1,	1 },
 };
 #else
 #if defined(SLICKROCK)
 #define SR_GPIO_MODE 0xc1c1f
 #else
 const static u_int8_t pin_share[] = {
 , 6, 9, 14, 14, 16, 21, 23, 39, 51
 };
 #endif
 #endif /* MT7628 */
 #define DEBOUNCE_TIME 150  /* Milliseconds */
 #if defined(TABLEROCK)  || defined(SPOT2) || defined(PUCK) || defined(MOAB)
 static const u_int32_t debounce_pin[DEBOUNCED_PINS] = {
 	WPS_BUTTON,
 	POWER_OFF_BUTTON,
 	DOCK_SENSE,
 	IN_5V,
 	LAN_WAN_SW
 };
 static struct timeval debounce_time[DEBOUNCED_PINS];
 /* LED defines for display during boot */
 static const char led_array1[] = {
 	LED_BATT_7,
 	LED_BATT_8,
 	LED_BATT_9,
 	LED_BATT_10,
 	LED_SS_11,
 	LED_SS_12,
 	LED_SS_13,
 	LED_SS_14
 };
 #define SET_SS_LED_REG RA_PIO_24_39_SET_BIT
 #define CLEAR_SS_LED_REG RA_PIO_24_39_CLR_BIT
 #define SS_OFFSET 24
 #define BOOT_LED_TIMING 3000
 #endif	/* TABLEROCK || SPOT2 || PUCK || MOAB */
 #if defined(PEBBLES500) || defined (PEBBLES35)
 static const u_int32_t debounce_pin[DEBOUNCED_PINS] = {
 	WPS_BUTTON,
 	SOFT_RST_IN_BUTTON,
 	CURRENT_LIMIT_FLAG1_3_3v,
 	CURRENT_LIMIT_FLAG_USB1,
 	CURRENT_LIMIT_FLAG1_1_5v,
 	EXCARD_ATTACH
 };
 static struct timeval debounce_time[DEBOUNCED_PINS];
 /* LED defines for display during boot */
 #if defined(PEBBLES500)
 static const char led_array1[] = {
 	LED_SS_13,
 	LED_SS_12,
 	LED_SS_11,
 	LED_SS_10
 };
 #else
 static const char led_array1[] = {};
 #endif
 #define SET_SS_LED_REG RA_PIO_40_51_SET_BIT
 #define CLEAR_SS_LED_REG RA_PIO_40_51_CLR_BIT
 #define SS_OFFSET 40
 #define BOOT_LED_TIMING 5500
 #endif	/* PEBBLES500 || PEBBLES35 */
 #if defined(SLICKROCK)
 static const u_int32_t debounce_pin[DEBOUNCED_PINS] = {
 	WPS_BUTTON,
 	SOFT_RST_IN_BUTTON,
 	SS_BUTTON,
 	CURRENT_LIMIT_FLAG_USB1,
 	CURRENT_LIMIT_FLAG_USB2,
 	CURRENT_LIMIT_FLAG_USB3,
 	CURRENT_LIMIT_FLAG_EX1,
 	CURRENT_LIMIT_FLAG_EX2,
 	WIFI_ENABLE
 };
 static struct timeval debounce_time[DEBOUNCED_PINS];
 /* LED defines for display during boot */
 static const char led_array1[] = {
 	LED_SS_13,
 	LED_SS_12,
 	LED_SS_11,
 	LED_SS_10
 };
 #define SET_SS_LED_REG RA_PIO_40_51_SET_BIT
 #define CLEAR_SS_LED_REG RA_PIO_40_51_CLR_BIT
 #define SS_OFFSET 40
 #define BOOT_LED_TIMING 3250
 #endif	/* SLICKROCK */
 #ifndef DEBOUNCED_PINS
 static const u_int32_t debounce_pin[] = {};
 static struct timeval debounce_time[] = {};
 #endif
 #ifndef BOOT_LED_TIMING
 static const char led_array1[] = {};
 #endif
 #define RA_GPIO_PIN_INIT(sc, var, pin, ptp, regname)			\
 	do {								\
 		const u_int _reg_bit = 1 << (pin - ptp->pin_reg_base);	\
 		const u_int _mask_bit = 1 << (pin - ptp->pin_mask_base);\
 		var = gp_read(sc, ptp->regname.reg);			\
 		if ((ptp->regname.mask & _mask_bit) != 0) {		\
 			var |= _reg_bit;				\
 		} else {						\
 			var &= ~_reg_bit;				\
 		}							\
 		gp_write(sc, ptp->regname.reg, var);			\
 	} while (0)
 #define RA_GPIO_PIN_INIT_DIR(sc, var, pin, ptp)				\
 	do {								\
 		const u_int _reg_bit = 1 << (pin - ptp->pin_reg_base);	\
 		const u_int _mask_bit = 1 << (pin - ptp->pin_mask_base);\
 		var = gp_read(sc, ptp->pin_dir.reg);			\
 		if ((ptp->pin_dir.mask & _mask_bit) != 0) {		\
 			var |= _reg_bit;				\
 			sc->sc_pins[pin].pin_flags = GPIO_PIN_OUTPUT;	\
 		} else {						\
 			var &= ~_reg_bit;				\
 			sc->sc_pins[pin].pin_flags = GPIO_PIN_INPUT;	\
 		}							\
 		gp_write(sc, ptp->pin_dir.reg, var);			\
 	} while (0)
 typedef struct ra_gpio_softc {
 	device_t sc_dev;
 	struct gpio_chipset_tag	sc_gc;
 	gpio_pin_t sc_pins[GPIO_PINS + SPECIAL_COMMANDS];
 	bus_space_tag_t	sc_memt;	/* bus space tag */
 	bus_space_handle_t sc_sy_memh;	/* Sysctl bus space handle */
 	int sc_sy_size;			/* size of Sysctl register space */
 	bus_space_handle_t sc_gp_memh;	/* PIO bus space handle */
 	int sc_gp_size;			/* size of PIO register space */
 	void *sc_ih;			/* interrupt handle */
 	void *sc_si;			/* softintr handle  */
 	struct callout sc_tick_callout;	/* For debouncing inputs */
 	/*
 	 * These track gpio pins that have interrupted
 	 */
 #if defined(MT7628)
 	uint32_t sc_intr_status00_31;
 	uint32_t sc_intr_status32_63;
 	uint32_t sc_intr_status64_95;
 #else
 	uint32_t sc_intr_status00_23;
 	uint32_t sc_intr_status24_39;
 	uint32_t sc_intr_status40_51;
 	uint32_t sc_intr_status72_95;
 #endif
 } ra_gpio_softc_t;
 static int ra_gpio_match(device_t, cfdata_t , void *);
 static void ra_gpio_attach(device_t, device_t, void *);
 #ifdef NOTYET
 static int ra_gpio_open(void *, device_t);
 static int ra_gpio_close(void *, device_t);
 #endif
 static void ra_gpio_pin_init(ra_gpio_softc_t *, int);
 static void ra_gpio_pin_ctl(void *, int, int);
 static int  ra_gpio_intr(void *);
 static void ra_gpio_softintr(void *);
 static void ra_gpio_debounce_process(void *);
 static void ra_gpio_debounce_setup(ra_gpio_softc_t *);
 static void disable_gpio_interrupt(ra_gpio_softc_t *, int);
 static void enable_gpio_interrupt(ra_gpio_softc_t *, int);
 static void gpio_reset_registers(ra_gpio_softc_t *);
 #if 0
 static void gpio_register_dump(ra_gpio_softc_t *);
 #endif
 typedef struct pin_reg {
 	u_int mask;
 	u_int reg;
 } pin_reg_t;
 typedef struct pin_tab {
 	int pin_reg_base;
 	int pin_reg_limit;
 	int pin_mask_base;
 	u_int pin_enabled;
 	u_int pin_input;
 	u_int pin_output_clr;
 	u_int pin_output_set;
 	pin_reg_t pin_dir;
 	pin_reg_t pin_rise;
 	pin_reg_t pin_fall;
 	pin_reg_t pin_pol;
 } pin_tab_t;
 /*
  * use pin_tab[] in conjunction with pin_tab_index[]
  * to look up register offsets, masks, etc. for a given GPIO pin,
  * instead of lots of if/then/else test & branching
  */
 static const pin_tab_t pin_tab[] = {
 #if defined(MT7628)
+    {
 , 31, 0, 0xffffffff,
 	RA_PIO_00_31_DATA,
 	RA_PIO_00_31_CLR_BIT,
 	RA_PIO_00_31_SET_BIT,
 	{ 0xffffffff,		RA_PIO_00_31_DIR		},
 	{ 0xffffffff,		RA_PIO_00_31_INT_RISE_EN	},
 	{ 0xffffffff,		RA_PIO_00_31_INT_FALL_EN	},
 	{ 0xffffffff,		RA_PIO_00_31_POLARITY		}
     },
+    {
 , 63, 32, 0xffffffff,
 	RA_PIO_32_63_DATA,
 	RA_PIO_32_63_CLR_BIT,
 	RA_PIO_32_63_SET_BIT,
 	{ 0xffffffff,		RA_PIO_32_63_DIR		},
 	{ 0xffffffff,		RA_PIO_32_63_INT_RISE_EN	},
 	{ 0xffffffff,		RA_PIO_32_63_INT_FALL_EN	},
 	{ 0xffffffff,		RA_PIO_32_63_POLARITY		}
     },
+    {
 , 95, 64, 0xffffffff,
 	RA_PIO_64_95_DATA,
 	RA_PIO_64_95_CLR_BIT,
 	RA_PIO_64_95_SET_BIT,
 	{ 0xffffffff,		RA_PIO_64_95_DIR		},
 	{ 0xffffffff,		RA_PIO_64_95_INT_RISE_EN	},
 	{ 0xffffffff,		RA_PIO_64_95_INT_FALL_EN	},
 	{ 0xffffffff,		RA_PIO_64_95_POLARITY		}
+    }
 #else
+    {
 , 24, 0, GPIO_PIN_MASK,
 	RA_PIO_00_23_DATA,
 	RA_PIO_00_23_CLR_BIT,
 	RA_PIO_00_23_SET_BIT,
 	{ GPIO_OUTPUT_PIN_MASK,          RA_PIO_00_23_DIR,         },
 	{ GPIO_INT_PIN_MASK,             RA_PIO_00_23_INT_RISE_EN, },
 	{ GPIO_INT_FEDGE_PIN_MASK,       RA_PIO_00_23_INT_RISE_EN, },
 	{ GPIO_POL_MASK,                 RA_PIO_00_23_POLARITY,    },
     },
+    {
 , 40, 24, GPIO_PIN_MASK_24_51,
 	RA_PIO_24_39_DATA,
 	RA_PIO_24_39_CLR_BIT,
 	RA_PIO_24_39_SET_BIT,
 	{ GPIO_OUTPUT_PIN_MASK_24_51,    RA_PIO_24_39_DIR,         },
 	{ GPIO_INT_PIN_MASK_24_51,       RA_PIO_24_39_INT_RISE_EN, },
 	{ GPIO_INT_FEDGE_PIN_MASK_24_51, RA_PIO_24_39_INT_FALL_EN, },
 	{ GPIO_POL_MASK_24_51,           RA_PIO_24_39_POLARITY,    },
     },
+    {
 , 52, 24, GPIO_PIN_MASK_24_51,
 	RA_PIO_40_51_DATA,
 	RA_PIO_40_51_CLR_BIT,
 	RA_PIO_40_51_SET_BIT,
 	{ GPIO_OUTPUT_PIN_MASK_24_51,    RA_PIO_40_51_DIR,         },
 	{ GPIO_INT_PIN_MASK_24_51,       RA_PIO_40_51_INT_RISE_EN, },
 	{ GPIO_INT_FEDGE_PIN_MASK_24_51, RA_PIO_40_51_INT_FALL_EN, },
 	{ GPIO_POL_MASK_24_51,           RA_PIO_40_51_POLARITY,    },
     },
 #if defined(SLICKROCK)
+    {
 , 96, 72, GPIO_PIN_MASK_72_95,
 	RA_PIO_72_95_DATA,
 	RA_PIO_72_95_CLR_BIT,
 	RA_PIO_72_95_SET_BIT,
 	{ GPIO_OUTPUT_PIN_MASK_72_95,    RA_PIO_72_95_DIR,         },
 	{ GPIO_INT_PIN_MASK_72_95,       RA_PIO_72_95_INT_RISE_EN, },
 	{ GPIO_INT_FEDGE_PIN_MASK_72_95, RA_PIO_72_95_INT_FALL_EN, },
 	{ GPIO_POL_MASK_72_95,           RA_PIO_72_95_POLARITY,    },
     },
 #endif
 #endif
 };
 /*
  * use pin_tab_index[] to determine index in pin_tab[]
  * for a given pin.  -1 means there is no pin there.
  */
 static const int pin_tab_index[GPIO_PINS] = {
 #if defined(MT7628)
 /*		 0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 */
 /*  0 */	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 /* 16 */	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 /* 32 */	 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 /* 48 */	 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 /* 64 */	 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
 /* 80 */	 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2
 #else /* !MT7628 */
 /*		 0   1   2   3   4   5   6   7   8   9	*/
 /*  0 */	 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
 /* 10 */	 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
 /* 20 */	 0,  0,  0,  0,  1,  1,  1,  1,  1,  1,
 /* 30 */	 1,  1,  1,  1,  1,  1,  1,  1,  1,  1,
 /* 40 */	 2,  2,  2,  2,  2,  2,  2,  2,  2,  2,
 /* 50 */	 2,  2,
 #if defined(SLICKROCK)
 /* 50 */	        -1, -1, -1, -1, -1, -1, -1, -1,
 /* 60 */	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 /* 70 */	-1, -1,
 /* 72 */	         3,  3,  3,  3,  3,  3,  3,  3,
 /* 80 */	 3,  3,  3,  3,  3,  3,  3,  3,  3,  3,
 /* 90 */	 3,  3,  3,  3,  3,  3
 #endif
 #endif /* !MT7628 */
 };
 CFATTACH_DECL_NEW(rgpio, sizeof(struct ra_gpio_softc), ra_gpio_match,
 	ra_gpio_attach, NULL, NULL);
 /*
  * Event handler calls and structures
  */
 static int  gpio_event_app_user_attach(struct knote *);
 static void gpio_event_app_user_detach(struct knote *);
 static int  gpio_event_app_user_event(struct knote *, long);
 static struct klist knotes;
 static int app_filter_id;
 static struct filterops app_fops = {
-,
+	.f_isfd = 0,
-	gpio_event_app_user_attach,
+	.f_attach = gpio_event_app_user_attach,
-	gpio_event_app_user_detach,
+	.f_detach = gpio_event_app_user_detach,
-	gpio_event_app_user_event
+	.f_event = gpio_event_app_user_event,
 };
 static struct callout led_tick_callout;
 static int gpio_driver_blink_leds = 1;
 static inline uint32_t
 sy_read(ra_gpio_softc_t *sc, bus_size_t off)
+{
 	KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n",
 	    __func__, off);
 	return bus_space_read_4(sc->sc_memt, sc->sc_sy_memh, off);
+}
 static inline void
 sy_write(ra_gpio_softc_t *sc, bus_size_t off, uint32_t val)
+{
 	KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n",
 	    __func__, off);
 	bus_space_write_4(sc->sc_memt, sc->sc_sy_memh, off, val);
+}
 static inline uint32_t
 gp_read(ra_gpio_softc_t *sc, bus_size_t off)
+{
 	KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n",
 	    __func__, off);
 	return bus_space_read_4(sc->sc_memt, sc->sc_gp_memh, off);
+}
 static inline void
 gp_write(ra_gpio_softc_t *sc, bus_size_t off, uint32_t val)
+{
 	KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n",
 	    __func__, off);
 	bus_space_write_4(sc->sc_memt, sc->sc_gp_memh, off, val);
+}
 /*
  * Basic debug function, dump all PIO registers
  */
 #if 0
 static void
 gpio_register_dump(ra_gpio_softc_t *sc)
+{
 	for (int i=0; i < 0xb0; i+=4)
 		RALINK_DEBUG(RALINK_DEBUG_INFO, "Reg: 0x%x, Value: 0x%x\n",
 			(RA_PIO_BASE + i), gp_read(sc, i));
+}
 #endif
 static void
 gpio_reset_registers(ra_gpio_softc_t *sc)
+{
 #if 0
 	for (int i=0; i < 0x88; i+=4)
 		gp_write(sc, i, 0);
 #endif
+}
 static int
 ra_gpio_match(device_t parent, cfdata_t cf, void *aux)
+{
 	RALINK_DEBUG_FUNC_ENTRY();
 	return 1;
+}
 static void
 ra_gpio_attach(device_t parent, device_t self, void *aux)
+{
 	struct gpiobus_attach_args gba;
 	ra_gpio_softc_t * const sc = device_private(self);
 	const struct mainbus_attach_args *ma = aux;
 	int error;
 	aprint_naive(": Ralink GPIO controller\n");
 	aprint_normal(": Ralink GPIO controller\n");
 	sc->sc_dev = self;
 	sc->sc_memt = ma->ma_memt;
 	sc->sc_sy_size = 0x10000;
 	sc->sc_gp_size = 0x1000;
 	/*
 	 * map the registers
+	 *
 	 * we map the Sysctl, and PIO registers separately so we can use the
 	 * defined register offsets sanely; just use the correct corresponding
 	 * bus_space_handle
 	 */
 	if ((error = bus_space_map(sc->sc_memt, RA_SYSCTL_BASE,
 	    sc->sc_sy_size, 0, &sc->sc_sy_memh)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 			"unable to map Sysctl registers, error=%d\n", error);
 		goto fail_0;
+	}
 	if ((error = bus_space_map(sc->sc_memt, RA_PIO_BASE,
 	    sc->sc_gp_size, 0, &sc->sc_gp_memh)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 			"unable to map PIO registers, error=%d\n", error);
 		goto fail_1;
+	}
 	/* Reset some registers */
 #if defined(MT7628)
 	gp_write(sc, RA_PIO_00_31_INT_RISE_EN, 0xffffffff);
 	gp_write(sc, RA_PIO_00_31_INT_FALL_EN, 0xffffffff);
 	gp_write(sc, RA_PIO_00_31_INT_HIGH_EN, 0);
 	gp_write(sc, RA_PIO_00_31_INT_LOW_EN, 0);
 	gp_write(sc, RA_PIO_32_63_INT_RISE_EN, 0xffffffff);
 	gp_write(sc, RA_PIO_32_63_INT_FALL_EN, 0xffffffff);
 	gp_write(sc, RA_PIO_32_63_INT_HIGH_EN, 0);
 	gp_write(sc, RA_PIO_32_63_INT_LOW_EN, 0);
 	gp_write(sc, RA_PIO_64_95_INT_RISE_EN, 0xffffffff);
 	gp_write(sc, RA_PIO_64_95_INT_FALL_EN, 0xffffffff);
 	gp_write(sc, RA_PIO_64_95_INT_HIGH_EN, 0);
 	gp_write(sc, RA_PIO_64_95_INT_LOW_EN, 0);
 	gp_write(sc, RA_PIO_00_31_POLARITY, 0);
 	gp_write(sc, RA_PIO_32_63_POLARITY, 0);
 	gp_write(sc, RA_PIO_64_95_POLARITY, 0);
 #else
 	gp_write(sc, RA_PIO_00_23_INT, 0xffffff);
 	gp_write(sc, RA_PIO_00_23_EDGE_INT, 0xffffff);
 	gp_write(sc, RA_PIO_24_39_INT, 0xffff);
 	gp_write(sc, RA_PIO_24_39_EDGE_INT, 0xffff);
 	gp_write(sc, RA_PIO_40_51_INT, 0xfff);
 	gp_write(sc, RA_PIO_40_51_EDGE_INT, 0xfff);
 	gp_write(sc, RA_PIO_00_23_POLARITY, 0);
 #if defined(SLICKROCK)
 	gp_write(sc, RA_PIO_72_95_INT, 0xffffff);
 	gp_write(sc, RA_PIO_72_95_EDGE_INT, 0xffffff);
 #endif
 #endif
 	/* Set up for interrupt handling, low priority interrupt queue */
 	sc->sc_ih = ra_intr_establish(RA_IRQ_PIO,
 		ra_gpio_intr, sc, 0);
 	if (sc->sc_ih == NULL) {
 		RALINK_DEBUG(RALINK_DEBUG_ERROR,
 			"%s: unable to establish interrupt\n",
 			device_xname(sc->sc_dev));
 		goto fail_2;
+	}
 	/* Soft int setup */
 	sc->sc_si = softint_establish(SOFTINT_BIO, ra_gpio_softintr, sc);
 	if (sc->sc_si == NULL) {
 		ra_intr_disestablish(sc->sc_ih);
 		RALINK_DEBUG(RALINK_DEBUG_ERROR,
 			"%s: unable to establish soft interrupt\n",
 			device_xname(sc->sc_dev));
 		goto fail_3;
+	}
 	SLIST_INIT(&knotes);
 	if (kfilter_register("CP_GPIO_EVENT", &app_fops, &app_filter_id) != 0) {
 		RALINK_DEBUG(RALINK_DEBUG_ERROR,
 			"%s: kfilter_register for CP_GPIO_EVENT failed\n",
 			__func__);
 		goto fail_4;
+	}
 	sc->sc_gc.gp_cookie = sc;
 	sc->sc_gc.gp_pin_read = ra_gpio_pin_read;
 	sc->sc_gc.gp_pin_write = ra_gpio_pin_write;
 	sc->sc_gc.gp_pin_ctl = ra_gpio_pin_ctl;
 #if 0
 	gpio_register_dump(sc);
 #endif
 	gpio_reset_registers(sc);
 	/* Initialize the GPIO pins */
 	for (int pin = 0; pin < GPIO_PINS; pin++)
 		ra_gpio_pin_init(sc, pin);
 #if 0
 	/* debug check */
 	KASSERT((sy_read(sc, RA_SYSCTL_GPIOMODE) == 0x31c) != 0);
 	RALINK_DEBUG(RALINK_DEBUG_INFO, "SYSCTL_GPIOMODE = 0x%x\n",
 		sy_read(sc, RA_SYSCTL_GPIOMODE));
 #endif
 	/*
 	 * Some simple board setup actions:
 	 * Check if we're attached to the dock. If so, enable dock power.
 	 *  BIG NOTE: Dock power is dependent on USB5V_EN!
 	 */
 #if defined(PEBBLES500) || defined (PEBBLES35)
 	RALINK_DEBUG(RALINK_DEBUG_INFO, "Enabling USB power\n");
 	ra_gpio_pin_write(sc, VBUS_EN, 1);
 	ra_gpio_pin_write(sc, POWER_EN_USB, 1);
 #if defined(PEBBLES500)
 	/*
 	 * Is an express card attached? Enable power if it is
 	 *  or it isn't
 	 */
 #if 0
 	if (ra_gpio_pin_read(sc, EXCARD_ATTACH) == 0) {
 #endif
 		ra_gpio_pin_write(sc, POWER_EN_EXCARD1_3_3v, 1);
 		ra_gpio_pin_write(sc, POWER_EN_EXCARD1_1_5v, 1);
 #if 0
+	}
 #endif	/* 0 */
 #endif	/* PEBBLES500 */
 #endif	/* PEBBLES500 || PEBBLES35 */
 #if defined(TABLEROCK) || defined(SPOT2) || defined(PUCK) || defined(MOAB)
 	/* CHARGER_OFF pin matches the IN_5V */
 	if (ra_gpio_pin_read(sc, IN_5V) == 0) {
 		ra_gpio_pin_write(sc, CHARGER_OFF, 0);
 	} else {
 		ra_gpio_pin_write(sc, CHARGER_OFF, 1);
+	}
 #endif
 #if defined(SLICKROCK)
 	/* Enable all modem slots */
 	ra_gpio_pin_write(sc, POWER_EN_USB1, 1);
 	ra_gpio_pin_write(sc, POWER_EN_USB2, 1);
 	ra_gpio_pin_write(sc, POWER_EN_USB3, 1);
 	ra_gpio_pin_write(sc, POWER_EN_EX1, 1);
 	ra_gpio_pin_write(sc, EX1_CPUSB_RST, 0);
 	ra_gpio_pin_write(sc, POWER_EN_EX2, 1);
 	ra_gpio_pin_write(sc, EX2_CPUSB_RST, 0);
 	/* Wake up with an overcurrent on EX1. Try to shut it down. */
 	gp_write(sc, RA_PIO_72_95_INT, 0xffffff);
 	gp_write(sc, RA_PIO_72_95_EDGE_INT, 0xffffff);
 #endif
 #ifdef BOOT_COUNT
 	sc->sc_pins[BOOT_COUNT].pin_flags = GPIO_PIN_OUTPUT;
 	sc->sc_pins[BOOT_COUNT].pin_mapped = 0;
 #endif
 #ifdef UPGRADE
 	sc->sc_pins[UPGRADE].pin_flags = GPIO_PIN_OUTPUT;
 	sc->sc_pins[UPGRADE].pin_mapped = 0;
 #endif
 	gba.gba_gc = &sc->sc_gc;
 	gba.gba_pins = sc->sc_pins;
 	/* Note, > 52nd pin isn't a gpio, it is a special command */
 	gba.gba_npins = (GPIO_PINS + SPECIAL_COMMANDS);
 	config_found_ia(sc->sc_dev, "gpiobus", &gba, gpiobus_print);
 #if 0
 	gpio_register_dump(sc);
 #endif
 	/* init our gpio debounce */
 	callout_init(&sc->sc_tick_callout, 0);
 	callout_setfunc(&sc->sc_tick_callout, ra_gpio_debounce_process, sc);
 	/* LED blinking during boot */
 	callout_init(&led_tick_callout, 0);
 	ra_gpio_toggle_LED(sc);
 	return;
  fail_4:
 	softint_disestablish(sc->sc_si);
  fail_3:
 	ra_intr_disestablish(sc->sc_ih);
  fail_2:
 	bus_space_unmap(sc->sc_memt, sc->sc_gp_memh, sc->sc_sy_size);
  fail_1:
 	bus_space_unmap(sc->sc_memt, sc->sc_sy_memh, sc->sc_sy_size);
  fail_0:
 	return;
+}
 /*
  * ra_gpio_pin_init - initialize the given gpio pin
  */
 static void
 ra_gpio_pin_init(ra_gpio_softc_t *sc, int pin)
+{
 	uint32_t r;
 	sc->sc_pins[pin].pin_caps = 0;
 	sc->sc_pins[pin].pin_flags = 0;
 	sc->sc_pins[pin].pin_state = 0;
 	sc->sc_pins[pin].pin_mapped = 0;
 	/* ensure pin number is in range */
 	KASSERT(pin < GPIO_PINS);
 	if (pin >= GPIO_PINS)
 		return;
 	/* if pin number is in a gap in the range, just return */
 	const int index = pin_tab_index[pin];
 	if (index == -1)
 		return;
 	/* if pin is not enabled, just return */
 	const pin_tab_t * const ptp = &pin_tab[index];
 	const u_int mask_bit = 1 << (pin - ptp->pin_mask_base);
 	if ((ptp->pin_enabled & mask_bit) == 0)
 		return;
 	sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
 	    GPIO_PIN_INVIN | GPIO_PIN_INVOUT;
 	sc->sc_pins[pin].pin_state = GPIO_PIN_INPUT;
 #if defined(MT7628)
 	/*
 	 * Set the SYSCTL_GPIO{1,2}MODE register
 	 * for the PIO block of any mapped GPIO
 	 */
 	for (int i = 0; i < __arraycount(gpio_mux_map); i++) {
 		if ((pin >= gpio_mux_map[i].pin_start) &&
 		    (pin >= gpio_mux_map[i].pin_end)) {
 			r = sy_read(sc, gpio_mux_map[i].sysreg);
 			r &= ~gpio_mux_map[i].regmask;
 			r |= __SHIFTIN(gpio_mux_map[i].mode,
 			    gpio_mux_map[i].regmask);
 			sy_write(sc, gpio_mux_map[i].sysreg, r);
 			break;
+		}
+	}
 #else
 #if defined(SLICKROCK)
 	r = sy_read(sc, RA_SYSCTL_GPIOMODE);
 	r |= SR_GPIO_MODE;
 	sy_write(sc, RA_SYSCTL_GPIOMODE, r);
 #else
 	/*
 	 * Set the SYSCTL_GPIOMODE register to 1 for
 	 * the PIO block of any mapped GPIO
 	 * (most have reset defaults of 1 already).
 	 * GPIO0 doesn't have an associated MODE register.
 	 */
 	if (pin != 0) {
 		u_int gpio_mode;
 		for (gpio_mode = 0; gpio_mode < __arraycount(pin_share);
 		    gpio_mode++) {
 			if (pin <= pin_share[gpio_mode]) {
 				r = sy_read(sc, RA_SYSCTL_GPIOMODE);
 				if (10 == pin) {
 					/*
 					 * Special case:
 					 *   GPIO 10 requires GPIOMODE_UARTF0-2
 					 */
 					r |= GPIOMODE_UARTF_0_2;
 				} else {
 					/* standard case */
 					r |= (1 << gpio_mode);
+				}
 				sy_write(sc, RA_SYSCTL_GPIOMODE, r);
 				break;
+			}
+		}
+	}
 #endif /* SLICKROCK */
 #endif /* !MT7628 */
 	/* set direction */
 	RA_GPIO_PIN_INIT_DIR(sc, r, pin, ptp);
 	/* rising edge interrupt */
 	RA_GPIO_PIN_INIT(sc, r, pin, ptp, pin_rise);
 	/* falling edge interrupt */
 	RA_GPIO_PIN_INIT(sc, r, pin, ptp, pin_fall);
 	/* polarirty */
 	RA_GPIO_PIN_INIT(sc, r, pin, ptp, pin_pol);
+}
 /*
  * Note: This has special hacks in it. If pseudo-pin BOOT_COUNT
  * is requested, it is a signal check the memo register for a special key
  * that means run Wi-Fi in no security mode.
  */
 int
 ra_gpio_pin_read(void *arg, int pin)
+{
 	RALINK_DEBUG_FUNC_ENTRY();
 	const ra_gpio_softc_t * const sc = arg;
 	int rv;
 	KASSERT(sc != NULL);
 	if (pin < GPIO_PINS) {
 		/*
 		 * normal case: a regular GPIO pin
 		 * if pin number is in a gap in the range,
 		 * then warn and return 0
 		 */
 		const int index = pin_tab_index[pin];
 		KASSERTMSG(index != -1, "%s: non-existant pin=%d\n",
 			__func__, pin);
 		if (index == -1) {
 			rv = 0;
 		} else {
 			const pin_tab_t * const ptp = &pin_tab[index];
 			const uint32_t reg_bit = 1 << (pin - ptp->pin_reg_base);
 			const bus_size_t off = ptp->pin_input;
 			uint32_t r;
 			r = bus_space_read_4(sc->sc_memt, sc->sc_gp_memh, off);
 			rv = ((r & (1 << reg_bit)) != 0);
+		}
 	} else {
 		/*
 		 * Special hack: a pseudo-pin used for signaling
 		 */
 		rv = 0;
 		switch (pin) {
 #ifdef BOOT_COUNT
 		case BOOT_COUNT:
 			if (1 == ra_check_memo_reg(NO_SECURITY))
 				rv = 1;
 			break;
 #endif
 		default:
 #ifdef DIAGNOSTIC
 			aprint_normal_dev(sc->sc_dev, "%s: bad pin=%d\n",
 				__func__, pin);
 #endif
 			break;
+		}
+	}
 	RALINK_DEBUG_0(RALINK_DEBUG_INFO, "pin %d, value %x\n", pin, rv);
 	return rv;
+}
 /*
  * There are three ways to change the value of a pin.
  *   You can write to the DATA register, which will set
  *   or reset a pin.  But you need to store it locally and
  *   read/mask/set it, which is potentially racy without locks.
  *   There are also SET and RESET registers, which allow you to write
  *   a value to a single pin and not affect any other pins
  *   by accident.
+ *
  * NOTE:  This has special hacks in it.  If pin 52 (which does not exist)
  * is written, it is a signal to clear the boot count register.  If pin
  * 53 is written, it is a upgrade signal to the bootloader.
+ *
  */
 #define MAGIC		0x27051956
 #define UPGRADE_MAGIC	0x27051957
 void
 ra_gpio_pin_write(void *arg, int pin, int value)
+{
 	RALINK_DEBUG_FUNC_ENTRY();
 	ra_gpio_softc_t * const sc = arg;
 #if defined(BOOT_COUNT) || defined(UPGRADE)
 	uint32_t r;
 #endif
 	KASSERT(sc != NULL);
 	RALINK_DEBUG(RALINK_DEBUG_INFO, "pin %d, val %d\n", pin, value);
 	if (pin >= GPIO_PINS) {
 		/*
 		 * Special hack: a pseudo-pin used for signaling
 		 */
 		switch(pin) {
 #ifdef BOOT_COUNT
 		case BOOT_COUNT:
 			/* Reset boot count */
 			r = sy_read(sc, RA_SYSCTL_MEMO0);
 			if (r == MAGIC)
 				sy_write(sc, RA_SYSCTL_MEMO1, 0);
 			break;
 #endif
 #ifdef UPGRADE
 		case UPGRADE:
 			/* Set upgrade flag */
 			sy_write(sc, RA_SYSCTL_MEMO0, UPGRADE_MAGIC);
 			sy_write(sc, RA_SYSCTL_MEMO1, UPGRADE_MAGIC);
 			break;
 #endif
 		default:
 #ifdef DIAGNOSTIC
 			aprint_normal_dev(sc->sc_dev, "%s: bad pin=%d\n",
 				__func__, pin);
 #endif
+		}
 		return;
+	}
 	/*
 	 * normal case: a regular GPIO pin
 	 * if pin number is in a gap in the range,
 	 * then warn and return
 	 */
 	const int index = pin_tab_index[pin];
 	KASSERTMSG(index != -1, "%s: non-existant pin=%d\n", __func__, pin);
 	if (index == -1)
 		return;
 	const pin_tab_t * const ptp = &pin_tab[index];
 	const u_int mask_bit = 1 << (pin - ptp->pin_mask_base);
 	const uint32_t reg_bit = 1 << (pin - ptp->pin_reg_base);
 	const bus_size_t off = (value == 0) ?
 		ptp->pin_output_clr : ptp->pin_output_set;
 	if ((ptp->pin_dir.mask & mask_bit) == 0) {
 #ifdef DIAGNOSTIC
 		aprint_normal_dev(sc->sc_dev,
 			"%s: Writing non-output pin: %d\n", __func__, pin);
 #endif
 		return;
+	}
 	bus_space_write_4(sc->sc_memt, sc->sc_gp_memh, off, reg_bit);
+}
 static void
 ra_gpio_pin_ctl(void *arg, int pin, int flags)
+{
 	RALINK_DEBUG_FUNC_ENTRY();
 	/*
 	 * For now, this lets us know that user-space is using the GPIOs
 	 *  and the kernel shouldn't blink LEDs any more
 	 */
 	gpio_driver_blink_leds = 0;
+}
 /*
  *  Check the three interrupt registers and ack them
  *   immediately.  If a button is pushed, use the
  *   handle_key_press call to debounce it.  Otherwise,
  *   call the softint handler to send any necessary
  *   events.
  */
 static int
 ra_gpio_intr(void *arg)
+{
 	RALINK_DEBUG_FUNC_ENTRY();
 	ra_gpio_softc_t * const sc = arg;
 #if 0
 	/* Read the 3 interrupt registers */
 #if defined(MT7628)
 	if (sc->sc_intr_status00_31 || sc->sc_intr_status32_63 ||
 	    sc->sc_intr_status64_95) {
 		printf("\n0-31 %x, 32-63 %x, 64_95 %x\n",
 		    sc->sc_intr_status00_31,
 		    sc->sc_intr_status32_63,
 		    sc->sc_intr_status64_95);
+	}
 #else
 	if (sc->sc_intr_status00_23 || sc->sc_intr_status24_39 ||
 	    sc->sc_intr_status40_51) {
 		printf("\n0-23 %x, 24-39 %x, 40_51 %x\n",
 		    sc->sc_intr_status00_23,
 		    sc->sc_intr_status24_39,
 		    sc->sc_intr_status40_51);
+	}
 #endif
 #endif
 #if defined(MT7628)
 	sc->sc_intr_status00_31 |= gp_read(sc, RA_PIO_00_31_INT_STAT);
 	sc->sc_intr_status32_63 |= gp_read(sc, RA_PIO_32_63_INT_STAT);
 	sc->sc_intr_status64_95 |= gp_read(sc, RA_PIO_64_95_INT_STAT);
 #else
 	sc->sc_intr_status00_23 |= gp_read(sc, RA_PIO_00_23_INT);
 	sc->sc_intr_status24_39 |= gp_read(sc, RA_PIO_24_39_INT);
 	sc->sc_intr_status40_51 |= gp_read(sc, RA_PIO_40_51_INT);
 #if defined(SLICKROCK)
 	sc->sc_intr_status72_95 |= gp_read(sc, RA_PIO_72_95_INT);
 #endif
 #endif
 #if 0
 	/* Trivial error checking, some interrupt had to have fired */
 #if defined(MT7628)
 	KASSERT((sc->sc_intr_status00_31 | sc->sc_intr_status32_64 |
 	    sc->sc_intr_status64_95) != 0);
 #else
 	KASSERT((sc->sc_intr_status00_23 | sc->sc_intr_status24_39 |
 	    sc->sc_intr_status40_51) != 0);
 #endif
 #endif
 	/* Debounce interrupt */
 	ra_gpio_debounce_setup(sc);
 	/*
 	 * and ACK the interrupt.
 	 *  OR the values in case the softint handler hasn't
 	 *  been scheduled and handled any previous int
 	 *  I don't know if resetting the EDGE register is
 	 *  necessary, but the Ralink Linux driver does it.
 	 */
 #if defined(MT7628)
 	gp_write(sc, RA_PIO_00_31_INT_STAT, sc->sc_intr_status00_31);
 	gp_write(sc, RA_PIO_00_31_INT_STAT_EDGE, sc->sc_intr_status00_31);
 	gp_write(sc, RA_PIO_32_63_INT_STAT, sc->sc_intr_status32_63);
 	gp_write(sc, RA_PIO_32_63_INT_STAT_EDGE, sc->sc_intr_status32_63);
 	gp_write(sc, RA_PIO_64_95_INT_STAT, sc->sc_intr_status64_95);
 	gp_write(sc, RA_PIO_64_95_INT_STAT_EDGE, sc->sc_intr_status64_95);
 	/* Reset until next time */
 	sc->sc_intr_status00_31 = 0;
 	sc->sc_intr_status32_63 = 0;
 	sc->sc_intr_status64_95 = 0;
 #else
 	gp_write(sc, RA_PIO_00_23_INT, sc->sc_intr_status00_23);
 	gp_write(sc, RA_PIO_00_23_EDGE_INT, sc->sc_intr_status00_23);
 	gp_write(sc, RA_PIO_24_39_INT, sc->sc_intr_status24_39);
 	gp_write(sc, RA_PIO_24_39_EDGE_INT, sc->sc_intr_status24_39);
 	gp_write(sc, RA_PIO_40_51_INT, sc->sc_intr_status40_51);
 	gp_write(sc, RA_PIO_40_51_EDGE_INT, sc->sc_intr_status40_51);
 #if defined(SLICKROCK)
 	gp_write(sc, RA_PIO_72_95_INT, sc->sc_intr_status72_95);
 	gp_write(sc, RA_PIO_72_95_EDGE_INT, sc->sc_intr_status72_95);
 #endif
 	/* Reset until next time */
 	sc->sc_intr_status00_23 = 0;
 	sc->sc_intr_status24_39 = 0;
 	sc->sc_intr_status40_51 = 0;
 	sc->sc_intr_status72_95 = 0;
 #endif /* MT7628 */
 	return 1;
+}
 /*
  *  Handle key debouncing for the given pin
  */
 static bool
 ra_gpio_debounce_pin(ra_gpio_softc_t *sc, struct timeval *tv, u_int pin)
+{
 	RALINK_DEBUG_FUNC_ENTRY();
 	/*
 	 * If a pin has a time set, it is waiting for
 	 *  a debounce period.  Check if it is ready
 	 *  to send its event and clean up.  Otherwise,
 	 *  reschedule 10mSec and try again later.
 	 */
 	if (0 != debounce_time[pin].tv_sec) {
 		if (timercmp(tv, &debounce_time[pin], <)) {
 			/*
 			 * Haven't hit debounce time,
 			 * need to reschedule
 			 */
 			return true;
+		}
 #if defined(SLICKROCK)
 		switch (debounce_pin[pin]) {
 		case SOFT_RST_IN_BUTTON:
 			KNOTE(&knotes, RESET_BUTTON_EVT);
 			break;
 		case SS_BUTTON:
 			KNOTE(&knotes, SS_BUTTON_EVT);
 			break;
 		case WPS_BUTTON:
 			KNOTE(&knotes, WPS_BUTTON_EVT);
 			break;
 		case WIFI_ENABLE:
 			KNOTE(&knotes, WIFI_ENABLE_EVT);
 			break;
 		/*
 		 * These events are in case of overcurrent
 		 * on USB/ExpressCard devices.
 		 * If we receive an overcurrent signal,
 		 * turn off power to the device and
 		 * let the USB driver know.
 		 */
 		case CURRENT_LIMIT_FLAG_USB1:
 			ra_gpio_pin_write(sc, POWER_EN_USB1, 0);
 			KNOTE(&knotes, CURRENT_LIMIT_EVT);
 #if 0
 			cpusb_overcurrent_occurred(CURRENT_LIMIT_FLAG_USB1);
 #endif
 			printf("\nUSB1 current limit received!\n");
 			break;
 		case CURRENT_LIMIT_FLAG_USB2:
 			ra_gpio_pin_write(sc, POWER_EN_USB2, 0);
 			KNOTE(&knotes, CURRENT_LIMIT_EVT);
 #if 0
 			cpusb_overcurrent_occurred(CURRENT_LIMIT_FLAG_USB2);
 #endif
 			printf("\nUSB2 current limit received!\n");
 			break;
 		case CURRENT_LIMIT_FLAG_USB3:
 			ra_gpio_pin_write(sc, POWER_EN_USB3, 0);
 			KNOTE(&knotes, CURRENT_LIMIT_EVT);
 #if 0
 			cpusb_overcurrent_occurred(CURRENT_LIMIT_FLAG_USB3);
 #endif
 			printf("\nUSB3 current limit received!\n");
 			break;
 		case CURRENT_LIMIT_FLAG_EX1:
 			ra_gpio_pin_write(sc, POWER_EN_EX1, 0);
 			KNOTE(&knotes, CURRENT_LIMIT_EVT);
 #if 0
 			cpusb_overcurrent_occurred(debounce_pin[pin]);
 #endif
 			printf("\nExpressCard1 current limit received!\n");
 			break;
 		case CURRENT_LIMIT_FLAG_EX2:
 			ra_gpio_pin_write(sc, POWER_EN_EX2, 0);
 			KNOTE(&knotes, CURRENT_LIMIT_EVT);
 #if 0
 			cpusb_overcurrent_occurred(debounce_pin[pin]);
 #endif
 			printf("\nExpressCard2 current limit received!\n");
 			break;
 		default:
 			printf("\nUnknown debounce pin %d received.\n",
 			    debounce_pin[pin]);
+		}
 #endif/* SLICKROCK */
 #if defined(PEBBLES500) || defined(PEBBLES35)
 		switch (debounce_pin[pin]) {
 		case SOFT_RST_IN_BUTTON:
 			KNOTE(&knotes, RESET_BUTTON_EVT);
 			break;
 		case WPS_BUTTON:
 			KNOTE(&knotes, WPS_BUTTON_EVT);
 			break;
 		case EXCARD_ATTACH:
 			KNOTE(&knotes, EXCARD_ATTACH_EVT);
 			break;
 		/*
 		 * These events are in case of overcurrent
 		 * on USB/ExpressCard devices.
 		 * If we receive an overcurrent signal,
 		 * turn off power to the device and
 		 * let the USB driver know.
 		 */
 		case CURRENT_LIMIT_FLAG_USB1:
 			ra_gpio_pin_write(sc, POWER_EN_USB, 0);
 			KNOTE(&knotes, CURRENT_LIMIT_EVT);
 			cpusb_overcurrent_occurred(CURRENT_LIMIT_FLAG_USB1);
 			printf("\nUSB current limit received!\n");
 			break;
 		/*
 		 * If either voltage is over current,
 		 * turn off all ExpressCard power
 		 */
 		case CURRENT_LIMIT_FLAG1_3_3v:
 		case CURRENT_LIMIT_FLAG1_1_5v:
 			ra_gpio_pin_write(sc, POWER_EN_EXCARD1_3_3v, 0);
 			ra_gpio_pin_write(sc, POWER_EN_EXCARD1_1_5v, 0);
 			KNOTE(&knotes, CURRENT_LIMIT_EVT);
 			cpusb_overcurrent_occurred(debounce_pin[pin]);
 			printf("\nExpressCard current limit received!\n");
 			break;
 		default:
 			printf("\nUnknown debounce pin received.\n");
+		}
 #endif/* PEBBLES500 || PEBBLES35 */
 #if defined(TABLEROCK) || defined(SPOT2) || defined(PUCK) || defined(MOAB)
 		if (POWER_OFF_BUTTON == debounce_pin[pin]) {
 			KNOTE(&knotes, POWER_BUTTON_EVT);
+		}
 		if (LAN_WAN_SW == debounce_pin[pin]) {
 			KNOTE(&knotes, LAN_WAN_SW_EVT);
+		}
 		if (DOCK_SENSE == debounce_pin[pin]) {
 			KNOTE(&knotes, DOCK_SENSE_EVT);
+		}
 		if (WPS_BUTTON == debounce_pin[pin]) {
 			KNOTE(&knotes, WPS_BUTTON_EVT);
+		}
 		if (IN_5V == debounce_pin[pin]) {
 			/* Set the charger to match the in 5V line */
 			if (ra_gpio_pin_read(sc, IN_5V) == 0) {
 				ra_gpio_pin_write(sc, CHARGER_OFF, 0);
 			} else {
 				ra_gpio_pin_write(sc, CHARGER_OFF, 1);
+			}
 			KNOTE(&knotes, IN_5V_EVT);
+		}
 #endif/* TABLEROCK || SPOT2 || PUCK || MOAB */
 		/* Re-enable interrupt and reset time */
 		enable_gpio_interrupt(sc, debounce_pin[pin]);
 		debounce_time[pin].tv_sec = 0;
+	}
 	return false;
+}
 /*
  *  Handle key debouncing.
  *  Re-enable the key interrupt after DEBOUNCE_TIME
  */
 static void
 ra_gpio_debounce_process(void *arg)
+{
 	RALINK_DEBUG_FUNC_ENTRY();
 	ra_gpio_softc_t * const sc = arg;
 	bool reschedule = false;
 	struct timeval now;
 	microtime(&now);
 	for (u_int pin=0; pin < __arraycount(debounce_pin); pin++)
 		if (ra_gpio_debounce_pin(sc, &now, pin))
 			reschedule = true;
 	if (reschedule)
 		callout_schedule(&sc->sc_tick_callout, MS_TO_HZ(10));
+}
 /*
  * Handle key and other interrupt debouncing.
  */
 static void
 ra_gpio_debounce_setup(ra_gpio_softc_t *sc)
+{
 	RALINK_DEBUG_FUNC_ENTRY();
 	u_int32_t pin;
 	struct timeval now;
 	struct timeval wait = {
 		.tv_sec  = 0,
 		.tv_usec = (DEBOUNCE_TIME * 1000)
 	};
 	/*
 	 * The 371/372 series are a bit more complex.  They have
 	 *  interrupt sources across all three interrupt
 	 *  registers.
 	 */
 	for (int i = 0; i < __arraycount(debounce_pin); i++) {
 		u_int32_t *intr_status;
 		int offset;
 #if defined(MT7628)
 		if (debounce_pin[i] < 32) {
 			intr_status = &sc->sc_intr_status00_31;
 			offset = 0;
 		} else if (debounce_pin[i] < 64) {
 			intr_status = &sc->sc_intr_status32_63;
 			offset = 32;
 		} else {
 			intr_status = &sc->sc_intr_status64_95;
 			offset = 64;
+		}
 #else /* !MT7628 */
 		if (debounce_pin[i] < 24) {
 			intr_status = &sc->sc_intr_status00_23;
 			offset = 0;
 		} else if (debounce_pin[i] < 40) {
 			intr_status = &sc->sc_intr_status24_39;
 			offset = 24;
 		} else if (debounce_pin[i] < 71) {
 			intr_status = &sc->sc_intr_status40_51;
 			offset = 40;
 		} else {
 			intr_status = &sc->sc_intr_status72_95;
 			offset = 72;
+		}
 #endif /* !MT7628 */
 		if (*intr_status & (1 << (debounce_pin[i] - offset))) {
 			pin = debounce_pin[i];
 #ifdef ENABLE_RALINK_DEBUG_INFO
 			if (ra_gpio_pin_read(sc, pin)) {
 				RALINK_DEBUG(RALINK_DEBUG_INFO,
 				    "%s() button 0x%x, pin %d released\n",
 				    __func__, *intr_status, pin);
 			} else {
 				RALINK_DEBUG(RALINK_DEBUG_INFO,
 				    "%s() button 0x%x, pin %d pressed\n",
 				    __func__, *intr_status, pin);
+			}
 #endif
 #if 0
 			/* Mask pin that is being handled */
 			*intr_status &= ~((1 << (debounce_pin[i] - offset)));
 #endif
 			/* Handle debouncing. */
 			disable_gpio_interrupt(sc, pin);
 			microtime(&now);
 #if defined(TABLEROCK)
 			/*
 			 * The dock's LAN_WAN switch can cause a fire of
 			 * interrupts if it sticks in the half-way position.
 			 * Ignore it for longer than other buttons.
 			 */
 			if (pin == LAN_WAN_SW) {
 				wait.tv_usec *= 2;
+			}
 #endif
 			timeradd(&now, &wait, &debounce_time[i]);
+		}
+	}
 	/* If the debounce callout hasn't been scheduled, start it up. */
 	if (FALSE == callout_pending(&sc->sc_tick_callout)) {
 		callout_schedule(&sc->sc_tick_callout, MS_TO_HZ(DEBOUNCE_TIME));
+	}
+}
 /*
  * Disable both rising and falling
  */
 static void
 disable_gpio_interrupt(ra_gpio_softc_t *sc, int pin)
+{
 	RALINK_DEBUG_FUNC_ENTRY();
 	const int index = pin_tab_index[pin];
 	KASSERTMSG(index != -1, "%s: non-existant pin=%d\n", __func__, pin);
 	if (index == -1)
 		return;
 	const pin_tab_t * const ptp = &pin_tab[index];
 	const uint32_t reg_bit = 1 << (pin - ptp->pin_reg_base);
 	uint32_t r;
 	r = gp_read(sc, ptp->pin_rise.reg);
 	r &= ~reg_bit;
 	gp_write(sc, ptp->pin_rise.reg, r);
 	r = gp_read(sc, ptp->pin_fall.reg);
 	r &= ~reg_bit;
 	gp_write(sc, ptp->pin_fall.reg, r);
+}
 /*
  * Restore GPIO interrupt setting
  */
 static void
 enable_gpio_interrupt(ra_gpio_softc_t *sc, int pin)
+{
 	const int index = pin_tab_index[pin];
 	KASSERTMSG(index != -1, "%s: non-existant pin=%d\n", __func__, pin);
 	if (index == -1)
 		return;
 	const pin_tab_t * const ptp = &pin_tab[index];
 	const uint32_t mask_bit = 1 << (pin - ptp->pin_mask_base);
 	const uint32_t reg_bit = 1 << (pin - ptp->pin_reg_base);
 	uint32_t r;
 	if (ptp->pin_rise.mask & mask_bit) {
 		r = gp_read(sc, ptp->pin_rise.reg);
 		r |= reg_bit;
 		gp_write(sc, ptp->pin_rise.reg, r);
+	}
 	if (ptp->pin_fall.mask & mask_bit) {
 		r = gp_read(sc, ptp->pin_fall.reg);
 		r |= reg_bit;
 		gp_write(sc, ptp->pin_fall.reg, r);
+	}
+}
 /*
  * XXX this function is obsolete/unused? XXX
+ *
  *  Go through each of the interrupts and send the appropriate
  *   event.
  */
 static void
 ra_gpio_softintr(void *arg)
+{
 #if defined(MT7628)
 	RALINK_DEBUG(RALINK_DEBUG_INFO,
 	    "gpio softintr called with 0x%x, 0x%x, 0x%x\n",
 	    sc->sc_intr_status00_31, sc->sc_intr_status32_63,
 	    sc->sc_intr_status64_95);
 #else
 	RALINK_DEBUG(RALINK_DEBUG_INFO,
 	    "gpio softintr called with 0x%x, 0x%x, 0x%x, 0x%x\n",
 	    sc->sc_intr_status00_23, sc->sc_intr_status24_39,
 	    sc->sc_intr_status40_51, sc->sc_intr_status72_95);
 #endif