Sat Oct 31 04:05:42 2020 UTC ()
Match linux here and wait without interrupts.

>From David H. Gutteridge in PR port-amd64/55555
There's a second part to the patch, but "make our code behave the way
the upstream code does" is very welcome.
Also PR kern/54515 and possibly others.


(maya)
diff -r1.10 -r1.11 src/sys/external/bsd/drm2/dist/drm/i915/intel_sprite.c
cvs diff -r1.10 -r1.11 src/sys/external/bsd/drm2/dist/drm/i915/Attic/intel_sprite.c (expand / switch to unified diff)

--- src/sys/external/bsd/drm2/dist/drm/i915/Attic/intel_sprite.c 2020/02/14 04:36:12 1.10
+++ src/sys/external/bsd/drm2/dist/drm/i915/Attic/intel_sprite.c 2020/10/31 04:05:42 1.11
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: intel_sprite.c,v 1.10 2020/02/14 04:36:12 riastradh Exp $ */ 1/* $NetBSD: intel_sprite.c,v 1.11 2020/10/31 04:05:42 maya Exp $ */
2 2
3/* 3/*
4 * Copyright © 2011 Intel Corporation 4 * Copyright © 2011 Intel Corporation
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation 8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the 10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions: 11 * Software is furnished to do so, subject to the following conditions:
12 * 12 *
13 * The above copyright notice and this permission notice (including the next 13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the 14 * paragraph) shall be included in all copies or substantial portions of the
@@ -22,27 +22,27 @@ @@ -22,27 +22,27 @@
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE. 23 * SOFTWARE.
24 * 24 *
25 * Authors: 25 * Authors:
26 * Jesse Barnes <jbarnes@virtuousgeek.org> 26 * Jesse Barnes <jbarnes@virtuousgeek.org>
27 * 27 *
28 * New plane/sprite handling. 28 * New plane/sprite handling.
29 * 29 *
30 * The older chips had a separate interface for programming plane related 30 * The older chips had a separate interface for programming plane related
31 * registers; newer ones are much simpler and we can use the new DRM plane 31 * registers; newer ones are much simpler and we can use the new DRM plane
32 * support. 32 * support.
33 */ 33 */
34#include <sys/cdefs.h> 34#include <sys/cdefs.h>
35__KERNEL_RCSID(0, "$NetBSD: intel_sprite.c,v 1.10 2020/02/14 04:36:12 riastradh Exp $"); 35__KERNEL_RCSID(0, "$NetBSD: intel_sprite.c,v 1.11 2020/10/31 04:05:42 maya Exp $");
36 36
37#include <drm/drmP.h> 37#include <drm/drmP.h>
38#include <drm/drm_crtc.h> 38#include <drm/drm_crtc.h>
39#include <drm/drm_fourcc.h> 39#include <drm/drm_fourcc.h>
40#include <drm/drm_rect.h> 40#include <drm/drm_rect.h>
41#include <drm/drm_atomic.h> 41#include <drm/drm_atomic.h>
42#include <drm/drm_plane_helper.h> 42#include <drm/drm_plane_helper.h>
43#include "intel_drv.h" 43#include "intel_drv.h"
44#include <drm/i915_drm.h> 44#include <drm/i915_drm.h>
45#include "i915_drv.h" 45#include "i915_drv.h"
46#include "i915_trace.h" 46#include "i915_trace.h"
47 47
48static bool 48static bool
@@ -114,27 +114,27 @@ void intel_pipe_update_start(struct inte @@ -114,27 +114,27 @@ void intel_pipe_update_start(struct inte
114#endif 114#endif
115 115
116 if (min <= 0 || max <= 0) 116 if (min <= 0 || max <= 0)
117 return; 117 return;
118 118
119 if (WARN_ON(drm_crtc_vblank_get_locked(&crtc->base))) 119 if (WARN_ON(drm_crtc_vblank_get_locked(&crtc->base)))
120 return; 120 return;
121 121
122 crtc->debug.min_vbl = min; 122 crtc->debug.min_vbl = min;
123 crtc->debug.max_vbl = max; 123 crtc->debug.max_vbl = max;
124 trace_i915_pipe_update_start(crtc); 124 trace_i915_pipe_update_start(crtc);
125 125
126#ifdef __NetBSD__ 126#ifdef __NetBSD__
127 DRM_SPIN_TIMED_WAIT_UNTIL(ret, wq, &dev->vbl_lock, timeout, 127 DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL(ret, wq, &dev->vbl_lock, timeout,
128 (scanline = intel_get_crtc_scanline(crtc), 128 (scanline = intel_get_crtc_scanline(crtc),
129 scanline < min || scanline > max)); 129 scanline < min || scanline > max));
130 if (ret <= 0) 130 if (ret <= 0)
131 DRM_ERROR("Potential atomic update failure on pipe %c: %d\n", 131 DRM_ERROR("Potential atomic update failure on pipe %c: %d\n",
132 pipe_name(crtc->pipe), ret ? ret : -EWOULDBLOCK); 132 pipe_name(crtc->pipe), ret ? ret : -EWOULDBLOCK);
133 drm_crtc_vblank_put_locked(&crtc->base); 133 drm_crtc_vblank_put_locked(&crtc->base);
134#else 134#else
135 for (;;) { 135 for (;;) {
136 /* 136 /*
137 * prepare_to_wait() has a memory barrier, which guarantees 137 * prepare_to_wait() has a memory barrier, which guarantees
138 * other CPUs can see the task state update by the time we 138 * other CPUs can see the task state update by the time we
139 * read the scanline. 139 * read the scanline.
140 */ 140 */