Sun Nov 1 19:47:46 2020 UTC ()
Comments from zmcgrew@


(skrll)
diff -r1.4 -r1.5 src/sys/arch/riscv/include/pte.h

cvs diff -r1.4 -r1.5 src/sys/arch/riscv/include/pte.h (expand / switch to unified diff)

--- src/sys/arch/riscv/include/pte.h 2020/03/14 16:12:16 1.4
+++ src/sys/arch/riscv/include/pte.h 2020/11/01 19:47:46 1.5
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: pte.h,v 1.4 2020/03/14 16:12:16 skrll Exp $ */ 1/* $NetBSD: pte.h,v 1.5 2020/11/01 19:47:46 skrll Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2014, 2019 The NetBSD Foundation, Inc. 4 * Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas (of 3am Software Foundry) and Maxime Villard. 8 * by Matt Thomas (of 3am Software Foundry) and Maxime Villard.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -49,34 +49,35 @@ typedef __uint32_t pd_entry_t; @@ -49,34 +49,35 @@ typedef __uint32_t pd_entry_t;
49#define atomic_cas_pte atomic_cas_32 49#define atomic_cas_pte atomic_cas_32
50#endif 50#endif
51 51
52#define PTE_PPN_SHIFT 10 52#define PTE_PPN_SHIFT 10
53 53
54#define NPTEPG (PAGE_SIZE / sizeof(pt_entry_t)) 54#define NPTEPG (PAGE_SIZE / sizeof(pt_entry_t))
55#define NSEGPG NPTEPG 55#define NSEGPG NPTEPG
56#define NPDEPG NPTEPG 56#define NPDEPG NPTEPG
57 57
58/* Software PTE bits. */ 58/* Software PTE bits. */
59#define PTE_WIRED __BIT(8) 59#define PTE_WIRED __BIT(8)
60 60
61/* Hardware PTE bits. */ 61/* Hardware PTE bits. */
62#define PTE_D __BIT(7) 62// These are hardware defined bits
63#define PTE_A __BIT(6) 63#define PTE_D __BIT(7) // Dirty
64#define PTE_G __BIT(5) 64#define PTE_A __BIT(6) // Accessed
65#define PTE_U __BIT(4) 65#define PTE_G __BIT(5) // Global
66#define PTE_X __BIT(3) 66#define PTE_U __BIT(4) // User
67#define PTE_W __BIT(2) 67#define PTE_X __BIT(3) // eXecute
68#define PTE_R __BIT(1) 68#define PTE_W __BIT(2) // Write
69#define PTE_V __BIT(0) 69#define PTE_R __BIT(1) // Read
 70#define PTE_V __BIT(0) // Valid
70 71
71#define PA_TO_PTE(pa) (((pa) >> PAGE_SHIFT) << PTE_PPN_SHIFT) 72#define PA_TO_PTE(pa) (((pa) >> PAGE_SHIFT) << PTE_PPN_SHIFT)
72#define PTE_TO_PA(pte) (((pte) >> PTE_PPN_SHIFT) << PAGE_SHIFT) 73#define PTE_TO_PA(pte) (((pte) >> PTE_PPN_SHIFT) << PAGE_SHIFT)
73 74
74#define L2_SHIFT 30 75#define L2_SHIFT 30
75#define L1_SHIFT 21 76#define L1_SHIFT 21
76#define L0_SHIFT 12 77#define L0_SHIFT 12
77 78
78#define L2_SIZE (1 << L2_SHIFT) 79#define L2_SIZE (1 << L2_SHIFT)
79#define L1_SIZE (1 << L1_SHIFT) 80#define L1_SIZE (1 << L1_SHIFT)
80#define L0_SIZE (1 << L0_SHIFT) 81#define L0_SIZE (1 << L0_SHIFT)
81 82
82#define L2_OFFSET (L2_SIZE - 1) 83#define L2_OFFSET (L2_SIZE - 1)