 @@ -1,14 +1,14 @@
-/* $NetBSD: sysreg.h,v 1.5 2020/03/14 16:12:16 skrll Exp $ */
+/* $NetBSD: sysreg.h,v 1.6 2020/11/01 21:09:48 skrll Exp $ */
 /*
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -145,38 +145,44 @@ riscvreg_status_clear(uint32_t __mask)
 static inline uint32_t
 riscvreg_status_set(uint32_t __mask)
+{
 	uint32_t __sr;
 	if (__builtin_constant_p(__mask) && __mask < 0x20) {
 		__asm("csrrsi\t%0, sstatus, %1" : "=r"(__sr) : "i"(__mask));
 	} else {
 		__asm("csrrs\t%0, sstatus, %1" : "=r"(__sr) : "r"(__mask));
+	}
 	return __sr;
+}
 // Cause register
-#define CAUSE_MISALIGNED_FETCH		0
+#define CAUSE_FETCH_MISALIGNED		0
-#define CAUSE_FAULT_FETCH		1
+#define CAUSE_FETCH_ACCESS		1
 #define CAUSE_ILLEGAL_INSTRUCTION	2
-#define CAUSE_PRIVILEGED_INSTRUCTION	3
+#define CAUSE_BREAKPOINT		3
-#define CAUSE_MISALIGNED_LOAD		4
+#define CAUSE_LOAD_MISALIGNED		4
-#define CAUSE_FAULT_LOAD		5
+#define CAUSE_LOAD_ACCESS		5
-#define CAUSE_MISALIGNED_STORE		6
+#define CAUSE_STORE_MISALIGNED		6
-#define CAUSE_FAULT_STORE		7
+#define CAUSE_STORE_ACCESS		7
 #define CAUSE_SYSCALL			8
-#define CAUSE_BREAKPOINT		9
+#define CAUSE_USER_ECALL		8
-#define CAUSE_FP_DISABLED		10
+#define CAUSE_SUPERVISOR_ECALL		9
-#define CAUSE_ACCELERATOR_DISABLED	12
+/* 10 is reserved */
 #define CAUSE_MACHINE_ECALL		11
 #define CAUSE_FETCH_PAGE_FAULT		12
 #define CAUSE_LOAD_PAGE_FAULT		13
 /* 14 is Reserved */
 #define CAUSE_STORE_PAGE_FAULT		15
 /* >= 16 is reserved */
 static inline uint64_t
 riscvreg_cycle_read(void)
+{
 #ifdef _LP64
 	uint64_t __lo;
 	__asm __volatile("csrr\t%0, cycle" : "=r"(__lo));
 	return __lo;
 #else
 	uint32_t __hi0, __hi1, __lo0;
 	do {
 		__asm __volatile(
 			"csrr\t%[__hi0], cycleh"

 @@ -22,61 +22,58 @@
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
 #define __PMAP_PRIVATE
 #define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.9 2020/11/01 21:06:22 skrll Exp $");
+__RCSID("$NetBSD: trap.c,v 1.10 2020/11/01 21:09:48 skrll Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/atomic.h>
 #include <sys/signal.h>
 #include <sys/signalvar.h>
 #include <sys/siginfo.h>
 #include <uvm/uvm.h>
 #include <riscv/locore.h>
-#define	INSTRUCTION_TRAP_MASK	(__BIT(CAUSE_PRIVILEGED_INSTRUCTION) \
+#define	INSTRUCTION_TRAP_MASK	(__BIT(CAUSE_ILLEGAL_INSTRUCTION))
 				|__BIT(CAUSE_ILLEGAL_INSTRUCTION))
-#define	FAULT_TRAP_MASK		(__BIT(CAUSE_FAULT_FETCH) \
+#define	FAULT_TRAP_MASK		(__BIT(CAUSE_FETCH_ACCESS) \
-				|__BIT(CAUSE_FAULT_LOAD) \
+				|__BIT(CAUSE_LOAD_ACCESS) \
-				|__BIT(CAUSE_FAULT_STORE))
+				|__BIT(CAUSE_STORE_ACCESS))
-#define	MISALIGNED_TRAP_MASK	(__BIT(CAUSE_MISALIGNED_FETCH) \
+#define	MISALIGNED_TRAP_MASK	(__BIT(CAUSE_FETCH_MISALIGNED) \
-				|__BIT(CAUSE_MISALIGNED_LOAD) \
+				|__BIT(CAUSE_LOAD_MISALIGNED) \
-				|__BIT(CAUSE_MISALIGNED_STORE))
+				|__BIT(CAUSE_STORE_MISALIGNED))
 static const char * const causenames[] = {
-	[CAUSE_MISALIGNED_FETCH] = "misaligned fetch",
+	[CAUSE_FETCH_MISALIGNED] = "misaligned fetch",
-	[CAUSE_MISALIGNED_LOAD] = "misaligned load",
+	[CAUSE_LOAD_MISALIGNED] = "misaligned load",
-	[CAUSE_MISALIGNED_STORE] = "misaligned store",
+	[CAUSE_STORE_MISALIGNED] = "misaligned store",
-	[CAUSE_FAULT_FETCH] = "fetch",
+	[CAUSE_FETCH_ACCESS] = "fetch",
-	[CAUSE_FAULT_LOAD] = "load",
+	[CAUSE_LOAD_ACCESS] = "load",
-	[CAUSE_FAULT_STORE] = "store",
+	[CAUSE_STORE_ACCESS] = "store",
 	[CAUSE_FP_DISABLED] = "fp disabled",
 	[CAUSE_ILLEGAL_INSTRUCTION] = "illegal instruction",
 	[CAUSE_PRIVILEGED_INSTRUCTION] = "privileged instruction",
 	[CAUSE_BREAKPOINT] = "breakpoint",
 };
 void
 cpu_jump_onfault(struct trapframe *tf, const struct faultbuf *fb)
+{
 	tf->tf_a0 = fb->fb_reg[FB_A0];
 	tf->tf_ra = fb->fb_reg[FB_RA];
 	tf->tf_s0 = fb->fb_reg[FB_S0];
 	tf->tf_s1 = fb->fb_reg[FB_S1];
 	tf->tf_s2 = fb->fb_reg[FB_S2];
 	tf->tf_s3 = fb->fb_reg[FB_S3];
 	tf->tf_s4 = fb->fb_reg[FB_S4];
 @@ -210,31 +207,31 @@ trap_ksi_init(ksiginfo_t *ksi, int signo
 static void
 cpu_trapsignal(struct trapframe *tf, ksiginfo_t *ksi)
+{
 	if (cpu_printfataltraps) {
 		dump_trapframe(tf, printf);
+	}
 	(*curlwp->l_proc->p_emul->e_trapsignal)(curlwp, ksi);
+}
 static inline vm_prot_t
 get_faulttype(register_t cause)
+{
-	if (cause == CAUSE_FAULT_LOAD)
+	if (cause == CAUSE_LOAD_ACCESS)
 		return VM_PROT_READ;
-	if (cause == CAUSE_FAULT_STORE)
+	if (cause == CAUSE_STORE_ACCESS)
 		return VM_PROT_READ | VM_PROT_WRITE;
-	KASSERT(cause == CAUSE_FAULT_FETCH);
+	KASSERT(cause == CAUSE_FETCH_ACCESS);
 	return VM_PROT_READ | VM_PROT_EXECUTE;
+}
 static bool
 trap_pagefault_fixup(struct trapframe *tf, struct pmap *pmap, register_t cause,
     intptr_t addr)
+{
 	pt_entry_t * const ptep = pmap_pte_lookup(pmap, addr);
 	struct vm_page *pg;
 	if (ptep == NULL)
 		return false;
 @@ -246,32 +243,32 @@ trap_pagefault_fixup(struct trapframe *t
 			return false;
 		pg = PHYS_TO_VM_PAGE(pte_to_paddr(opte));
 		if (pg == NULL)
 			return false;
 		attr = 0;
 		npte = opte;
 		if ((npte & PTE_V) == 0) {
 			npte |= PTE_V;
 			attr |= VM_PAGEMD_REFERENCED;
+		}
 #if 0		/* XXX Outdated */
-		if (cause == CAUSE_FAULT_STORE) {
+		if (cause == CAUSE_STORE_ACCESS) {
 			if ((npte & PTE_NW) != 0) {
 				npte &= ~PTE_NW;
 				attr |= VM_PAGEMD_MODIFIED;
+			}
-		} else if (cause == CAUSE_FAULT_FETCH) {
+		} else if (cause == CAUSE_FETCH_ACCESS) {
 			if ((npte & PTE_NX) != 0) {
 				npte &= ~PTE_NX;
 				attr |= VM_PAGEMD_EXECPAGE;
+			}
+		}
 #endif
 		if (attr == 0)
 			return false;
 	} while (opte != atomic_cas_pte(ptep, opte, npte));
 	pmap_page_set_attributes(VM_PAGE_TO_MD(pg), attr);
 	pmap_tlb_update_addr(pmap, addr, npte, 0);
 @@ -339,29 +336,28 @@ trap_pagefault(struct trapframe *tf, reg
 	if (fb == NULL) {
 		return false;
+	}
 	cpu_jump_onfault(tf, fb);
 	return true;
+}
 static bool
 trap_instruction(struct trapframe *tf, register_t epc, register_t status,
     register_t cause, register_t badaddr, bool usertrap_p, ksiginfo_t *ksi)
+{
 	const bool prvopc_p = (cause == CAUSE_PRIVILEGED_INSTRUCTION);
 	if (usertrap_p) {
-		trap_ksi_init(ksi, SIGILL, prvopc_p ? ILL_PRVOPC : ILL_ILLOPC,
+		trap_ksi_init(ksi, SIGILL, ILL_ILLOPC,
 		    (intptr_t)badaddr, cause);
+	}
 	return false;
+}
 static bool
 trap_misalignment(struct trapframe *tf, register_t epc, register_t status,
     register_t cause, register_t badaddr, bool usertrap_p, ksiginfo_t *ksi)
+{
 	if (usertrap_p) {
 		trap_ksi_init(ksi, SIGBUS, BUS_ADRALN,
 		    (intptr_t)badaddr, cause);
+	}
 @@ -385,32 +381,34 @@ cpu_trap(struct trapframe *tf, register_
 		// about it.  See
 		struct pmap * const pmap = curlwp->l_proc->p_vmspace->vm_map.pmap;
 		if ((intptr_t) addr < 0
 		    && pmap != pmap_kernel()
 		    && pmap_pdetab_fixup(pmap, addr)) {
 			return;
+		}
 #endif
 		ok = trap_pagefault(tf, epc, status, cause, addr,
 		    usertrap_p, &ksi);
 	} else if (fault_mask & INSTRUCTION_TRAP_MASK) {
 		ok = trap_instruction(tf, epc, status, cause, addr,
 		    usertrap_p, &ksi);
 #if 0
 	} else if (fault_mask && __BIT(CAUSE_FP_DISABLED)) {
 		if (!usertrap_p) {
 			panic("%s: fp used @ %#"PRIxREGISTER" in kernel!",
 			    __func__, tf->tf_pc);
+		}
 		fpu_load();
 #endif
 	} else if (fault_mask & MISALIGNED_TRAP_MASK) {
 		ok = trap_misalignment(tf, epc, status, cause, addr,
 		    usertrap_p, &ksi);
 	} else {
 		dump_trapframe(tf, printf);
 		panic("%s: unknown kernel trap", __func__);
+	}
 	if (usertrap_p) {
 		if (!ok)
 			cpu_trapsignal(tf, &ksi);
 		userret(curlwp);
 	} else if (!ok) {