Mon Nov 2 08:37:59 2020 UTC ()

Add SATP_MODE values


(skrll)

diff -r1.7 -r1.8 src/sys/arch/riscv/include/sysreg.h

--- src/sys/arch/riscv/include/sysreg.h 2020/11/02 08:36:54	1.7
+++ src/sys/arch/riscv/include/sysreg.h 2020/11/02 08:37:59	1.8

 @@ -1,14 +1,14 @@
-/* $NetBSD: sysreg.h,v 1.7 2020/11/02 08:36:54 skrll Exp $ */
+/* $NetBSD: sysreg.h,v 1.8 2020/11/02 08:37:59 skrll Exp $ */
 /*
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -188,30 +188,33 @@ riscvreg_cycle_read(void)
 			"csrr\t%[__hi0], cycleh"
 		"\n\t"	"csrr\t%[__lo0], cycle"
 		"\n\t"	"csrr\t%[__hi1], cycleh"
 		   :	[__hi0] "=r"(__hi0),
 			[__lo0] "=r"(__lo0),
 			[__hi1] "=r"(__hi1));
 	} while (__hi0 != __hi1);
 	return ((uint64_t)__hi0 << 32) | (uint64_t)__lo0;
 #endif
+}
 #ifdef _LP64
 #define SATP_MODE		__BITS(63,60)
 #define  SATP_MODE_SV39		8
 #define  SATP_MODE_SV48		9
 #define SATP_ASID		__BITS(59,44)
 #define SATP_PPN		__BITS(43,0)
 #else
 #define SATP_MODE		__BIT(31)
 #define  SATP_MODE_SV32		1
 #define SATP_ASID		__BITS(30,22)
 #define SATP_PPN		__BITS(21,0)
 #endif
 static inline uint32_t
 riscvreg_asid_read(void)
+{
 	uintptr_t satp;
 	__asm __volatile("csrr	%0, satp" : "=r" (satp));
 	return __SHIFTOUT(satp, SATP_ASID);
+}
 static inline void