Wed Nov 4 06:56:56 2020 UTC ()
Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@


(skrll)
diff -r1.10 -r1.11 src/sys/arch/riscv/conf/GENERIC
diff -r1.6 -r1.7 src/sys/arch/riscv/conf/files.riscv
diff -r1.2 -r1.3 src/sys/arch/riscv/include/frame.h
diff -r1.5 -r1.6 src/sys/arch/riscv/include/locore.h
diff -r1.8 -r1.9 src/sys/arch/riscv/include/sysreg.h
diff -r1.3 -r1.4 src/sys/arch/riscv/riscv/core_machdep.c
diff -r1.4 -r1.5 src/sys/arch/riscv/riscv/db_machdep.c
diff -r1.7 -r1.8 src/sys/arch/riscv/riscv/genassym.cf
diff -r1.13 -r1.14 src/sys/arch/riscv/riscv/locore.S
diff -r1.10 -r1.11 src/sys/arch/riscv/riscv/trap.c
cvs diff -r1.10 -r1.11 src/sys/arch/riscv/conf/GENERIC (expand / switch to unified diff)

--- src/sys/arch/riscv/conf/GENERIC 2019/06/01 12:42:27 1.10
+++ src/sys/arch/riscv/conf/GENERIC 2020/11/04 06:56:56 1.11
@@ -1,43 +1,43 @@ @@ -1,43 +1,43 @@
1# $NetBSD: GENERIC,v 1.10 2019/06/01 12:42:27 maxv Exp $ 1# $NetBSD: GENERIC,v 1.11 2020/11/04 06:56:56 skrll Exp $
2# 2#
3# GENERIC machine description file 3# GENERIC machine description file
4# 4#
5# This machine description file is used to generate the default NetBSD 5# This machine description file is used to generate the default NetBSD
6# kernel. The generic kernel does not include all options, subsystems 6# kernel. The generic kernel does not include all options, subsystems
7# and device drivers, but should be useful for most applications. 7# and device drivers, but should be useful for most applications.
8# 8#
9# The machine description file can be customised for your specific 9# The machine description file can be customised for your specific
10# machine to reduce the kernel size and improve its performance. 10# machine to reduce the kernel size and improve its performance.
11# 11#
12# For further information on compiling NetBSD kernels, see the config(8) 12# For further information on compiling NetBSD kernels, see the config(8)
13# man page. 13# man page.
14# 14#
15# For further information on hardware support for this architecture, see 15# For further information on hardware support for this architecture, see
16# the intro(4) man page. For further information about kernel options 16# the intro(4) man page. For further information about kernel options
17# for this architecture, see the options(4) man page. For an explanation 17# for this architecture, see the options(4) man page. For an explanation
18# of each device driver in this file see the section 4 man page for the 18# of each device driver in this file see the section 4 man page for the
19# device. 19# device.
20 20
21include "arch/riscv/conf/std.riscv64" 21include "arch/riscv/conf/std.riscv64"
22 22
23options INCLUDE_CONFIG_FILE # embed config file in kernel binary 23options INCLUDE_CONFIG_FILE # embed config file in kernel binary
24 24
25#ident "GENERIC-$Revision: 1.10 $" 25#ident "GENERIC-$Revision: 1.11 $"
26 26
27maxusers 64 # estimated number of users 27maxusers 64 # estimated number of users
28 28
29# Standard system options 29# Standard system options
30 30#options FPE # Floating-point extension support
31options NTP # NTP phase/frequency locked loop 31options NTP # NTP phase/frequency locked loop
32 32
33options KTRACE # system call tracing via ktrace(1) 33options KTRACE # system call tracing via ktrace(1)
34 34
35# Note: SysV IPC parameters could be changed dynamically, see sysctl(8). 35# Note: SysV IPC parameters could be changed dynamically, see sysctl(8).
36options SYSVMSG # System V-like message queues 36options SYSVMSG # System V-like message queues
37options SYSVSEM # System V-like semaphores 37options SYSVSEM # System V-like semaphores
38options SYSVSHM # System V-like memory sharing 38options SYSVSHM # System V-like memory sharing
39 39
40options MODULAR # new style module(7) framework 40options MODULAR # new style module(7) framework
41options MODULAR_DEFAULT_AUTOLOAD 41options MODULAR_DEFAULT_AUTOLOAD
42options USERCONF # userconf(4) support 42options USERCONF # userconf(4) support
43#options PIPE_SOCKETPAIR # smaller, but slower pipe(2) 43#options PIPE_SOCKETPAIR # smaller, but slower pipe(2)
cvs diff -r1.6 -r1.7 src/sys/arch/riscv/conf/files.riscv (expand / switch to unified diff)

--- src/sys/arch/riscv/conf/files.riscv 2020/10/21 13:31:51 1.6
+++ src/sys/arch/riscv/conf/files.riscv 2020/11/04 06:56:56 1.7
@@ -1,30 +1,30 @@ @@ -1,30 +1,30 @@
1# $NetBSD: files.riscv,v 1.6 2020/10/21 13:31:51 christos Exp $ 1# $NetBSD: files.riscv,v 1.7 2020/11/04 06:56:56 skrll Exp $
2# 2#
3 3
4maxpartitions 16 4maxpartitions 16
5maxusers 8 32 64 5maxusers 8 32 64
6 6
7defflag opt_ddb.h DDB_TRACE 7defflag opt_ddb.h DDB_TRACE
8 8
9#file arch/riscv/riscv/locore.S 9#file arch/riscv/riscv/locore.S
10file arch/riscv/riscv/spl.S 10file arch/riscv/riscv/spl.S
11 11
12file arch/riscv/riscv/autoconf.c 12file arch/riscv/riscv/autoconf.c
13file arch/riscv/riscv/cpu_subr.c 13file arch/riscv/riscv/cpu_subr.c
14file arch/riscv/riscv/db_disasm.c ddb 14file arch/riscv/riscv/db_disasm.c ddb
15file arch/riscv/riscv/db_trace.c ddb 15file arch/riscv/riscv/db_trace.c ddb
16file arch/riscv/riscv/fixup.c 16file arch/riscv/riscv/fixup.c
17file arch/riscv/riscv/fpu.c 17file arch/riscv/riscv/fpu.c fpe
18file arch/riscv/riscv/ipifuncs.c multiprocessor 18file arch/riscv/riscv/ipifuncs.c multiprocessor
19file arch/riscv/riscv/stubs.c 19file arch/riscv/riscv/stubs.c
20file arch/riscv/riscv/syscall.c # syscall handler 20file arch/riscv/riscv/syscall.c # syscall handler
21file arch/riscv/riscv/trap.c # trap handlers 21file arch/riscv/riscv/trap.c # trap handlers
22 22
23file arch/riscv/riscv/core_machdep.c coredump 23file arch/riscv/riscv/core_machdep.c coredump
24file arch/riscv/riscv/clock_machdep.c 24file arch/riscv/riscv/clock_machdep.c
25file arch/riscv/riscv/db_machdep.c ddb | kgdb 25file arch/riscv/riscv/db_machdep.c ddb | kgdb
26file arch/riscv/riscv/exec_machdep.c 26file arch/riscv/riscv/exec_machdep.c
27file arch/riscv/riscv/kgdb_machdep.c kgdb 27file arch/riscv/riscv/kgdb_machdep.c kgdb
28file arch/riscv/riscv/kobj_machdep.c modular 28file arch/riscv/riscv/kobj_machdep.c modular
29file arch/riscv/riscv/pmap_machdep.c 29file arch/riscv/riscv/pmap_machdep.c
30file arch/riscv/riscv/process_machdep.c 30file arch/riscv/riscv/process_machdep.c
cvs diff -r1.2 -r1.3 src/sys/arch/riscv/include/frame.h (expand / switch to unified diff)

--- src/sys/arch/riscv/include/frame.h 2020/03/14 16:12:16 1.2
+++ src/sys/arch/riscv/include/frame.h 2020/11/04 06:56:56 1.3
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: frame.h,v 1.2 2020/03/14 16:12:16 skrll Exp $ */ 1/* $NetBSD: frame.h,v 1.3 2020/11/04 06:56:56 skrll Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas of 3am Software Foundry. 8 * by Matt Thomas of 3am Software Foundry.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -26,27 +26,27 @@ @@ -26,27 +26,27 @@
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE. 29 * POSSIBILITY OF SUCH DAMAGE.
30 */ 30 */
31 31
32#ifndef _RISCV_FRAME_H_ 32#ifndef _RISCV_FRAME_H_
33#define _RISCV_FRAME_H_ 33#define _RISCV_FRAME_H_
34 34
35#include <riscv/reg.h> 35#include <riscv/reg.h>
36 36
37struct trapframe { 37struct trapframe {
38 struct reg tf_regs __aligned(8); 38 struct reg tf_regs __aligned(8);
39 register_t tf_badvaddr; 39 register_t tf_stval; // supervisor trap value
40 register_t tf_pc; 40 register_t tf_sepc; // supervisor exception program counter
41 uint32_t tf_cause; // 32-bit register 41 register_t tf_scause; // supervisor cause register
42 uint32_t tf_sr; // 32-bit register 42 register_t tf_sr; // supervisor status register
43#define tf_reg tf_regs.r_reg 43#define tf_reg tf_regs.r_reg
44#define tf_a0 tf_reg[_X_A0] 44#define tf_a0 tf_reg[_X_A0]
45#define tf_t0 tf_reg[_X_T0] 45#define tf_t0 tf_reg[_X_T0]
46#define tf_v0 tf_reg[_X_V0] 46#define tf_v0 tf_reg[_X_V0]
47#define tf_v1 tf_reg[_X_V1] 47#define tf_v1 tf_reg[_X_V1]
48#define tf_ra tf_reg[_X_RA] 48#define tf_ra tf_reg[_X_RA]
49#define tf_sp tf_reg[_X_SP] 49#define tf_sp tf_reg[_X_SP]
50}; 50};
51 51
52#endif /* _RISCV_FRAME_H_ */ 52#endif /* _RISCV_FRAME_H_ */
cvs diff -r1.5 -r1.6 src/sys/arch/riscv/include/locore.h (expand / switch to unified diff)

--- src/sys/arch/riscv/include/locore.h 2020/03/14 16:12:16 1.5
+++ src/sys/arch/riscv/include/locore.h 2020/11/04 06:56:56 1.6
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: locore.h,v 1.5 2020/03/14 16:12:16 skrll Exp $ */ 1/* $NetBSD: locore.h,v 1.6 2020/11/04 06:56:56 skrll Exp $ */
2/*- 2/*-
3 * Copyright (c) 2014 The NetBSD Foundation, Inc. 3 * Copyright (c) 2014 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas of 3am Software Foundry. 7 * by Matt Thomas of 3am Software Foundry.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -29,29 +29,29 @@ @@ -29,29 +29,29 @@
29 */ 29 */
30 30
31#ifndef _RISCV_LOCORE_H_ 31#ifndef _RISCV_LOCORE_H_
32#define _RISCV_LOCORE_H_ 32#define _RISCV_LOCORE_H_
33 33
34#include <sys/lwp.h> 34#include <sys/lwp.h>
35#include <sys/userret.h> 35#include <sys/userret.h>
36 36
37#include <riscv/reg.h> 37#include <riscv/reg.h>
38#include <riscv/sysreg.h> 38#include <riscv/sysreg.h>
39 39
40struct trapframe { 40struct trapframe {
41 struct reg tf_regs; 41 struct reg tf_regs;
42 register_t tf_badaddr; 42 register_t tf_tval;
43 uint32_t tf_cause; // 32-bit register 43 register_t tf_cause;
44 uint32_t tf_sr; // 32-bit register 44 register_t tf_sr;
45#define tf_reg tf_regs.r_reg 45#define tf_reg tf_regs.r_reg
46#define tf_pc tf_regs.r_pc 46#define tf_pc tf_regs.r_pc
47#define tf_ra tf_reg[_X_RA] 47#define tf_ra tf_reg[_X_RA]
48#define tf_sp tf_reg[_X_SP] 48#define tf_sp tf_reg[_X_SP]
49#define tf_gp tf_reg[_X_GP] 49#define tf_gp tf_reg[_X_GP]
50#define tf_tp tf_reg[_X_TP] 50#define tf_tp tf_reg[_X_TP]
51#define tf_t0 tf_reg[_X_T0] 51#define tf_t0 tf_reg[_X_T0]
52#define tf_t1 tf_reg[_X_T1] 52#define tf_t1 tf_reg[_X_T1]
53#define tf_t2 tf_reg[_X_T2] 53#define tf_t2 tf_reg[_X_T2]
54#define tf_s0 tf_reg[_X_S0] 54#define tf_s0 tf_reg[_X_S0]
55#define tf_s1 tf_reg[_X_S1] 55#define tf_s1 tf_reg[_X_S1]
56#define tf_a0 tf_reg[_X_A0] 56#define tf_a0 tf_reg[_X_A0]
57#define tf_a1 tf_reg[_X_A1] 57#define tf_a1 tf_reg[_X_A1]
@@ -70,52 +70,52 @@ struct trapframe { @@ -70,52 +70,52 @@ struct trapframe {
70#define tf_s8 tf_reg[_X_S8] 70#define tf_s8 tf_reg[_X_S8]
71#define tf_s9 tf_reg[_X_S9] 71#define tf_s9 tf_reg[_X_S9]
72#define tf_s10 tf_reg[_X_S10] 72#define tf_s10 tf_reg[_X_S10]
73#define tf_s11 tf_reg[_X_S11] 73#define tf_s11 tf_reg[_X_S11]
74#define tf_t3 tf_reg[_X_T3] 74#define tf_t3 tf_reg[_X_T3]
75#define tf_t4 tf_reg[_X_T4] 75#define tf_t4 tf_reg[_X_T4]
76#define tf_t5 tf_reg[_X_T5] 76#define tf_t5 tf_reg[_X_T5]
77#define tf_t6 tf_reg[_X_T6] 77#define tf_t6 tf_reg[_X_T6]
78}; 78};
79 79
80// For COMPAT_NETBSD32 coredumps 80// For COMPAT_NETBSD32 coredumps
81struct trapframe32 { 81struct trapframe32 {
82 struct reg32 tf_regs; 82 struct reg32 tf_regs;
83 register32_t tf_badaddr; 83 register32_t tf_tval;
84 uint32_t tf_cause; // 32-bit register 84 register32_t tf_cause;
85 uint32_t tf_sr; // 32-bit register 85 register32_t tf_sr;
86}; 86};
87 87
88#define FB_A0 0 88#define FB_A0 0
89#define FB_RA 1 89#define FB_RA 1
90#define FB_SP 2 90#define FB_SP 2
91#define FB_GP 3 91#define FB_GP 3
92#define FB_S0 4 92#define FB_S0 4
93#define FB_S1 5 93#define FB_S1 5
94#define FB_S2 6 94#define FB_S2 6
95#define FB_S3 7 95#define FB_S3 7
96#define FB_S4 8 96#define FB_S4 8
97#define FB_S5 9 97#define FB_S5 9
98#define FB_S6 10 98#define FB_S6 10
99#define FB_S7 11 99#define FB_S7 11
100#define FB_S8 12 100#define FB_S8 12
101#define FB_S9 13 101#define FB_S9 13
102#define FB_S10 14 102#define FB_S10 14
103#define FB_S11 15 103#define FB_S11 15
104#define FB_MAX 16 104#define FB_MAX 16
105 105
106struct faultbuf { 106struct faultbuf {
107 register_t fb_reg[FB_MAX]; 107 register_t fb_reg[FB_MAX];
108 uint32_t fb_sr; 108 register_t fb_sr;
109}; 109};
110 110
111CTASSERT(sizeof(label_t) == sizeof(struct faultbuf)); 111CTASSERT(sizeof(label_t) == sizeof(struct faultbuf));
112 112
113struct mainbus_attach_args { 113struct mainbus_attach_args {
114 const char *maa_name; 114 const char *maa_name;
115 u_int maa_instance; 115 u_int maa_instance;
116}; 116};
117 117
118#ifdef _KERNEL 118#ifdef _KERNEL
119extern int cpu_printfataltraps; 119extern int cpu_printfataltraps;
120extern const pcu_ops_t pcu_fpu_ops; 120extern const pcu_ops_t pcu_fpu_ops;
121 121
cvs diff -r1.8 -r1.9 src/sys/arch/riscv/include/sysreg.h (expand / switch to unified diff)

--- src/sys/arch/riscv/include/sysreg.h 2020/11/02 08:37:59 1.8
+++ src/sys/arch/riscv/include/sysreg.h 2020/11/04 06:56:56 1.9
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: sysreg.h,v 1.8 2020/11/02 08:37:59 skrll Exp $ */ 1/* $NetBSD: sysreg.h,v 1.9 2020/11/04 06:56:56 skrll Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas of 3am Software Foundry. 8 * by Matt Thomas of 3am Software Foundry.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -33,26 +33,27 @@ @@ -33,26 +33,27 @@
33#define _RISCV_SYSREG_H_ 33#define _RISCV_SYSREG_H_
34 34
35#ifndef _KERNEL 35#ifndef _KERNEL
36#include <sys/param.h> 36#include <sys/param.h>
37#endif 37#endif
38 38
39#define FCSR_FMASK 0 // no exception bits 39#define FCSR_FMASK 0 // no exception bits
40#define FCSR_FRM __BITS(7,5) 40#define FCSR_FRM __BITS(7,5)
41#define FCSR_FRM_RNE 0b000 // Round Nearest, ties to Even 41#define FCSR_FRM_RNE 0b000 // Round Nearest, ties to Even
42#define FCSR_FRM_RTZ 0b001 // Round Towards Zero 42#define FCSR_FRM_RTZ 0b001 // Round Towards Zero
43#define FCSR_FRM_RDN 0b010 // Round DowN (-infinity) 43#define FCSR_FRM_RDN 0b010 // Round DowN (-infinity)
44#define FCSR_FRM_RUP 0b011 // Round UP (+infinity) 44#define FCSR_FRM_RUP 0b011 // Round UP (+infinity)
45#define FCSR_FRM_RMM 0b100 // Round to nearest, ties to Max Magnitude 45#define FCSR_FRM_RMM 0b100 // Round to nearest, ties to Max Magnitude
 46#define FCSR_FRM_DYN 0b111 // Dynamic rounding
46#define FCSR_FFLAGS __BITS(4,0) // Sticky bits 47#define FCSR_FFLAGS __BITS(4,0) // Sticky bits
47#define FCSR_NV __BIT(4) // iNValid operation 48#define FCSR_NV __BIT(4) // iNValid operation
48#define FCSR_DZ __BIT(3) // Divide by Zero 49#define FCSR_DZ __BIT(3) // Divide by Zero
49#define FCSR_OF __BIT(2) // OverFlow 50#define FCSR_OF __BIT(2) // OverFlow
50#define FCSR_UF __BIT(1) // UnderFlow 51#define FCSR_UF __BIT(1) // UnderFlow
51#define FCSR_NX __BIT(0) // iNeXact 52#define FCSR_NX __BIT(0) // iNeXact
52 53
53static inline uint32_t 54static inline uint32_t
54riscvreg_fcsr_read(void) 55riscvreg_fcsr_read(void)
55{ 56{
56 uint32_t __fcsr; 57 uint32_t __fcsr;
57 __asm("frcsr %0" : "=r"(__fcsr)); 58 __asm("frcsr %0" : "=r"(__fcsr));
58 return __fcsr; 59 return __fcsr;
@@ -91,45 +92,97 @@ riscvreg_fcsr_read_frm(void) @@ -91,45 +92,97 @@ riscvreg_fcsr_read_frm(void)
91 __asm("frrm\t%0" : "=r"(__old)); 92 __asm("frrm\t%0" : "=r"(__old));
92 return __SHIFTOUT(__old, FCSR_FRM); 93 return __SHIFTOUT(__old, FCSR_FRM);
93} 94}
94 95
95static inline uint32_t 96static inline uint32_t
96riscvreg_fcsr_write_frm(uint32_t __new) 97riscvreg_fcsr_write_frm(uint32_t __new)
97{ 98{
98 uint32_t __old; 99 uint32_t __old;
99 __new = __SHIFTIN(__new, FCSR_FRM); 100 __new = __SHIFTIN(__new, FCSR_FRM);
100 __asm volatile("fsrm\t%0, %1" : "=r"(__old) : "r"(__new)); 101 __asm volatile("fsrm\t%0, %1" : "=r"(__old) : "r"(__new));
101 return __SHIFTOUT(__old, FCSR_FRM); 102 return __SHIFTOUT(__old, FCSR_FRM);
102} 103}
103 104
104// Status Register 105/* Supervisor Status Register */
105#define SR_IP __BITS(31,24) // Pending interrupts 106#ifdef _LP64
106#define SR_IM __BITS(23,16) // Interrupt Mask 107#define SR_WPRI __BITS(62, 34) | __BITS(31,20) | __BIT(17) | \
107#define SR_VM __BIT(7) // MMU On 108 __BITS(12,9) | __BITS(7,6) | __BITS(3,2)
108#define SR_S64 __BIT(6) // RV64 supervisor mode 109#define SR_SD __BIT(63)
109#define SR_U64 __BIT(5) // RV64 user mode 110 /* Bits 62-34 are WPRI */
110#define SR_EF __BIT(4) // Enable Floating Point 111#define SR_UXL __BITS(33,32)
111#define SR_PEI __BIT(3) // Previous EI setting 112#define SR_UXL_32 1
112#define SR_EI __BIT(2) // Enable interrupts 113#define SR_UXL_64 2
113#define SR_PS __BIT(1) // Previous (S) supervisor setting 114#define SR_UXL_128 3
114#define SR_S __BIT(0) // Supervisor 115 /* Bits 31-20 are WPRI*/
 116#else
 117#define SR_WPRI __BITS(30,20) | __BIT(17) | __BITS(12,9) | \
 118 __BITS(7,6) | __BITS(3,2)
 119#define SR_SD __BIT(31)
 120 /* Bits 30-20 are WPRI*/
 121#endif /* _LP64 */
 122
 123/* Both RV32 and RV64 have the bottom 20 bits shared */
 124#define SR_MXR __BIT(19)
 125#define SR_SUM __BIT(18)
 126 /* Bit 17 is WPRI */
 127#define SR_XS __BITS(16,15)
 128#define SR_FS __BITS(14,13)
 129#define SR_FS_OFF 0
 130#define SR_FS_INITIAL 1
 131#define SR_FS_CLEAN 2
 132#define SR_FS_DIRTY 3
 133
 134 /* Bits 12-9 are WPRI */
 135#define SR_SPP __BIT(8)
 136 /* Bits 7-6 are WPRI */
 137#define SR_SPIE __BIT(5)
 138#define SR_UPIE __BIT(4)
 139 /* Bits 3-2 are WPRI */
 140#define SR_SIE __BIT(1)
 141#define SR_UIE __BIT(0)
 142
 143/* Supervisor interrupt registers */
 144/* ... interupt pending register (sip) */
 145 /* Bit (XLEN-1)-10 is WIRI */
 146#define SIP_SEIP __BIT(9)
 147#define SIP_UEIP __BIT(8)
 148 /* Bit 7-6 is WIRI */
 149#define SIP_STIP __BIT(5)
 150#define SIP_UTIP __BIT(4)
 151 /* Bit 3-2 is WIRI */
 152#define SIP_SSIP __BIT(1)
 153#define SIP_USIP __BIT(0)
 154
 155/* ... interupt-enable register (sie) */
 156 /* Bit (XLEN-1) - 10 is WIRI */
 157#define SIE_SEIE __BIT(9)
 158#define SIE_UEIE __BIT(8)
 159 /* Bit 7-6 is WIRI */
 160#define SIE_STIE __BIT(5)
 161#define SIE_UTIE __BIT(4)
 162 /* Bit 3-2 is WIRI */
 163#define SIE_SSIE __BIT(1)
 164#define SIE_USIE __BIT(0)
 165
 166/* Mask for all interrupts */
 167#define SIE_IM (SIE_SEI|SIE_UEIE|SIE_STIE|SIE_UTIE|SIE_SSIE|SIE_USIE)
115 168
116#ifdef _LP64 169#ifdef _LP64
117#define SR_USER (SR_EI|SR_U64|SR_S64|SR_VM|SR_IM) 170#define SR_USER (SR_UIE | SR_U64 | SR_S64 | SR_IM)
118#define SR_USER32 (SR_USER & ~SR_U64) 171#define SR_USER32 (SR_USER & ~SR_U64)
119#define SR_KERNEL (SR_S|SR_EI|SR_U64|SR_S64|SR_VM) 172#define SR_KERNEL (SR_S | SR_UIE | SR_U64 | SR_S64)
120#else 173#else
121#define SR_USER (SR_EI|SR_VM|SR_IM) 174#define SR_USER (SR_UIE||SR_IM)
122#define SR_KERNEL (SR_S|SR_EI|SR_VM) 175#define SR_KERNEL (SR_S|SR_UIE)
123#endif 176#endif
124 177
125static inline uint32_t 178static inline uint32_t
126riscvreg_status_read(void) 179riscvreg_status_read(void)
127{ 180{
128 uint32_t __sr; 181 uint32_t __sr;
129 __asm("csrr\t%0, sstatus" : "=r"(__sr)); 182 __asm("csrr\t%0, sstatus" : "=r"(__sr));
130 return __sr; 183 return __sr;
131} 184}
132 185
133static inline uint32_t 186static inline uint32_t
134riscvreg_status_clear(uint32_t __mask) 187riscvreg_status_clear(uint32_t __mask)
135{ 188{
cvs diff -r1.3 -r1.4 src/sys/arch/riscv/riscv/core_machdep.c (expand / switch to unified diff)

--- src/sys/arch/riscv/riscv/core_machdep.c 2019/11/20 19:37:52 1.3
+++ src/sys/arch/riscv/riscv/core_machdep.c 2020/11/04 06:56:56 1.4
@@ -20,27 +20,27 @@ @@ -20,27 +20,27 @@
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE. 27 * POSSIBILITY OF SUCH DAMAGE.
28 */ 28 */
29 29
30#include <sys/cdefs.h> 30#include <sys/cdefs.h>
31 31
32#ifndef CORENAME 32#ifndef CORENAME
33__RCSID("$NetBSD: core_machdep.c,v 1.3 2019/11/20 19:37:52 pgoyette Exp $"); 33__RCSID("$NetBSD: core_machdep.c,v 1.4 2020/11/04 06:56:56 skrll Exp $");
34#endif 34#endif
35 35
36#include <sys/param.h> 36#include <sys/param.h>
37#include <sys/systm.h> 37#include <sys/systm.h>
38#include <sys/proc.h> 38#include <sys/proc.h>
39#include <sys/core.h> 39#include <sys/core.h>
40#include <sys/exec.h> 40#include <sys/exec.h>
41#include <sys/cpu.h> 41#include <sys/cpu.h>
42#include <sys/compat_stub.h> 42#include <sys/compat_stub.h>
43 43
44#include <riscv/locore.h> 44#include <riscv/locore.h>
45 45
46#ifndef CORENAME 46#ifndef CORENAME
@@ -71,27 +71,27 @@ CORENAME(cpu_coredump)(struct lwp *l, st @@ -71,27 +71,27 @@ CORENAME(cpu_coredump)(struct lwp *l, st
71 chdr->c_cpusize = sizeof(struct cpustate); 71 chdr->c_cpusize = sizeof(struct cpustate);
72 chdr->c_nseg++; 72 chdr->c_nseg++;
73 return 0; 73 return 0;
74 } 74 }
75 75
76 pcu_save_all(l); 76 pcu_save_all(l);
77 77
78 // Can't use structure assignment if this is doing COMPAT_NETBSD32 78 // Can't use structure assignment if this is doing COMPAT_NETBSD32
79 const struct trapframe * const tf = l->l_md.md_utf; 79 const struct trapframe * const tf = l->l_md.md_utf;
80 for (size_t i = _X_RA; i <= _X_GP; i++) { 80 for (size_t i = _X_RA; i <= _X_GP; i++) {
81 cpustate.tf.tf_reg[i] = tf->tf_reg[i]; 81 cpustate.tf.tf_reg[i] = tf->tf_reg[i];
82 } 82 }
83 cpustate.tf.tf_pc = tf->tf_pc; 83 cpustate.tf.tf_pc = tf->tf_pc;
84 cpustate.tf.tf_badaddr = tf->tf_badaddr; 84 cpustate.tf.tf_tval = tf->tf_tval;
85 cpustate.tf.tf_cause = tf->tf_cause; 85 cpustate.tf.tf_cause = tf->tf_cause;
86 cpustate.tf.tf_sr = tf->tf_sr; 86 cpustate.tf.tf_sr = tf->tf_sr;
87 if (fpu_valid_p(l)) { 87 if (fpu_valid_p(l)) {
88 cpustate.fpregs = ((struct pcb *)lwp_getpcb(l))->pcb_fpregs; 88 cpustate.fpregs = ((struct pcb *)lwp_getpcb(l))->pcb_fpregs;
89 } else { 89 } else {
90 memset(&cpustate.fpregs, 0, sizeof(cpustate.fpregs)); 90 memset(&cpustate.fpregs, 0, sizeof(cpustate.fpregs));
91 } 91 }
92 CORE_SETMAGIC(cseg, CORESEGMAGIC, MID_MACHINE, CORE_CPU); 92 CORE_SETMAGIC(cseg, CORESEGMAGIC, MID_MACHINE, CORE_CPU);
93 cseg.c_addr = 0; 93 cseg.c_addr = 0;
94 cseg.c_size = chdr->c_cpusize; 94 cseg.c_size = chdr->c_cpusize;
95 95
96 MODULE_HOOK_CALL(coredump_write_hook, (iocookie, UIO_SYSSPACE, &cseg, 96 MODULE_HOOK_CALL(coredump_write_hook, (iocookie, UIO_SYSSPACE, &cseg,
97 chdr->c_seghdrsize), ENOSYS, error); 97 chdr->c_seghdrsize), ENOSYS, error);
cvs diff -r1.4 -r1.5 src/sys/arch/riscv/riscv/db_machdep.c (expand / switch to unified diff)

--- src/sys/arch/riscv/riscv/db_machdep.c 2020/03/14 16:12:16 1.4
+++ src/sys/arch/riscv/riscv/db_machdep.c 2020/11/04 06:56:56 1.5
@@ -19,27 +19,27 @@ @@ -19,27 +19,27 @@
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE. 27 * POSSIBILITY OF SUCH DAMAGE.
28 */ 28 */
29 29
30#include <sys/cdefs.h> 30#include <sys/cdefs.h>
31 31
32__RCSID("$NetBSD: db_machdep.c,v 1.4 2020/03/14 16:12:16 skrll Exp $"); 32__RCSID("$NetBSD: db_machdep.c,v 1.5 2020/11/04 06:56:56 skrll Exp $");
33 33
34#include <sys/param.h> 34#include <sys/param.h>
35 35
36#include <riscv/insn.h> 36#include <riscv/insn.h>
37#include <riscv/db_machdep.h> 37#include <riscv/db_machdep.h>
38 38
39#include <ddb/db_access.h> 39#include <ddb/db_access.h>
40#include <ddb/db_interface.h> 40#include <ddb/db_interface.h>
41#include <ddb/db_extern.h> 41#include <ddb/db_extern.h>
42#include <ddb/db_variables.h> 42#include <ddb/db_variables.h>
43 43
44int db_active = 0; 44int db_active = 0;
45 45
@@ -70,27 +70,27 @@ const struct db_variable db_regs[] = { @@ -70,27 +70,27 @@ const struct db_variable db_regs[] = {
70 { "a5", (void *)offsetof(struct trapframe, tf_a5), db_rw_ddbreg, NULL }, 70 { "a5", (void *)offsetof(struct trapframe, tf_a5), db_rw_ddbreg, NULL },
71 { "a6", (void *)offsetof(struct trapframe, tf_a6), db_rw_ddbreg, NULL }, 71 { "a6", (void *)offsetof(struct trapframe, tf_a6), db_rw_ddbreg, NULL },
72 { "a7", (void *)offsetof(struct trapframe, tf_a7), db_rw_ddbreg, NULL }, 72 { "a7", (void *)offsetof(struct trapframe, tf_a7), db_rw_ddbreg, NULL },
73 { "t0", (void *)offsetof(struct trapframe, tf_t0), db_rw_ddbreg, NULL }, 73 { "t0", (void *)offsetof(struct trapframe, tf_t0), db_rw_ddbreg, NULL },
74 { "t1", (void *)offsetof(struct trapframe, tf_t1), db_rw_ddbreg, NULL }, 74 { "t1", (void *)offsetof(struct trapframe, tf_t1), db_rw_ddbreg, NULL },
75 { "t2", (void *)offsetof(struct trapframe, tf_t2), db_rw_ddbreg, NULL }, 75 { "t2", (void *)offsetof(struct trapframe, tf_t2), db_rw_ddbreg, NULL },
76 { "t3", (void *)offsetof(struct trapframe, tf_t3), db_rw_ddbreg, NULL }, 76 { "t3", (void *)offsetof(struct trapframe, tf_t3), db_rw_ddbreg, NULL },
77 { "t4", (void *)offsetof(struct trapframe, tf_t4), db_rw_ddbreg, NULL }, 77 { "t4", (void *)offsetof(struct trapframe, tf_t4), db_rw_ddbreg, NULL },
78 { "t5", (void *)offsetof(struct trapframe, tf_t5), db_rw_ddbreg, NULL }, 78 { "t5", (void *)offsetof(struct trapframe, tf_t5), db_rw_ddbreg, NULL },
79 { "t6", (void *)offsetof(struct trapframe, tf_t6), db_rw_ddbreg, NULL }, 79 { "t6", (void *)offsetof(struct trapframe, tf_t6), db_rw_ddbreg, NULL },
80 { "pc", (void *)offsetof(struct trapframe, tf_pc), db_rw_ddbreg, NULL }, 80 { "pc", (void *)offsetof(struct trapframe, tf_pc), db_rw_ddbreg, NULL },
81 { "status", (void *)offsetof(struct trapframe, tf_sr), db_rw_ddbreg, "i" }, 81 { "status", (void *)offsetof(struct trapframe, tf_sr), db_rw_ddbreg, "i" },
82 { "cause", (void *)offsetof(struct trapframe, tf_cause), db_rw_ddbreg, "i" }, 82 { "cause", (void *)offsetof(struct trapframe, tf_cause), db_rw_ddbreg, "i" },
83 { "badaddr", (void *)offsetof(struct trapframe, tf_badaddr), db_rw_ddbreg, NULL }, 83 { "tval", (void *)offsetof(struct trapframe, tf_tval), db_rw_ddbreg, NULL },
84}; 84};
85const struct db_variable * const db_eregs = db_regs + __arraycount(db_regs); 85const struct db_variable * const db_eregs = db_regs + __arraycount(db_regs);
86 86
87int 87int
88db_rw_ddbreg(const struct db_variable *vp, db_expr_t *valp, int rw) 88db_rw_ddbreg(const struct db_variable *vp, db_expr_t *valp, int rw)
89{ 89{
90 struct trapframe * const tf = curcpu()->ci_ddb_regs; 90 struct trapframe * const tf = curcpu()->ci_ddb_regs;
91 KASSERT(db_regs <= vp && vp < db_regs + __arraycount(db_regs)); 91 KASSERT(db_regs <= vp && vp < db_regs + __arraycount(db_regs));
92 const uintptr_t addr = (uintptr_t)tf + (uintptr_t)vp->valuep; 92 const uintptr_t addr = (uintptr_t)tf + (uintptr_t)vp->valuep;
93 if (vp->modif != NULL && vp->modif[0] == 'i') { 93 if (vp->modif != NULL && vp->modif[0] == 'i') {
94 if (rw == DB_VAR_GET) { 94 if (rw == DB_VAR_GET) {
95 *valp = *(const uint32_t *)addr; 95 *valp = *(const uint32_t *)addr;
96 } else { 96 } else {
cvs diff -r1.7 -r1.8 src/sys/arch/riscv/riscv/genassym.cf (expand / switch to unified diff)

--- src/sys/arch/riscv/riscv/genassym.cf 2020/01/08 17:38:42 1.7
+++ src/sys/arch/riscv/riscv/genassym.cf 2020/11/04 06:56:56 1.8
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1# $NetBSD: genassym.cf,v 1.7 2020/01/08 17:38:42 ad Exp $ 1# $NetBSD: genassym.cf,v 1.8 2020/11/04 06:56:56 skrll Exp $
2#- 2#-
3# Copyright (c) 2014 The NetBSD Foundation, Inc. 3# Copyright (c) 2014 The NetBSD Foundation, Inc.
4# All rights reserved. 4# All rights reserved.
5# 5#
6# This code is derived from software contributed to The NetBSD Foundation 6# This code is derived from software contributed to The NetBSD Foundation
7# by Matt Thomas of 3am Software Foundry. 7# by Matt Thomas of 3am Software Foundry.
8# 8#
9# Redistribution and use in source and binary forms, with or without 9# Redistribution and use in source and binary forms, with or without
10# modification, are permitted provided that the following conditions 10# modification, are permitted provided that the following conditions
11# are met: 11# are met:
12# 1. Redistributions of source code must retain the above copyright 12# 1. Redistributions of source code must retain the above copyright
13# notice, this list of conditions and the following disclaimer. 13# notice, this list of conditions and the following disclaimer.
14# 2. Redistributions in binary form must reproduce the above copyright 14# 2. Redistributions in binary form must reproduce the above copyright
@@ -37,37 +37,38 @@ include  @@ -37,37 +37,38 @@ include
37include <sys/bitops.h> 37include <sys/bitops.h>
38include <sys/cpu.h> 38include <sys/cpu.h>
39include <sys/intr.h> 39include <sys/intr.h>
40include <sys/lwp.h> 40include <sys/lwp.h>
41include <sys/mutex.h> 41include <sys/mutex.h>
42include <sys/proc.h> 42include <sys/proc.h>
43include <sys/rwlock.h> 43include <sys/rwlock.h>
44 44
45include <uvm/uvm_extern.h> 45include <uvm/uvm_extern.h>
46 46
47include <riscv/locore.h> 47include <riscv/locore.h>
48include <riscv/sysreg.h> 48include <riscv/sysreg.h>
49 49
50define SR_IM SR_IM 50#define SR_IM SR_IM
51define SR_IM_LSHIFT __SIZEOF_LONG__ * 8 - (ilog2(SR_IM) + 1) 51#define SR_IM_LSHIFT __SIZEOF_LONG__ * 8 - (ilog2(SR_IM) + 1)
52define SR_IM_RSHIFT ilog2(__LOWEST_SET_BIT(SR_IM)) 52#define SR_IM_RSHIFT ilog2(__LOWEST_SET_BIT(SR_IM))
53define SR_VM SR_VM 53#define SR_VM SR_VM
54define SR_U64 SR_U64 54#define SR_U64 SR_U64
55define SR_S64 SR_S64 55#define SR_S64 SR_S64
56define SR_EF SR_EF 56#define SR_EF SR_EF
57define SR_PEI SR_PEI 57#define SR_PEI SR_PEI
58define SR_EI SR_EI 58#define SR_EI SR_EI
59define SR_PS SR_PS 59#define SR_PS SR_PS
60define SR_S SR_S 60#define SR_S SR_S
 61define SR_SIE SR_SIE
61 62
62define CAUSE_SYSCALL CAUSE_SYSCALL 63define CAUSE_SYSCALL CAUSE_SYSCALL
63 64
64define IPL_HIGH IPL_HIGH 65define IPL_HIGH IPL_HIGH
65define IPL_DDB IPL_DDB 66define IPL_DDB IPL_DDB
66define IPL_SCHED IPL_SCHED 67define IPL_SCHED IPL_SCHED
67define IPL_VM IPL_VM 68define IPL_VM IPL_VM
68define IPL_SOFTSERIAL IPL_SOFTSERIAL 69define IPL_SOFTSERIAL IPL_SOFTSERIAL
69define IPL_SOFTNET IPL_SOFTNET 70define IPL_SOFTNET IPL_SOFTNET
70define IPL_SOFTBIO IPL_SOFTBIO 71define IPL_SOFTBIO IPL_SOFTBIO
71define IPL_SOFTCLOCK IPL_SOFTCLOCK 72define IPL_SOFTCLOCK IPL_SOFTCLOCK
72define IPL_NONE IPL_NONE 73define IPL_NONE IPL_NONE
73 74
@@ -96,28 +97,28 @@ define TF_A3 offsetof(struct trapframe, @@ -96,28 +97,28 @@ define TF_A3 offsetof(struct trapframe,
96define TF_A4 offsetof(struct trapframe, tf_reg[_X_A4]) 97define TF_A4 offsetof(struct trapframe, tf_reg[_X_A4])
97define TF_A5 offsetof(struct trapframe, tf_reg[_X_A5]) 98define TF_A5 offsetof(struct trapframe, tf_reg[_X_A5])
98define TF_A6 offsetof(struct trapframe, tf_reg[_X_A6]) 99define TF_A6 offsetof(struct trapframe, tf_reg[_X_A6])
99define TF_A7 offsetof(struct trapframe, tf_reg[_X_A7]) 100define TF_A7 offsetof(struct trapframe, tf_reg[_X_A7])
100define TF_T0 offsetof(struct trapframe, tf_reg[_X_T0]) 101define TF_T0 offsetof(struct trapframe, tf_reg[_X_T0])
101define TF_T1 offsetof(struct trapframe, tf_reg[_X_T1]) 102define TF_T1 offsetof(struct trapframe, tf_reg[_X_T1])
102define TF_T2 offsetof(struct trapframe, tf_reg[_X_T2]) 103define TF_T2 offsetof(struct trapframe, tf_reg[_X_T2])
103define TF_T3 offsetof(struct trapframe, tf_reg[_X_T3]) 104define TF_T3 offsetof(struct trapframe, tf_reg[_X_T3])
104define TF_T4 offsetof(struct trapframe, tf_reg[_X_T4]) 105define TF_T4 offsetof(struct trapframe, tf_reg[_X_T4])
105define TF_T5 offsetof(struct trapframe, tf_reg[_X_T5]) 106define TF_T5 offsetof(struct trapframe, tf_reg[_X_T5])
106define TF_T6 offsetof(struct trapframe, tf_reg[_X_T6]) 107define TF_T6 offsetof(struct trapframe, tf_reg[_X_T6])
107define TF_GP offsetof(struct trapframe, tf_reg[_X_GP]) 108define TF_GP offsetof(struct trapframe, tf_reg[_X_GP])
108define TF_PC offsetof(struct trapframe, tf_pc) 109define TF_PC offsetof(struct trapframe, tf_pc)
109define TF_CAUSE offsetof(struct trapframe, tf_cause) 110define TF_SCAUSE offsetof(struct trapframe, tf_scause)
110define TF_BADADDR offsetof(struct trapframe, tf_badaddr) 111define TF_STVAL offsetof(struct trapframe, tf_stval)
111define TF_SR offsetof(struct trapframe, tf_sr) 112define TF_SR offsetof(struct trapframe, tf_sr)
112 113
113define L_CPU offsetof(struct lwp, l_cpu) 114define L_CPU offsetof(struct lwp, l_cpu)
114define L_MD_ASTPENDING offsetof(struct lwp, l_md.md_astpending) 115define L_MD_ASTPENDING offsetof(struct lwp, l_md.md_astpending)
115define L_MD_ONFAULT offsetof(struct lwp, l_md.md_onfault) 116define L_MD_ONFAULT offsetof(struct lwp, l_md.md_onfault)
116define L_MD_USP offsetof(struct lwp, l_md.md_usp) 117define L_MD_USP offsetof(struct lwp, l_md.md_usp)
117define L_MD_UTF offsetof(struct lwp, l_md.md_utf) 118define L_MD_UTF offsetof(struct lwp, l_md.md_utf)
118define L_MD_KTF offsetof(struct lwp, l_md.md_ktf) 119define L_MD_KTF offsetof(struct lwp, l_md.md_ktf)
119define L_PCB offsetof(struct lwp, l_addr) 120define L_PCB offsetof(struct lwp, l_addr)
120define L_PROC offsetof(struct lwp, l_proc) 121define L_PROC offsetof(struct lwp, l_proc)
121 122
122define P_MD_SYSCALL offsetof(struct proc, p_md.md_syscall) 123define P_MD_SYSCALL offsetof(struct proc, p_md.md_syscall)
123 124
cvs diff -r1.13 -r1.14 src/sys/arch/riscv/riscv/locore.S (expand / switch to unified diff)

--- src/sys/arch/riscv/riscv/locore.S 2020/10/31 15:18:09 1.13
+++ src/sys/arch/riscv/riscv/locore.S 2020/11/04 06:56:56 1.14
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: locore.S,v 1.13 2020/10/31 15:18:09 skrll Exp $ */ 1/* $NetBSD: locore.S,v 1.14 2020/11/04 06:56:56 skrll Exp $ */
2/*- 2/*-
3 * Copyright (c) 2014 The NetBSD Foundation, Inc. 3 * Copyright (c) 2014 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas of 3am Software Foundry. 7 * by Matt Thomas of 3am Software Foundry.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -30,30 +30,30 @@ @@ -30,30 +30,30 @@
30 30
31#include <machine/asm.h> 31#include <machine/asm.h>
32#include "assym.h" 32#include "assym.h"
33 33
34 .globl _C_LABEL(exception_userexit) 34 .globl _C_LABEL(exception_userexit)
35 .globl _C_LABEL(cpu_Debugger_insn) 35 .globl _C_LABEL(cpu_Debugger_insn)
36 36
37ENTRY_NP(start) 37ENTRY_NP(start)
38 // We get loaded and starting running at or near 0, not where we 38 // We get loaded and starting running at or near 0, not where we
39 // should be. We need to construct an initial PDETAB 39 // should be. We need to construct an initial PDETAB
40 40
41#ifdef _LP64 41#ifdef _LP64
42 li t0, SR_U64|SR_S64 42 li t0, SR_U64|SR_S64
43 li t1, SR_IM|SR_VM|SR_EI 43 li t1, SR_IM|SR_SIE
44 csrs sstatus, t0 44 csrs sstatus, t0
45#else 45#else
46 li t1, SR_IM|SR_VM|SR_U64|SR_S64|R_EI 46 li t1, SR_IM|SR_U64|SR_S64|SR_EI
47#endif 47#endif
48 csrc sstatus, t1 48 csrc sstatus, t1
49 49
50 li s11, VM_MAX_KERNEL_ADDRESS 50 li s11, VM_MAX_KERNEL_ADDRESS
51 li s10, PAGE_SIZE 51 li s10, PAGE_SIZE
52 li s9, USPACE 52 li s9, USPACE
53 53
54 /* 54 /*
55 * XXX XXX XXX: This is completely broken and wrong, we should map only 55 * XXX XXX XXX: This is completely broken and wrong, we should map only
56 * the kernel sections, and the direct map should be mapped later in C. 56 * the kernel sections, and the direct map should be mapped later in C.
57 */ 57 */
58#if 0 58#if 0
59#if 0 59#if 0
@@ -117,30 +117,26 @@ ENTRY_NP(start) @@ -117,30 +117,26 @@ ENTRY_NP(start)
117 srli a7, a7, (SEGSHIFT-PGSHIFT) // pages to segments 117 srli a7, a7, (SEGSHIFT-PGSHIFT) // pages to segments
118 li t3, NBSEG // load for ease 118 li t3, NBSEG // load for ease
119 119
120 // 120 //
121 // Fill in the PDEs to direct map memory. 121 // Fill in the PDEs to direct map memory.
122 // 122 //
123.Lfill: REG_S t4, 0(s3) // store PDE 123.Lfill: REG_S t4, 0(s3) // store PDE
124 add t4, t4, t3 // advance PA in PDE to next segment 124 add t4, t4, t3 // advance PA in PDE to next segment
125 add s3, s3, SZREG // advance to next PDE slot 125 add s3, s3, SZREG // advance to next PDE slot
126 addi a7, a7, -1 // count down segment 126 addi a7, a7, -1 // count down segment
127 bgtz a6, .Lfill // loop if more 127 bgtz a6, .Lfill // loop if more
128#endif 128#endif
129 129
130 csrw sptbr, s1 // set the page table base 
131 li t0, SR_VM 
132 csrs sstatus, t0 // Enable VM 
133 
134 // We should have a VM so let's start using our real addresses 130 // We should have a VM so let's start using our real addresses
135 lui t0, %hi(.Lmmu_on) // load hi part of absolute address 131 lui t0, %hi(.Lmmu_on) // load hi part of absolute address
136 jr t0, %lo(.Lmmu_on) // jump to absolute address 132 jr t0, %lo(.Lmmu_on) // jump to absolute address
137 133
138.Lmmu_on: 134.Lmmu_on:
139 // MMU is on! 135 // MMU is on!
140 csrw sscratch, zero // zero in sscratch to mark kernel 136 csrw sscratch, zero // zero in sscratch to mark kernel
141 137
142 PTR_LA tp, _C_LABEL(lwp0) // put curlwp in tp 138 PTR_LA tp, _C_LABEL(lwp0) // put curlwp in tp
143 139
144 PTR_LA a0, _C_LABEL(cpu_exception_handler) 140 PTR_LA a0, _C_LABEL(cpu_exception_handler)
145 csrw stvec, a0 141 csrw stvec, a0
146 142
@@ -175,27 +171,27 @@ ENTRY_NP(cpu_switchto) @@ -175,27 +171,27 @@ ENTRY_NP(cpu_switchto)
175 REG_S s4, TF_S4(sp) // save callee saved address 171 REG_S s4, TF_S4(sp) // save callee saved address
176 REG_S s5, TF_S5(sp) // save callee saved address 172 REG_S s5, TF_S5(sp) // save callee saved address
177 REG_S s6, TF_S6(sp) // save callee saved address 173 REG_S s6, TF_S6(sp) // save callee saved address
178 REG_S s7, TF_S7(sp) // save callee saved address 174 REG_S s7, TF_S7(sp) // save callee saved address
179 REG_S s8, TF_S8(sp) // save callee saved address 175 REG_S s8, TF_S8(sp) // save callee saved address
180 REG_S s9, TF_S9(sp) // save callee saved address 176 REG_S s9, TF_S9(sp) // save callee saved address
181 REG_S s10, TF_S10(sp) // save callee saved address 177 REG_S s10, TF_S10(sp) // save callee saved address
182 REG_S s11, TF_S11(sp) // save callee saved address 178 REG_S s11, TF_S11(sp) // save callee saved address
183 csrr t4, sstatus // get status for intr state 179 csrr t4, sstatus // get status for intr state
184 REG_S t4, TF_SR(sp) // save it 180 REG_S t4, TF_SR(sp) // save it
185 181
186 REG_S sp, L_MD_KTF(a0) // record trapframe pointer 182 REG_S sp, L_MD_KTF(a0) // record trapframe pointer
187 183
188 csrrci t0, sstatus, SR_EI // # disable interrupts 184 csrrci t0, sstatus, SR_SIE // # disable interrupts
189 185
190 mv tp, a1 // # put the new lwp in thread pointer 186 mv tp, a1 // # put the new lwp in thread pointer
191 187
192 PTR_L t1, L_CPU(tp) // # get curcpu 188 PTR_L t1, L_CPU(tp) // # get curcpu
193 PTR_S tp, CI_CURLWP(t1) // # update curcpu with the new curlwp 189 PTR_S tp, CI_CURLWP(t1) // # update curcpu with the new curlwp
194 190
195 REG_L sp, L_MD_KTF(tp) // # load its kernel stack pointer 191 REG_L sp, L_MD_KTF(tp) // # load its kernel stack pointer
196 REG_L t4, TF_SR(sp) // # fetch status register 192 REG_L t4, TF_SR(sp) // # fetch status register
197 csrw sstatus, t4 // # restore it (and interrupts?) 193 csrw sstatus, t4 // # restore it (and interrupts?)
198 194
199 REG_L s0, TF_S0(sp) // restore callee saved 195 REG_L s0, TF_S0(sp) // restore callee saved
200 REG_L s1, TF_S1(sp) // restore callee saved 196 REG_L s1, TF_S1(sp) // restore callee saved
201 REG_L s2, TF_S2(sp) // restore callee saved 197 REG_L s2, TF_S2(sp) // restore callee saved
@@ -264,48 +260,40 @@ ENTRY_NP(cpu_fast_switchto) @@ -264,48 +260,40 @@ ENTRY_NP(cpu_fast_switchto)
264 REG_S s5, TF_S5(sp) // save callee saved register 260 REG_S s5, TF_S5(sp) // save callee saved register
265 REG_S s6, TF_S6(sp) // save callee saved register 261 REG_S s6, TF_S6(sp) // save callee saved register
266 REG_S s7, TF_S7(sp) // save callee saved register 262 REG_S s7, TF_S7(sp) // save callee saved register
267 REG_S s8, TF_S8(sp) // save callee saved register 263 REG_S s8, TF_S8(sp) // save callee saved register
268 REG_S s9, TF_S9(sp) // save callee saved register 264 REG_S s9, TF_S9(sp) // save callee saved register
269 REG_S s10, TF_S10(sp) // save callee saved register 265 REG_S s10, TF_S10(sp) // save callee saved register
270 REG_S s11, TF_S11(sp) // save callee saved register 266 REG_S s11, TF_S11(sp) // save callee saved register
271 csrr t4, sstatus // get status register (for intr state) 267 csrr t4, sstatus // get status register (for intr state)
272 REG_S t4, TF_SR(sp) // save it 268 REG_S t4, TF_SR(sp) // save it
273 269
274 mv s0, tp // remember curlwp 270 mv s0, tp // remember curlwp
275 mv s1, sp // remember kernel stack 271 mv s1, sp // remember kernel stack
276 272
277#if 0 273 csrrci t0, sstatus, SR_SIE // disable interrupts
278 csrrci t0, sstatus, SR_EI // disable interrupts 
279#endif 
280 PTR_L t1, L_CPU(tp) // get curcpu() 274 PTR_L t1, L_CPU(tp) // get curcpu()
281 275
282 PTR_S sp, L_MD_KTF(tp) // save trapframe ptr in oldlwp 276 PTR_S sp, L_MD_KTF(tp) // save trapframe ptr in oldlwp
283 mv tp, a0 // set thread pointer to newlwp 277 mv tp, a0 // set thread pointer to newlwp
284 PTR_S tp, CI_CURLWP(t1) // update curlwp 278 PTR_S tp, CI_CURLWP(t1) // update curlwp
285 PTR_L sp, L_MD_KTF(tp) // switch to its stack 279 PTR_L sp, L_MD_KTF(tp) // switch to its stack
286#if 0 
287 csrw sstatus, t0 // reenable interrupts 280 csrw sstatus, t0 // reenable interrupts
288#endif 
289 call _C_LABEL(softint_dispatch) 281 call _C_LABEL(softint_dispatch)
290#if 0 282 csrrci t0, sstatus, SR_SIE // disable interrupts
291 csrrci t0, sstatus, SR_EI // disable interrupts 
292#endif 
293 PTR_L t1, L_CPU(tp) // get curcpu() again 283 PTR_L t1, L_CPU(tp) // get curcpu() again
294 mv tp, s0 // return to pinned lwp 284 mv tp, s0 // return to pinned lwp
295 PTR_S tp, CI_CURLWP(t1) // restore curlwp 285 PTR_S tp, CI_CURLWP(t1) // restore curlwp
296#if 0 
297 csrw sstatus, t0 // reeanble interrupts 286 csrw sstatus, t0 // reeanble interrupts
298#endif 
299 mv sp, s1 // restore stack pointer 287 mv sp, s1 // restore stack pointer
300 288
301 REG_L ra, (TF_RA + CALLFRAME_RA)(sp) // get return address 289 REG_L ra, (TF_RA + CALLFRAME_RA)(sp) // get return address
302 REG_L s0, TF_S0(sp) // restore register we used 290 REG_L s0, TF_S0(sp) // restore register we used
303 REG_L s1, TF_S1(sp) // restore register we used 291 REG_L s1, TF_S1(sp) // restore register we used
304 292
305 addi sp, sp, TF_LEN+CALLFRAME_SIZ // drop trapframe/callframe 293 addi sp, sp, TF_LEN+CALLFRAME_SIZ // drop trapframe/callframe
306 ret // return 294 ret // return
307END(cpu_fast_switchto) 295END(cpu_fast_switchto)
308 296
309// RISCV only has a simple exception handler handles both synchronous traps 297// RISCV only has a simple exception handler handles both synchronous traps
310// and interrupts. 298// and interrupts.
311ENTRY_NP(cpu_exception_handler) 299ENTRY_NP(cpu_exception_handler)
@@ -368,39 +356,39 @@ ENTRY_NP(cpu_exception_handler) @@ -368,39 +356,39 @@ ENTRY_NP(cpu_exception_handler)
368 mv a0, sp // trapframe pointer 356 mv a0, sp // trapframe pointer
369 csrr a1, sepc // get execption pc 357 csrr a1, sepc // get execption pc
370 csrr a2, sstatus // get status 358 csrr a2, sstatus // get status
371 csrr a3, scause // get cause 359 csrr a3, scause // get cause
372 360
373 REG_S a1, TF_PC(sp) 361 REG_S a1, TF_PC(sp)
374 INT_S a2, TF_SR(sp) 362 INT_S a2, TF_SR(sp)
375 INT_S a3, TF_CAUSE(sp) // save cause 363 INT_S a3, TF_CAUSE(sp) // save cause
376 364
377 // Now we've saved the trapfame, the cause is still in a3. 365 // Now we've saved the trapfame, the cause is still in a3.
378 366
379 bltz a3, intr_handler // MSB is set if interrupt 367 bltz a3, intr_handler // MSB is set if interrupt
380 368
381 // badaddr is only relavent for non-interrupts 369 // stval is only relavent for non-interrupts
382 csrr a4, sbadaddr // get badaddr 370 csrr a4, stval // get stval
383 REG_S a4, TF_BADADDR(sp) 371 REG_S a4, TF_TVAL(sp)
384 372
385 beqz t1, trap_user // this was a user trap 373 beqz t1, trap_user // this was a user trap
386 // This was a kernel exception 374 // This was a kernel exception
387 call _C_LABEL(cpu_trap) // just call trap to handle it 375 call _C_LABEL(cpu_trap) // just call trap to handle it
388exception_kernexit: 376exception_kernexit:
389 // If we got here, we are returning from a kernel exception (either a 377 // If we got here, we are returning from a kernel exception (either a
390 // trap or interrupt). Simply return the volatile registers and the 378 // trap or interrupt). Simply return the volatile registers and the
391 // exception PC and status, load the saved SP from the trapframe, and 379 // exception PC and status, load the saved SP from the trapframe, and
392 // return from the exception 380 // return from the exception
393 csrrci zero, sstatus, SR_EI // disable interrupts 381 csrrci zero, sstatus, SR_SIE // disable interrupts
394 382
395 REG_L ra, TF_RA(sp) // restore return address 383 REG_L ra, TF_RA(sp) // restore return address
396 REG_L gp, TF_GP(sp) // restore gp 384 REG_L gp, TF_GP(sp) // restore gp
397 REG_L a0, TF_A0(sp) // restore a0 385 REG_L a0, TF_A0(sp) // restore a0
398 REG_L a1, TF_A1(sp) // restore a1 386 REG_L a1, TF_A1(sp) // restore a1
399 REG_L a2, TF_A2(sp) // restore a2 387 REG_L a2, TF_A2(sp) // restore a2
400 REG_L a3, TF_A3(sp) // restore a3 388 REG_L a3, TF_A3(sp) // restore a3
401 REG_L a4, TF_A4(sp) // restore a4 389 REG_L a4, TF_A4(sp) // restore a4
402 REG_L a5, TF_A5(sp) // restore a5 390 REG_L a5, TF_A5(sp) // restore a5
403 REG_L a6, TF_A6(sp) // restore a6 391 REG_L a6, TF_A6(sp) // restore a6
404 REG_L a7, TF_A7(sp) // restore a7 392 REG_L a7, TF_A7(sp) // restore a7
405 REG_L t2, TF_T2(sp) // restore t2 393 REG_L t2, TF_T2(sp) // restore t2
406 REG_L t3, TF_T3(sp) // restore t3 394 REG_L t3, TF_T3(sp) // restore t3
@@ -423,36 +411,36 @@ trap_user: @@ -423,36 +411,36 @@ trap_user:
423 REG_S s0, TF_S0(sp) // only save from userland 411 REG_S s0, TF_S0(sp) // only save from userland
424 REG_S s1, TF_S1(sp) // only save from userland 412 REG_S s1, TF_S1(sp) // only save from userland
425 REG_S s2, TF_S2(sp) // only save from userland 413 REG_S s2, TF_S2(sp) // only save from userland
426 REG_S s3, TF_S3(sp) // only save from userland 414 REG_S s3, TF_S3(sp) // only save from userland
427 REG_S s4, TF_S4(sp) // only save from userland 415 REG_S s4, TF_S4(sp) // only save from userland
428 REG_S s5, TF_S5(sp) // only save from userland 416 REG_S s5, TF_S5(sp) // only save from userland
429 REG_S s6, TF_S6(sp) // only save from userland 417 REG_S s6, TF_S6(sp) // only save from userland
430 REG_S s7, TF_S7(sp) // only save from userland 418 REG_S s7, TF_S7(sp) // only save from userland
431 REG_S s8, TF_S8(sp) // only save from userland 419 REG_S s8, TF_S8(sp) // only save from userland
432 REG_S s9, TF_S9(sp) // only save from userland 420 REG_S s9, TF_S9(sp) // only save from userland
433 REG_S s10, TF_S10(sp) // only save from userland 421 REG_S s10, TF_S10(sp) // only save from userland
434 REG_S s11, TF_S11(sp) // only save from userland 422 REG_S s11, TF_S11(sp) // only save from userland
435 423
436 csrsi sstatus, SR_EI // reenable interrupts 424 csrsi sstatus, SR_SIE // reenable interrupts
437 425
438 li t0, CAUSE_SYSCALL // let's see if this was a syscall 426 li t0, CAUSE_SYSCALL // let's see if this was a syscall
439 beq a3, t0, trap_syscall // yes it was 427 beq a3, t0, trap_syscall // yes it was
440 428
441 call _C_LABEL(cpu_trap) // nope, just a regular trap 429 call _C_LABEL(cpu_trap) // nope, just a regular trap
442_C_LABEL(exception_userexit): 430_C_LABEL(exception_userexit):
443 INT_L t0, L_MD_ASTPENDING(tp) // ast pending? 431 INT_L t0, L_MD_ASTPENDING(tp) // ast pending?
444 bnez t0, trap_doast // yes, handle it. 432 bnez t0, trap_doast // yes, handle it.
445 csrrci zero, sstatus, SR_EI // disable interrupts 433 csrrci zero, sstatus, SR_SIE // disable interrupts
446 csrw sscratch, tp // show we are coming from userland 434 csrw sscratch, tp // show we are coming from userland
447 REG_L tp, TF_TP(sp) // only restore from userland 435 REG_L tp, TF_TP(sp) // only restore from userland
448 REG_L s0, TF_S0(sp) // only restore from userland 436 REG_L s0, TF_S0(sp) // only restore from userland
449 REG_L s1, TF_S1(sp) // only restore from userland 437 REG_L s1, TF_S1(sp) // only restore from userland
450 REG_L s2, TF_S2(sp) // only restore from userland 438 REG_L s2, TF_S2(sp) // only restore from userland
451 REG_L s3, TF_S3(sp) // only restore from userland 439 REG_L s3, TF_S3(sp) // only restore from userland
452 REG_L s4, TF_S4(sp) // only restore from userland 440 REG_L s4, TF_S4(sp) // only restore from userland
453 REG_L s5, TF_S5(sp) // only restore from userland 441 REG_L s5, TF_S5(sp) // only restore from userland
454 REG_L s6, TF_S6(sp) // only restore from userland 442 REG_L s6, TF_S6(sp) // only restore from userland
455 REG_L s7, TF_S7(sp) // only restore from userland 443 REG_L s7, TF_S7(sp) // only restore from userland
456 REG_L s8, TF_S8(sp) // only restore from userland 444 REG_L s8, TF_S8(sp) // only restore from userland
457 REG_L s9, TF_S9(sp) // only restore from userland 445 REG_L s9, TF_S9(sp) // only restore from userland
458 REG_L s10, TF_S10(sp) // only restore from userland 446 REG_L s10, TF_S10(sp) // only restore from userland
cvs diff -r1.10 -r1.11 src/sys/arch/riscv/riscv/trap.c (expand / switch to unified diff)

--- src/sys/arch/riscv/riscv/trap.c 2020/11/01 21:09:48 1.10
+++ src/sys/arch/riscv/riscv/trap.c 2020/11/04 06:56:56 1.11
@@ -22,27 +22,27 @@ @@ -22,27 +22,27 @@
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE. 27 * POSSIBILITY OF SUCH DAMAGE.
28 */ 28 */
29 29
30#include <sys/cdefs.h> 30#include <sys/cdefs.h>
31 31
32#define __PMAP_PRIVATE 32#define __PMAP_PRIVATE
33#define __UFETCHSTORE_PRIVATE 33#define __UFETCHSTORE_PRIVATE
34 34
35__RCSID("$NetBSD: trap.c,v 1.10 2020/11/01 21:09:48 skrll Exp $"); 35__RCSID("$NetBSD: trap.c,v 1.11 2020/11/04 06:56:56 skrll Exp $");
36 36
37#include <sys/param.h> 37#include <sys/param.h>
38#include <sys/systm.h> 38#include <sys/systm.h>
39#include <sys/atomic.h> 39#include <sys/atomic.h>
40 40
41#include <sys/signal.h> 41#include <sys/signal.h>
42#include <sys/signalvar.h> 42#include <sys/signalvar.h>
43#include <sys/siginfo.h> 43#include <sys/siginfo.h>
44 44
45#include <uvm/uvm.h> 45#include <uvm/uvm.h>
46 46
47#include <riscv/locore.h> 47#include <riscv/locore.h>
48 48
@@ -157,27 +157,27 @@ copyoutstr(const void *kaddr, void *uadd @@ -157,27 +157,27 @@ copyoutstr(const void *kaddr, void *uadd
157 return error; 157 return error;
158} 158}
159 159
160static void 160static void
161dump_trapframe(const struct trapframe *tf, void (*pr)(const char *, ...)) 161dump_trapframe(const struct trapframe *tf, void (*pr)(const char *, ...))
162{ 162{
163 const char *causestr = "?"; 163 const char *causestr = "?";
164 if (tf->tf_cause < __arraycount(causenames) 164 if (tf->tf_cause < __arraycount(causenames)
165 && causenames[tf->tf_cause] != NULL) 165 && causenames[tf->tf_cause] != NULL)
166 causestr = causenames[tf->tf_cause]; 166 causestr = causenames[tf->tf_cause];
167 (*pr)("Trapframe @ %p " 167 (*pr)("Trapframe @ %p "
168 "(cause=%d (%s), status=%#x, pc=%#16"PRIxREGISTER 168 "(cause=%d (%s), status=%#x, pc=%#16"PRIxREGISTER
169 ", va=%#"PRIxREGISTER"):\n", 169 ", va=%#"PRIxREGISTER"):\n",
170 tf, tf->tf_cause, causestr, tf->tf_sr, tf->tf_pc, tf->tf_badaddr); 170 tf, tf->tf_cause, causestr, tf->tf_sr, tf->tf_pc, tf->tf_tval);
171 (*pr)("ra=%#16"PRIxREGISTER", sp=%#16"PRIxREGISTER 171 (*pr)("ra=%#16"PRIxREGISTER", sp=%#16"PRIxREGISTER
172 ", gp=%#16"PRIxREGISTER", tp=%#16"PRIxREGISTER"\n", 172 ", gp=%#16"PRIxREGISTER", tp=%#16"PRIxREGISTER"\n",
173 tf->tf_ra, tf->tf_sp, tf->tf_gp, tf->tf_tp); 173 tf->tf_ra, tf->tf_sp, tf->tf_gp, tf->tf_tp);
174 (*pr)("s0=%#16"PRIxREGISTER", s1=%#16"PRIxREGISTER 174 (*pr)("s0=%#16"PRIxREGISTER", s1=%#16"PRIxREGISTER
175 ", s2=%#16"PRIxREGISTER", s3=%#16"PRIxREGISTER"\n", 175 ", s2=%#16"PRIxREGISTER", s3=%#16"PRIxREGISTER"\n",
176 tf->tf_s0, tf->tf_s1, tf->tf_s2, tf->tf_s3); 176 tf->tf_s0, tf->tf_s1, tf->tf_s2, tf->tf_s3);
177 (*pr)("s4=%#16"PRIxREGISTER", s5=%#16"PRIxREGISTER 177 (*pr)("s4=%#16"PRIxREGISTER", s5=%#16"PRIxREGISTER
178 ", s5=%#16"PRIxREGISTER", s3=%#16"PRIxREGISTER"\n", 178 ", s5=%#16"PRIxREGISTER", s3=%#16"PRIxREGISTER"\n",
179 tf->tf_s4, tf->tf_s5, tf->tf_s2, tf->tf_s3); 179 tf->tf_s4, tf->tf_s5, tf->tf_s2, tf->tf_s3);
180 (*pr)("s8=%#16"PRIxREGISTER", s9=%#16"PRIxREGISTER 180 (*pr)("s8=%#16"PRIxREGISTER", s9=%#16"PRIxREGISTER
181 ", s10=%#16"PRIxREGISTER", s11=%#16"PRIxREGISTER"\n", 181 ", s10=%#16"PRIxREGISTER", s11=%#16"PRIxREGISTER"\n",
182 tf->tf_s8, tf->tf_s9, tf->tf_s10, tf->tf_s11); 182 tf->tf_s8, tf->tf_s9, tf->tf_s10, tf->tf_s11);
183 (*pr)("a0=%#16"PRIxREGISTER", a1=%#16"PRIxREGISTER 183 (*pr)("a0=%#16"PRIxREGISTER", a1=%#16"PRIxREGISTER
@@ -271,30 +271,30 @@ trap_pagefault_fixup(struct trapframe *t @@ -271,30 +271,30 @@ trap_pagefault_fixup(struct trapframe *t
271 } while (opte != atomic_cas_pte(ptep, opte, npte)); 271 } while (opte != atomic_cas_pte(ptep, opte, npte));
272 272
273 pmap_page_set_attributes(VM_PAGE_TO_MD(pg), attr); 273 pmap_page_set_attributes(VM_PAGE_TO_MD(pg), attr);
274 pmap_tlb_update_addr(pmap, addr, npte, 0); 274 pmap_tlb_update_addr(pmap, addr, npte, 0);
275 275
276 if (attr & VM_PAGEMD_EXECPAGE) 276 if (attr & VM_PAGEMD_EXECPAGE)
277 pmap_md_page_syncicache(pg, curcpu()->ci_data.cpu_kcpuset); 277 pmap_md_page_syncicache(pg, curcpu()->ci_data.cpu_kcpuset);
278 278
279 return true; 279 return true;
280} 280}
281 281
282static bool 282static bool
283trap_pagefault(struct trapframe *tf, register_t epc, register_t status, 283trap_pagefault(struct trapframe *tf, register_t epc, register_t status,
284 register_t cause, register_t badaddr, bool usertrap_p, ksiginfo_t *ksi) 284 register_t cause, register_t tval, bool usertrap_p, ksiginfo_t *ksi)
285{ 285{
286 struct proc * const p = curlwp->l_proc; 286 struct proc * const p = curlwp->l_proc;
287 const intptr_t addr = trunc_page(badaddr); 287 const intptr_t addr = trunc_page(tval);
288 288
289 if (__predict_false(usertrap_p 289 if (__predict_false(usertrap_p
290 && (false 290 && (false
291 // Make this address is not trying to access kernel space. 291 // Make this address is not trying to access kernel space.
292 || addr < 0 292 || addr < 0
293#ifdef _LP64 293#ifdef _LP64
294 // If this is a process using a 32-bit address space, make 294 // If this is a process using a 32-bit address space, make
295 // sure the address is a signed 32-bit number. 295 // sure the address is a signed 32-bit number.
296 || ((p->p_flag & PK_32) && (int32_t) addr != addr) 296 || ((p->p_flag & PK_32) && (int32_t) addr != addr)
297#endif 297#endif
298 || false))) { 298 || false))) {
299 trap_ksi_init(ksi, SIGSEGV, SEGV_MAPERR, addr, cause); 299 trap_ksi_init(ksi, SIGSEGV, SEGV_MAPERR, addr, cause);
300 return false; 300 return false;
@@ -303,27 +303,27 @@ trap_pagefault(struct trapframe *tf, reg @@ -303,27 +303,27 @@ trap_pagefault(struct trapframe *tf, reg
303 struct vm_map * const map = (addr >= 0 ? &p->p_vmspace->vm_map : kernel_map); 303 struct vm_map * const map = (addr >= 0 ? &p->p_vmspace->vm_map : kernel_map);
304 304
305 // See if this fault is for reference/modified/execpage tracking 305 // See if this fault is for reference/modified/execpage tracking
306 if (trap_pagefault_fixup(tf, map->pmap, cause, addr)) 306 if (trap_pagefault_fixup(tf, map->pmap, cause, addr))
307 return true; 307 return true;
308 308
309 const vm_prot_t ftype = get_faulttype(cause); 309 const vm_prot_t ftype = get_faulttype(cause);
310 310
311 if (usertrap_p) { 311 if (usertrap_p) {
312 int error = uvm_fault(&p->p_vmspace->vm_map, addr, ftype); 312 int error = uvm_fault(&p->p_vmspace->vm_map, addr, ftype);
313 if (error) { 313 if (error) {
314 trap_ksi_init(ksi, SIGSEGV, 314 trap_ksi_init(ksi, SIGSEGV,
315 error == EACCES ? SEGV_ACCERR : SEGV_MAPERR, 315 error == EACCES ? SEGV_ACCERR : SEGV_MAPERR,
316 (intptr_t)badaddr, cause); 316 (intptr_t)tval, cause);
317 return false; 317 return false;
318 } 318 }
319 uvm_grow(p, addr); 319 uvm_grow(p, addr);
320 return true; 320 return true;
321 } 321 }
322 322
323 // Page fault are not allowed while dealing with interrupts 323 // Page fault are not allowed while dealing with interrupts
324 if (cpu_intr_p()) 324 if (cpu_intr_p())
325 return false; 325 return false;
326 326
327 struct faultbuf * const fb = cpu_disable_onfault(); 327 struct faultbuf * const fb = cpu_disable_onfault();
328 int error = uvm_fault(map, addr, ftype); 328 int error = uvm_fault(map, addr, ftype);
329 cpu_enable_onfault(fb); 329 cpu_enable_onfault(fb);
@@ -334,52 +334,52 @@ trap_pagefault(struct trapframe *tf, reg @@ -334,52 +334,52 @@ trap_pagefault(struct trapframe *tf, reg
334 return true; 334 return true;
335 } 335 }
336 336
337 if (fb == NULL) { 337 if (fb == NULL) {
338 return false; 338 return false;
339 } 339 }
340 340
341 cpu_jump_onfault(tf, fb); 341 cpu_jump_onfault(tf, fb);
342 return true; 342 return true;
343} 343}
344 344
345static bool 345static bool
346trap_instruction(struct trapframe *tf, register_t epc, register_t status, 346trap_instruction(struct trapframe *tf, register_t epc, register_t status,
347 register_t cause, register_t badaddr, bool usertrap_p, ksiginfo_t *ksi) 347 register_t cause, register_t tval, bool usertrap_p, ksiginfo_t *ksi)
348{ 348{
349 if (usertrap_p) { 349 if (usertrap_p) {
350 trap_ksi_init(ksi, SIGILL, ILL_ILLOPC, 350 trap_ksi_init(ksi, SIGILL, ILL_ILLOPC,
351 (intptr_t)badaddr, cause); 351 (intptr_t)tval, cause);
352 } 352 }
353 return false; 353 return false;
354} 354}
355 355
356static bool 356static bool
357trap_misalignment(struct trapframe *tf, register_t epc, register_t status, 357trap_misalignment(struct trapframe *tf, register_t epc, register_t status,
358 register_t cause, register_t badaddr, bool usertrap_p, ksiginfo_t *ksi) 358 register_t cause, register_t tval, bool usertrap_p, ksiginfo_t *ksi)
359{ 359{
360 if (usertrap_p) { 360 if (usertrap_p) {
361 trap_ksi_init(ksi, SIGBUS, BUS_ADRALN, 361 trap_ksi_init(ksi, SIGBUS, BUS_ADRALN,
362 (intptr_t)badaddr, cause); 362 (intptr_t)tval, cause);
363 } 363 }
364 return false; 364 return false;
365} 365}
366 366
367void 367void
368cpu_trap(struct trapframe *tf, register_t epc, register_t status, 368cpu_trap(struct trapframe *tf, register_t epc, register_t status,
369 register_t cause, register_t badaddr) 369 register_t cause, register_t tval)
370{ 370{
371 const u_int fault_mask = 1U << cause; 371 const u_int fault_mask = 1U << cause;
372 const intptr_t addr = badaddr; 372 const intptr_t addr = tval;
373 const bool usertrap_p = (status & SR_PS) == 0; 373 const bool usertrap_p = (status & SR_PS) == 0;
374 bool ok = true; 374 bool ok = true;
375 ksiginfo_t ksi; 375 ksiginfo_t ksi;
376 376
377 if (__predict_true(fault_mask & FAULT_TRAP_MASK)) { 377 if (__predict_true(fault_mask & FAULT_TRAP_MASK)) {
378#ifndef _LP64 378#ifndef _LP64
379 // This fault may be cause the kernel's page table got a new 379 // This fault may be cause the kernel's page table got a new
380 // page table page and this pmap's page table doesn't know 380 // page table page and this pmap's page table doesn't know
381 // about it. See 381 // about it. See
382 struct pmap * const pmap = curlwp->l_proc->p_vmspace->vm_map.pmap; 382 struct pmap * const pmap = curlwp->l_proc->p_vmspace->vm_map.pmap;
383 if ((intptr_t) addr < 0 383 if ((intptr_t) addr < 0
384 && pmap != pmap_kernel() 384 && pmap != pmap_kernel()
385 && pmap_pdetab_fixup(pmap, addr)) { 385 && pmap_pdetab_fixup(pmap, addr)) {