Wed Nov 4 07:40:15 2020 UTC ()
typo in comment


(skrll)
diff -r1.3 -r1.4 src/sys/arch/riscv/include/reg.h
cvs diff -r1.3 -r1.4 src/sys/arch/riscv/include/reg.h (expand / switch to unified diff)

--- src/sys/arch/riscv/include/reg.h 2020/11/04 06:24:44 1.3
+++ src/sys/arch/riscv/include/reg.h 2020/11/04 07:40:15 1.4
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: reg.h,v 1.3 2020/11/04 06:24:44 skrll Exp $ */ 1/* $NetBSD: reg.h,v 1.4 2020/11/04 07:40:15 skrll Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas of 3am Software Foundry. 8 * by Matt Thomas of 3am Software Foundry.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -32,27 +32,27 @@ @@ -32,27 +32,27 @@
32#ifndef _RISCV_REG_H_ 32#ifndef _RISCV_REG_H_
33#define _RISCV_REG_H_ 33#define _RISCV_REG_H_
34 34
35// x0 = 0 35// x0 = 0
36// x1 = ra (return address) 36// x1 = ra (return address)
37// x2 = sp (stack pointer) 37// x2 = sp (stack pointer)
38// x3 = gp (global pointer) 38// x3 = gp (global pointer)
39// x4 = tp (thread pointer) 39// x4 = tp (thread pointer)
40// x5-x7 = t0-t2 (temporary) 40// x5-x7 = t0-t2 (temporary)
41// x8 = s0/fp (saved register / frame pointer) 41// x8 = s0/fp (saved register / frame pointer)
42// x9 = s1 (saved register) 42// x9 = s1 (saved register)
43// x10-x11 = a0-a1 (arguments/return values) 43// x10-x11 = a0-a1 (arguments/return values)
44// x12-x17 = a2-a7 (arguments) 44// x12-x17 = a2-a7 (arguments)
45// x18-r27 = s2-s11 (saved registers) 45// x18-x27 = s2-s11 (saved registers)
46// x28-x31 = t3-r6 (temporaries) 46// x28-x31 = t3-r6 (temporaries)
47 47
48struct reg { // synced with register_t in <riscv/types.h> 48struct reg { // synced with register_t in <riscv/types.h>
49#ifdef _LP64 49#ifdef _LP64
50 __uint64_t r_reg[31]; /* x0 is always 0 */ 50 __uint64_t r_reg[31]; /* x0 is always 0 */
51 __uint64_t r_pc; 51 __uint64_t r_pc;
52#else 52#else
53 __uint32_t r_reg[31]; /* x0 is always 0 */ 53 __uint32_t r_reg[31]; /* x0 is always 0 */
54 __uint32_t r_pc; 54 __uint32_t r_pc;
55#endif 55#endif
56}; 56};
57 57
58#ifdef _LP64 58#ifdef _LP64