 @@ -1,14 +1,14 @@
-/*	$NetBSD: ofw_irq.S,v 1.16 2020/11/21 09:36:27 skrll Exp $	*/
+/*	$NetBSD: ofw_irq.S,v 1.17 2020/11/21 19:57:35 skrll Exp $	*/
 /*
  * Copyright (c) 1994-1998 Mark Brinicombe.
  * Copyright (c) 1994 Brini.
  * All rights reserved.
+ *
  * This code is derived from software written for Brini by Mark Brinicombe
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -85,32 +85,33 @@ Lirq_entry:
 	.word	irq_entry
 Lofwirqstk:			/* hack */
 	.word	ofwirqstk + 4096
 LOCK_CAS_CHECK_LOCALS
 AST_ALIGNMENT_FAULT_LOCALS
 /*
  * Regsister usage
+ *
  *  r4	- Address of cpu_info (on entry)
- *  r5  - Pointer to handler pointer list
+ *  r5  - Address of curlwp
  *  r6  - Address of current handler
  *  r7  - pspr mode (must be preserved)
  *  r8  - Current IRQ requests.
  *  r9  - Used to count through possible IRQ bits.
  *  r10 - Base address of IOMD
  *  r11  - Pointer to handler pointer list
  */
 ASENTRY_NP(irq_entry)
 	/*
 	 *  We come here following an OFW-handled timer tick.
+	 *
  	 *  We are in the SVC frame, and interrupts are disabled.
  	 *  The state of the interrupted context is partially in
  	 *  the registers and partially in the global storage area
  	 *  labeled ofw_ticktmp.  ofw_ticktmp is filled-in by the
  	 *  tick callback that is invoked by OFW on the way out of
  	 *  its interrupt handler.  ofw_ticktmp contains the following:
+ 	 *
 @@ -178,27 +179,27 @@ ASENTRY_NP(irq_entry)
 	movs	pc, lr			/* Exit */
  	/*
  	 *  Stuff a bit-mask into r8 indicating which interrupts
  	 *  are pending.  In our case, that is just the timer0
  	 *  interrupt:  (1 << TIMER0).  The existing code will take
  	 *  care of invoking that handler and the softint/ast stuff
  	 *  which follows it.
 	 */
 ofwtakeint:
 #ifdef EXEC_AOUT
 	ldr	r0, [sp]		/* Fetch SPSR */
 #endif
-	ENABLE_ALIGNMENT_FAULTS
+	ENABLE_ALIGNMENT_FAULTS		/* puts cur{cpu,lwp} in r4/r5 */
 	mov	r8, #0x00000001		/* timer interrupt pending! */
 	mov	r8, r8, lsl #IRQ_TIMER0
 	/*
 	 * Note that we have entered the IRQ handler.
 	 * We are in SVC mode so we cannot use the processor mode
 	 * to determine if we are in an IRQ. Instead we will count the
 	 * each time the interrupt handler is nested.
 	 */
 	ldr	r1, [r4, #CI_INTR_DEPTH]
 	add	r1, r1, #1
 @@ -214,63 +215,63 @@ ofwtakeint:
  	 * Need to block all interrupts at the IPL or lower for
 	 * all asserted interrupts.
 	 * This basically emulates hardware interrupt priority levels.
 	 * Means we need to go through the interrupt mask and for
 	 * every asserted interrupt we need to mask out all other
 	 * interrupts at the same or lower IPL.
 	 * If only we could wait until the main loop but we need to sort
 	 * this out first so interrupts can be re-enabled.
+	 *
 	 * This would benefit from a special ffs type routine
 	 */
 	mov	r9, #(NIPL - 1)
-	ldr	r5, Lspl_masks
+	ldr	r11, Lspl_masks
 Lfind_highest_ipl:
-	ldr	r2, [r5, r9, lsl #2]
+	ldr	r2, [r11, r9, lsl #2]
 	tst	r8, r2
 	subeq	r9, r9, #1
 	beq	Lfind_highest_ipl
 	/* r9 = SPL level of highest priority interrupt */
 	add	r9, r9, #1
-	ldr	r2, [r5, r9, lsl #2]
+	ldr	r2, [r11, r9, lsl #2]
 	mvn	r2, r2
 	orr	r0, r0, r2
 	str	r0, [r1]
 	ldr	r0, Lcurrent_spl_level
 	ldr	r1, [r4, #CI_CPL]
 	str	r9, [r4, #CI_CPL]
 	stmfd	sp!, {r1}
 	/* Update the irq masks */
 	bl	_C_LABEL(irq_setmasks)
 	mrs     r0, cpsr		/* Enable IRQ's */
 	bic	r0, r0, #I32_bit
 	msr	cpsr_all, r0
-	ldr	r5, Lirqhandlers
+	ldr	r11, Lirqhandlers
 	mov	r9, #0x00000001
 irqloop:
 	/* This would benefit from a special ffs type routine */
 	tst	r8, r9			/* Is a bit set ? */
 	beq	nextirq			/* No ? try next bit */
-	ldr	r6, [r5]		/* Get address of first handler structure */
+	ldr	r6, [r11]		/* Get address of first handler structure */
 	teq	r6, #0x00000000		/* Do we have a handler */
 	moveq	r0, r8			/* IRQ requests as arg 0 */
 	beq	_C_LABEL(stray_irqhandler) /* call special handler */
 	ldr	r1, [r4, #(CI_CC_NINTR)]
 	ldr	r2, [r4, #(CI_CC_NINTR+4)]
 #ifdef _ARMEL
 	adds	r1, r1, #0x00000001
 	adc	r2, r2, #0x00000000
 #else
 	adds	r2, r2, #0x00000001
 	adc	r1, r1, #0x00000000
 @@ -291,42 +292,40 @@ irqchainloop:
 	ldr	r6, [r6, #(IH_NEXT)]
 	teq	r6, #0x00000000
 	bne	irqchainloop
 	b	nextirq
 irqdone:
 	add	r3, r6, #IH_EV_COUNT	/* get address of ih's ev_count */
 	ldmia   r3, {r1-r2}		/* load ev_count */
 	adds	r1, r1, #0x00000001	/* 64bit incr (lo) */
 	adc     r2, r2, #0x00000000	/* 64bit incr (hi) */
 	stmia   r3, {r1-r2}		/* store ev_count */
 nextirq:
-	add	r5, r5, #0x00000004	/* update pointer to handlers */
+	add	r11, r11, #0x00000004	/* update pointer to handlers */
 	mov	r9, r9, lsl #1		/* move on to next bit */
 	teq	r9, #(1 << 24)		/* done the last bit ? */
 	bne	irqloop			/* no - loop back. */
 	ldmfd	sp!, {r2}
 	str	r2, [r4, #CI_CPL]
 	/* Restore previous disabled mask */
 	ldmfd	sp!, {r2}
 	ldr	r1, Ldisabled_mask
 	str	r2, [r1]
 	bl	_C_LABEL(irq_setmasks)
 	bl	_C_LABEL(dosoftints)	/* Handle the soft interrupts */
 	/* Kill IRQ's in preparation for exit */
 	mrs     r0, cpsr
 	orr     r0, r0, #(I32_bit)
 	msr     cpsr_all, r0
 	/* Decrement the nest count */
 	ldr	r1, [r4, #CI_INTR_DEPTH]
 	sub	r1, r1, #1
 	str	r1, [r4, #CI_INTR_DEPTH]
 	LOCK_CAS_CHECK
 	DO_AST_AND_RESTORE_ALIGNMENT_FAULTS