 @@ -1,559 +1,646 @@
-/*	$NetBSD: netbsd32_machdep.c,v 1.7.2.1 2020/05/02 16:26:04 martin Exp $	*/
+/*	$NetBSD: netbsd32_machdep.c,v 1.7.2.2 2021/01/01 12:58:35 martin Exp $	*/
 /*
  * Copyright (c) 2018 Ryo Shimizu <ryo@nerv.org>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.7.2.1 2020/05/02 16:26:04 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.7.2.2 2021/01/01 12:58:35 martin Exp $");
 #if defined(_KERNEL_OPT)
 #include "opt_compat_netbsd.h"
 #endif
 #include <sys/param.h>
 #include <sys/core.h>
 #include <sys/exec.h>
 #include <sys/lwp.h>
 #include <sys/ptrace.h>
 #include <sys/ras.h>
 #include <sys/signalvar.h>
 #include <sys/syscallargs.h>
 #include <uvm/uvm_extern.h>
 #include <compat/netbsd32/netbsd32.h>
 #include <compat/netbsd32/netbsd32_exec.h>
 #include <compat/netbsd32/netbsd32_syscallargs.h>
 #include <aarch64/armreg.h>
 #include <aarch64/cpufunc.h>
 #include <aarch64/frame.h>
 #include <aarch64/machdep.h>
 #include <aarch64/userret.h>
 const char machine32[] = MACHINE;
 #ifdef __AARCH64EB__
 const char machine_arch32[] = "earmv7hfeb";
 #else
 const char machine_arch32[] = "earmv7hf";
 #endif
 void
 netbsd32_setregs(struct lwp *l, struct exec_package *pack, vaddr_t stack)
+{
 	struct proc * const p = l->l_proc;
 	struct trapframe * const tf = l->l_md.md_utf;
 	p->p_flag |= PK_32;
 	/*
 	 * void __start(struct ps_strings *ps_strings, const Obj_Entry *obj,
 	 *     void (*cleanup)(void));
 	 */
 	memset(tf, 0, sizeof(*tf));
 	tf->tf_reg[0] = (uint32_t)p->p_psstrp;
 	tf->tf_reg[12] = stack;		/* r12 needed by pre 1.4 crt0.c */
 	tf->tf_reg[13] = stack;		/* sp */
 	tf->tf_reg[14] = pack->ep_entry;/* lr */
 	tf->tf_reg[18] = 0x77777777;	/* svc_lr. adjust to arm_machdep.c */
 	tf->tf_pc = pack->ep_entry;
 	/* set 32bit mode, and same endian as 64bit's */
 #ifdef __AARCH64EB__
 	tf->tf_spsr = SPSR_M_USR32 | SPSR_A32_E;
 #else
 	tf->tf_spsr = SPSR_M_USR32;
 #endif
 	/* THUMB CODE? */
 	if (pack->ep_entry & 1)
 		tf->tf_spsr |= SPSR_A32_T;
+}
 int
 netbsd32_ptrace_translate_request(int req)
+{
 	switch (req) {
 	case 0 ... PT_FIRSTMACH - 1:
 		return req;
 	case PT32_GETREGS:
 		return PT_GETREGS;
 	case PT32_SETREGS:
 		return PT_SETREGS;
 	case PT32_GETFPREGS:
 		return PT_GETFPREGS;
 	case PT32_SETFPREGS:
 		return PT_SETFPREGS;
 	/* not implemented for arm32 */
 	case PT32_STEP:
 	case PT32_SETSTEP:
 	case PT32_CLEARSTEP:
 	default:
 		return -1;
+	}
+}
 /* aarch32 fpscr register is assigned to two registers fpsr/fpcr on aarch64 */
 #define FPSR_BITS							\
 	(FPSR_N32|FPSR_Z32|FPSR_C32|FPSR_V32|FPSR_QC|			\
 	 FPSR_IDC|FPSR_IXC|FPSR_UFC|FPSR_OFC|FPSR_DZC|FPSR_IOC)
 #define FPCR_BITS							\
 	(FPCR_AHP|FPCR_DN|FPCR_FZ|FPCR_RMODE|FPCR_STRIDE|FPCR_LEN|	\
 	 FPCR_IDE|FPCR_IXE|FPCR_UFE|FPCR_OFE|FPCR_DZE|FPCR_IOE)
-static int
+int
 netbsd32_process_read_regs(struct lwp *l, struct reg32 *regs)
+{
 	struct proc * const p = l->l_proc;
 	struct trapframe *tf = l->l_md.md_utf;
 	int i;
 	if ((p->p_flag & PK_32) == 0)
 		return EINVAL;
 	for (i = 0; i < 13; i++)
 		regs->r[i] = tf->tf_reg[i];	/* r0-r12 */
 	regs->r_sp = tf->tf_reg[13];		/* r13 = sp */
 	regs->r_lr = tf->tf_reg[14];		/* r14 = lr */
 	regs->r_pc = tf->tf_pc;			/* r15 = pc */
 	regs->r_cpsr = tf->tf_spsr;
 	/* THUMB CODE? */
 	if (tf->tf_spsr & SPSR_A32_T)
 		regs->r_pc |= 1;
 	return 0;
+}
-static int
+int
 netbsd32_process_read_fpregs(struct lwp *l, struct fpreg32 *fpregs,
     size_t *lenp)
+{
 	struct proc * const p = l->l_proc;
 	struct pcb * const pcb = lwp_getpcb(l);
 	int i;
 	if ((p->p_flag & PK_32) == 0)
 		return EINVAL;
 	KASSERT(*lenp <= sizeof(*fpregs));
 	fpu_save(l);
 	/*
 	 * convert from aarch64's struct fpreg to arm's struct fpreg32
 	 */
 #define VFP_FPEXC_EN		0x40000000	/* VFP Enable bit */
 #define VFP_FPEXC_VECITR	0x00000700	/* VECtor ITeRation count */
 	fpregs->fpr_vfp.vfp_fpexc = VFP_FPEXC_EN | VFP_FPEXC_VECITR;
 	fpregs->fpr_vfp.vfp_fpscr =
 	    (pcb->pcb_fpregs.fpsr & FPSR_BITS) |
 	    (pcb->pcb_fpregs.fpcr & FPCR_BITS);
 	fpregs->fpr_vfp.vfp_fpinst = 0;
 	fpregs->fpr_vfp.vfp_fpinst2 = 0;
 	for (i = 0; i < 32; i++) {
 #ifdef __AARCH64EB__
 		fpregs->fpr_vfp.vfp_regs[i] = pcb->pcb_fpregs.fp_reg[i].u64[1];
 #else
 		fpregs->fpr_vfp.vfp_regs[i] = pcb->pcb_fpregs.fp_reg[i].u64[0];
 #endif
+	}
 	return 0;
+}
 int
 netbsd32_process_write_regs(struct lwp *l, const struct reg32 *regs)
+{
 	struct proc * const p = l->l_proc;
 	struct trapframe *tf = l->l_md.md_utf;
 	int i;
 	if ((p->p_flag & PK_32) == 0)
 		return EINVAL;
 	if (regs->r_pc >= VM_MAXUSER_ADDRESS32 ||
 	    regs->r_sp >= VM_MAXUSER_ADDRESS32)
 		return EINVAL;
 	for (i = 0; i < 13; i++)
 		tf->tf_reg[i] = regs->r[i];	/* r0-r12 */
 	tf->tf_reg[13] = regs->r_sp;		/* r13 = sp */
 	tf->tf_reg[14] = regs->r_lr;		/* r14 = lr */
 	tf->tf_pc = regs->r_pc;			/* r15 = pc */
 	tf->tf_spsr &= ~(SPSR_NZCV | SPSR_A32_T);
 	tf->tf_spsr |= regs->r_cpsr & (SPSR_NZCV | SPSR_A32_T);
 	/* THUMB CODE? */
 	if (regs->r_pc & 1)
 		tf->tf_spsr |= SPSR_A32_T;
 	return 0;
+}
 int
 netbsd32_process_write_fpregs(struct lwp *l, const struct fpreg32 *fpregs,
     size_t len)
+{
 	struct proc * const p = l->l_proc;
 	struct pcb * const pcb = lwp_getpcb(l);
 	int i;
 	if ((p->p_flag & PK_32) == 0)
 		return EINVAL;
 	KASSERT(len <= sizeof(*fpregs));
 	fpu_discard(l, true);		// set used flag
 	pcb->pcb_fpregs.fpsr = fpregs->fpr_vfp.vfp_fpscr & FPSR_BITS;
 	pcb->pcb_fpregs.fpcr = fpregs->fpr_vfp.vfp_fpscr & FPCR_BITS;
 	CTASSERT(__arraycount(fpregs->fpr_vfp.vfp_regs) ==
 	    __arraycount(pcb->pcb_fpregs.fp_reg) + 1);
 	for (i = 0; i < __arraycount(pcb->pcb_fpregs.fp_reg); i++) {
 #ifdef __AARCH64EB__
 		pcb->pcb_fpregs.fp_reg[i].u64[0] = 0;
 		pcb->pcb_fpregs.fp_reg[i].u64[1] =
 #else
 		pcb->pcb_fpregs.fp_reg[i].u64[1] = 0;
 		pcb->pcb_fpregs.fp_reg[i].u64[0] =
 #endif
 		    fpregs->fpr_vfp.vfp_regs[i];
+	}
 	return 0;
+}
 int
 cpu_coredump32(struct lwp *l, struct coredump_iostate *iocookie,
     struct core32 *chdr)
+{
 	struct netbsd32_cpustate md_core32;
 	struct coreseg32 cseg;
 	int error;
 	if (iocookie == NULL) {
 		CORE_SETMAGIC(*chdr, COREMAGIC, MID_ARM6, 0);
 		chdr->c_hdrsize = ALIGN32(sizeof(*chdr));
 		chdr->c_seghdrsize = ALIGN32(sizeof(cseg));
 		chdr->c_cpusize = sizeof(md_core32);
 		chdr->c_nseg++;
 		return 0;
+	}
 	error = netbsd32_process_read_regs(l, &md_core32.regs);
 	if (error)
 		return error;
 	error = netbsd32_process_read_fpregs(l, &md_core32.fpregs, NULL);
 	if (error)
 		return error;
 	CORE_SETMAGIC(cseg, CORESEGMAGIC, MID_ARM6, CORE_CPU);
 	cseg.c_addr = 0;
 	cseg.c_size = chdr->c_cpusize;
 	error = coredump_write(iocookie, UIO_SYSSPACE,
 	    &cseg, chdr->c_seghdrsize);
 	if (error)
 		return error;
 	return coredump_write(iocookie, UIO_SYSSPACE,
 	    &md_core32, sizeof(md_core32));
+}
 static void
 netbsd32_sendsig_siginfo(const ksiginfo_t *ksi, const sigset_t *mask)
+{
 	struct lwp * const l = curlwp;
 	struct proc * const p = l->l_proc;
 	struct trapframe * const tf = l->l_md.md_utf;
 	struct sigaltstack * const ss = &l->l_sigstk;
 	const int signo = ksi->ksi_signo;
 	const struct sigaction * const sa = &SIGACTION(p, signo);
 	const struct sigact_sigdesc * const sdesc =
 	    &p->p_sigacts->sa_sigdesc[signo];
 	const sig_t handler = sa->sa_handler;
 	struct netbsd32_sigframe_siginfo *fp, frame;
 	int error;
 	const bool onstack_p =
 	    (ss->ss_flags & (SS_DISABLE | SS_ONSTACK)) == 0 &&
 	    (sa->sa_flags & SA_ONSTACK);
 	vaddr_t sp = onstack_p ?
 	    ((vaddr_t)ss->ss_sp + ss->ss_size) :
 	    tf->tf_reg[13];	/* r13 = sp on aarch32 */
 	fp = (struct netbsd32_sigframe_siginfo *)sp;
 	fp = (struct netbsd32_sigframe_siginfo *)STACK_ALIGN(fp - 1, (8 - 1));
 	memset(&frame, 0, sizeof(frame));
 	/* XXX: netbsd32_ksi_to_si32 */
 	netbsd32_si_to_si32(&frame.sf_si, (const siginfo_t *)&ksi->ksi_info);
 	frame.sf_uc.uc_flags = _UC_SIGMASK;
 	frame.sf_uc.uc_sigmask = *mask;
 	frame.sf_uc.uc_link = (uint32_t)(uintptr_t)l->l_ctxlink;
 	frame.sf_uc.uc_flags |= (l->l_sigstk.ss_flags & SS_ONSTACK) ?
 	    _UC_SETSTACK : _UC_CLRSTACK;
 	sendsig_reset(l, signo);
 	mutex_exit(p->p_lock);
 	cpu_getmcontext32(l, &frame.sf_uc.uc_mcontext, &frame.sf_uc.uc_flags);
 	error = copyout(&frame, fp, sizeof(frame));
 	mutex_enter(p->p_lock);
 	if (error != 0) {
 		/*
 		 * Process has trashed its stack;
 		 * give it an illegal instruction to halt it in its tracks.
 		 */
 		sigexit(l, SIGILL);
 		/* NOTREACHED */
+	}
 	tf->tf_reg[0] = signo;
 	tf->tf_reg[1] = (uint32_t)(uintptr_t)&fp->sf_si;
 	tf->tf_reg[2] = (uint32_t)(uintptr_t)&fp->sf_uc;
 	/* the trampoline uses r5 as the uc address */
 	tf->tf_reg[5] = (uint32_t)(uintptr_t)&fp->sf_uc;
 	tf->tf_pc = (uint32_t)(uintptr_t)handler;
 	/* THUMB CODE? */
 	if (((uintptr_t)handler) & 1)
 		tf->tf_spsr |= SPSR_A32_T;
 	else
 		tf->tf_spsr &= ~SPSR_A32_T;
 	tf->tf_reg[13] = (uint32_t)(uintptr_t)fp;		/* sp */
 	tf->tf_reg[14] = (uint32_t)(uintptr_t)sdesc->sd_tramp;	/* lr */
 	/* Remember if we'ere now on the signal stack */
 	if (onstack_p)
 		ss->ss_flags |= SS_ONSTACK;
+}
 void
 netbsd32_sendsig(const ksiginfo_t *ksi, const sigset_t *mask)
+{
 #ifdef COMPAT_16
 #error non EABI generation binaries are not supported
 	if (curproc->p_sigacts->sa_sigdesc[ksi->ksi_signo].sd_vers < 2)
 		netbsd32_sendsig_sigcontext(ksi, mask);
 	else
 #endif
 		netbsd32_sendsig_siginfo(ksi, mask);
+}
 void
 startlwp32(void *arg)
+{
 	ucontext32_t *uc = arg;
 	lwp_t *l = curlwp;
 	int error __diagused;
 	/*
 	 * entity of *uc is ucontext_t. therefore
 	 * ucontext_t must be greater than ucontext32_t
 	 */
 	CTASSERT(sizeof(ucontext_t) >= sizeof(ucontext32_t));
 	error = cpu_setmcontext32(l, &uc->uc_mcontext, uc->uc_flags);
 	KASSERT(error == 0);
 	/* Note: we are freeing ucontext_t, not ucontext32_t. */
 	kmem_free(uc, sizeof(ucontext_t));
 	userret(l);
+}
 int
 cpu_mcontext32_validate(struct lwp *l, const mcontext32_t *mcp)
+{
 	struct proc * const p __diagused = l->l_proc;
 	const uint32_t spsr = mcp->__gregs[_REG_CPSR];
 	KASSERT(p->p_flag & PK_32);
 	if (__SHIFTOUT(spsr, SPSR_M) != SPSR_M_USR32)
 		return EINVAL;
 	if ((spsr & (SPSR_A64_D|SPSR_A|SPSR_I|SPSR_F)) != 0)
 		return EINVAL;
 #ifdef __AARCH64EB__
 	if ((spsr & SPSR_A32_E) == 0)
 		return EINVAL;
 #else
 	if ((spsr & SPSR_A32_E) != 0)
 		return EINVAL;
 #endif
 	if ((spsr & (SPSR_A|SPSR_I|SPSR_F)) != 0)
 		return EINVAL;
 	return 0;
+}
 void
 cpu_getmcontext32(struct lwp *l, mcontext32_t *mcp, unsigned int *flagsp)
+{
 	struct trapframe * const tf = l->l_md.md_utf;
 	__greg32_t *gr = mcp->__gregs;
 	__greg32_t ras_pc;
 	gr[_REG_R0]  = tf->tf_reg[0];
 	gr[_REG_R1]  = tf->tf_reg[1];
 	gr[_REG_R2]  = tf->tf_reg[2];
 	gr[_REG_R3]  = tf->tf_reg[3];
 	gr[_REG_R4]  = tf->tf_reg[4];
 	gr[_REG_R5]  = tf->tf_reg[5];
 	gr[_REG_R6]  = tf->tf_reg[6];
 	gr[_REG_R7]  = tf->tf_reg[7];
 	gr[_REG_R8]  = tf->tf_reg[8];
 	gr[_REG_R9]  = tf->tf_reg[9];
 	gr[_REG_R10] = tf->tf_reg[10];
 	gr[_REG_R11] = tf->tf_reg[11];
 	gr[_REG_R12] = tf->tf_reg[12];
 	gr[_REG_R13] = tf->tf_reg[13];
 	gr[_REG_R14] = tf->tf_reg[14];
 	gr[_REG_R15] = tf->tf_pc;
 	gr[_REG_CPSR] = tf->tf_spsr;
 	if ((ras_pc = (__greg32_t)(uintptr_t)ras_lookup(l->l_proc,
 	    (void *)(uintptr_t)gr[_REG_R15])) != -1) {
 		gr[_REG_R15] = ras_pc;
+	}
 	*flagsp |= _UC_CPU;
 	/* fpu context */
 	if (fpu_used_p(l)) {
 		const struct pcb * const pcb = lwp_getpcb(l);
 		int i;
 		fpu_save(l);
 		CTASSERT(__arraycount(mcp->__vfpregs.__vfp_fstmx) ==
 		    __arraycount(pcb->pcb_fpregs.fp_reg));
 		for (i = 0; i < __arraycount(pcb->pcb_fpregs.fp_reg); i++) {
 			mcp->__vfpregs.__vfp_fstmx[i] =
 #ifdef __AARCH64EB__
 			    pcb->pcb_fpregs.fp_reg[i].u64[1];
 #else
 			    pcb->pcb_fpregs.fp_reg[i].u64[0];
 #endif
+		}
 		mcp->__vfpregs.__vfp_fpscr =
 		    (pcb->pcb_fpregs.fpsr & FPSR_BITS) |
 		    (pcb->pcb_fpregs.fpcr & FPCR_BITS);
 		mcp->__vfpregs.__vfp_fpsid = 0;	/* XXX: build FPSID from MIDR */
 		*flagsp |= _UC_FPU;
+	}
 	mcp->_mc_tlsbase = (uint32_t)(uintptr_t)l->l_private;
 	*flagsp |= _UC_TLSBASE;
+}
 int
 cpu_setmcontext32(struct lwp *l, const mcontext32_t *mcp, unsigned int flags)
+{
 	struct trapframe * const tf = l->l_md.md_utf;
 	const __greg32_t * const gr = mcp->__gregs;
 	struct proc * const p = l->l_proc;
 	int error, i;
 	if (flags & _UC_CPU) {
 		error = cpu_mcontext32_validate(l, mcp);
 		if (error != 0)
 			return error;
 		tf->tf_reg[0]  = gr[_REG_R0];
 		tf->tf_reg[1]  = gr[_REG_R1];
 		tf->tf_reg[2]  = gr[_REG_R2];
 		tf->tf_reg[3]  = gr[_REG_R3];
 		tf->tf_reg[4]  = gr[_REG_R4];
 		tf->tf_reg[5]  = gr[_REG_R5];
 		tf->tf_reg[6]  = gr[_REG_R6];
 		tf->tf_reg[7]  = gr[_REG_R7];
 		tf->tf_reg[8]  = gr[_REG_R8];
 		tf->tf_reg[9]  = gr[_REG_R9];
 		tf->tf_reg[10] = gr[_REG_R10];
 		tf->tf_reg[11] = gr[_REG_R11];
 		tf->tf_reg[12] = gr[_REG_R12];
 		tf->tf_reg[13] = gr[_REG_R13];
 		tf->tf_reg[14] = gr[_REG_R14];
 		tf->tf_pc      = gr[_REG_R15];
 		tf->tf_spsr    = gr[_REG_CPSR];
+	}
 	if (flags & _UC_FPU) {
 		struct pcb * const pcb = lwp_getpcb(l);
 		fpu_discard(l, true);
 		CTASSERT(__arraycount(mcp->__vfpregs.__vfp_fstmx) ==
 		    __arraycount(pcb->pcb_fpregs.fp_reg));
 		for (i = 0; i < __arraycount(pcb->pcb_fpregs.fp_reg); i++) {
 #ifdef __AARCH64EB__
 			pcb->pcb_fpregs.fp_reg[i].u64[0] = 0;
 			pcb->pcb_fpregs.fp_reg[i].u64[1] =
 #else
 			pcb->pcb_fpregs.fp_reg[i].u64[1] = 0;
 			pcb->pcb_fpregs.fp_reg[i].u64[0] =
 #endif
 			    mcp->__vfpregs.__vfp_fstmx[i];
+		}
 		pcb->pcb_fpregs.fpsr =
 		    mcp->__vfpregs.__vfp_fpscr & FPSR_BITS;
 		pcb->pcb_fpregs.fpcr =
 		    mcp->__vfpregs.__vfp_fpscr & FPCR_BITS;
+	}
 	if (flags &_UC_TLSBASE)
 		l->l_private = (void *)(uintptr_t)mcp->_mc_tlsbase;
 	mutex_enter(p->p_lock);
 	if (flags & _UC_SETSTACK)
 		l->l_sigstk.ss_flags |= SS_ONSTACK;
 	if (flags & _UC_CLRSTACK)
 		l->l_sigstk.ss_flags &= ~SS_ONSTACK;
 	mutex_exit(p->p_lock);
 	return 0;
+}
 static int
 arm32_sync_icache(struct lwp *l, const void *args, register_t *retval)
+{
 	struct netbsd32_arm_sync_icache_args ua;
 	struct faultbuf fb;
 	int error;
 	error = copyin(args, &ua, sizeof(ua));
 	if (error != 0)
 		return error;
 	if ((vaddr_t)ua.addr + ua.len > VM_MAXUSER_ADDRESS32)
 		return EINVAL;
 	/* use cpu_set_onfault() by way of precaution */
 	if ((error = cpu_set_onfault(&fb)) == 0) {
 		pmap_icache_sync_range(
 		    vm_map_pmap(&l->l_proc->p_vmspace->vm_map),
 		    (vaddr_t)ua.addr, (vaddr_t)ua.addr + ua.len);
 		cpu_unset_onfault();
+	}
 	*retval = 0;
 	return error;
+}
 static int
 arm32_drain_writebuf(struct lwp *l, const void *args, register_t *retval)
+{
 	aarch64_drain_writebuf();
 	*retval = 0;
 	return 0;
+}
 int
 netbsd32_sysarch(struct lwp *l, const struct netbsd32_sysarch_args *uap,
     register_t *retval)
+{
 	/* {
 		syscallarg(int) op;
 		syscallarg(netbsd32_voidp) parms;
 	} */
 	int error;
 	switch (SCARG(uap, op)) {
 	case ARM_SYNC_ICACHE:
 		error = arm32_sync_icache(l,
 		    NETBSD32PTR64(SCARG(uap, parms)), retval);
 		break;
 	case ARM_DRAIN_WRITEBUF:
 		error = arm32_drain_writebuf(l,
 		    NETBSD32PTR64(SCARG(uap, parms)), retval);
 		break;
 	case ARM_VFP_FPSCR:
 		printf("%s: ARM_VFP_FPSCR not implemented\n", __func__);
 		error = EINVAL;
 		break;
 	case ARM_FPU_USED:
 		printf("%s: ARM_FPU_USED not implemented\n", __func__);
 		error = EINVAL;
 		break;
 	default:
 		printf("%s: op=%d: not implemented\n", __func__,
 		    SCARG(uap, op));
 		error = EINVAL;
 		break;
+	}
 	return error;
+}
 vaddr_t
 netbsd32_vm_default_addr(struct proc *p, vaddr_t base, vsize_t sz,
     int topdown)
+{
 	if (topdown)
 		return VM_DEFAULT_ADDRESS32_TOPDOWN(base, sz);
 	else
 		return VM_DEFAULT_ADDRESS32_BOTTOMUP(base, sz);
+}
 void
 netbsd32_machdep_md_init(void)
+{
 	/* nothing to do */
+}
 void
 netbsd32_machdep_md_fini(void)
+{
 	/* nothing to do */
+}

 @@ -1,638 +1,655 @@
-/* $NetBSD: trap.c,v 1.17.4.3 2021/01/01 12:31:19 martin Exp $ */
+/* $NetBSD: trap.c,v 1.17.4.4 2021/01/01 12:58:35 martin Exp $ */
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.17.4.3 2021/01/01 12:31:19 martin Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.17.4.4 2021/01/01 12:58:35 martin Exp $");
 #include "opt_arm_intr_impl.h"
 #include "opt_compat_netbsd32.h"
 #include "opt_dtrace.h"
 #include <sys/param.h>
 #include <sys/kauth.h>
 #include <sys/types.h>
 #include <sys/atomic.h>
 #include <sys/cpu.h>
 #ifdef KDB
 #include <sys/kdb.h>
 #endif
 #include <sys/proc.h>
 #include <sys/systm.h>
 #include <sys/signal.h>
 #include <sys/signalvar.h>
 #include <sys/siginfo.h>
 #ifdef ARM_INTR_IMPL
 #include ARM_INTR_IMPL
 #else
 #error ARM_INTR_IMPL not defined
 #endif
 #ifndef ARM_IRQ_HANDLER
 #error ARM_IRQ_HANDLER not defined
 #endif
 #include <aarch64/userret.h>
 #include <aarch64/frame.h>
 #include <aarch64/machdep.h>
 #include <aarch64/armreg.h>
 #include <aarch64/locore.h>
 #ifdef KDB
 #include <machine/db_machdep.h>
 #endif
 #ifdef DDB
 #include <ddb/db_output.h>
 #include <machine/db_machdep.h>
 #endif
 #ifdef KDTRACE_HOOKS
 #include <sys/dtrace_bsd.h>
 #endif
 #ifdef DDB
 int sigill_debug = 0;
 #endif
 #ifdef KDTRACE_HOOKS
 dtrace_doubletrap_func_t	dtrace_doubletrap_func = NULL;
 dtrace_trap_func_t		dtrace_trap_func = NULL;
 int (*dtrace_invop_jump_addr)(struct trapframe *);
 #endif
 const char * const trap_names[] = {
 	[ESR_EC_UNKNOWN]	= "Unknown Reason (Illegal Instruction)",
 	[ESR_EC_SERROR]		= "SError Interrupt",
 	[ESR_EC_WFX]		= "WFI or WFE instruction execution",
 	[ESR_EC_ILL_STATE]	= "Illegal Execution State",
 	[ESR_EC_SYS_REG]	= "MSR/MRS/SYS instruction",
 	[ESR_EC_SVC_A64]	= "SVC Instruction Execution",
 	[ESR_EC_HVC_A64]	= "HVC Instruction Execution",
 	[ESR_EC_SMC_A64]	= "SMC Instruction Execution",
 	[ESR_EC_INSN_ABT_EL0]	= "Instruction Abort (EL0)",
 	[ESR_EC_INSN_ABT_EL1]	= "Instruction Abort (EL1)",
 	[ESR_EC_DATA_ABT_EL0]	= "Data Abort (EL0)",
 	[ESR_EC_DATA_ABT_EL1]	= "Data Abort (EL1)",
 	[ESR_EC_PC_ALIGNMENT]	= "Misaligned PC",
 	[ESR_EC_SP_ALIGNMENT]	= "Misaligned SP",
 	[ESR_EC_FP_ACCESS]	= "Access to SIMD/FP Registers",
 	[ESR_EC_FP_TRAP_A64]	= "FP Exception",
 	[ESR_EC_BRKPNT_EL0]	= "Breakpoint Exception (EL0)",
 	[ESR_EC_BRKPNT_EL1]	= "Breakpoint Exception (EL1)",
 	[ESR_EC_SW_STEP_EL0]	= "Software Step (EL0)",
 	[ESR_EC_SW_STEP_EL1]	= "Software Step (EL1)",
 	[ESR_EC_WTCHPNT_EL0]	= "Watchpoint (EL0)",
 	[ESR_EC_WTCHPNT_EL1]	= "Watchpoint (EL1)",
 	[ESR_EC_BKPT_INSN_A64]	= "BKPT Instruction Execution",
 	[ESR_EC_CP15_RT]	= "A32: MCR/MRC access to CP15",
 	[ESR_EC_CP15_RRT]	= "A32: MCRR/MRRC access to CP15",
 	[ESR_EC_CP14_RT]	= "A32: MCR/MRC access to CP14",
 	[ESR_EC_CP14_DT]	= "A32: LDC/STC access to CP14",
 	[ESR_EC_CP14_RRT]	= "A32: MRRC access to CP14",
 	[ESR_EC_SVC_A32]	= "A32: SVC Instruction Execution",
 	[ESR_EC_HVC_A32]	= "A32: HVC Instruction Execution",
 	[ESR_EC_SMC_A32]	= "A32: SMC Instruction Execution",
 	[ESR_EC_FPID]		= "A32: MCR/MRC access to CP10",
 	[ESR_EC_FP_TRAP_A32]	= "A32: FP Exception",
 	[ESR_EC_BKPT_INSN_A32]	= "A32: BKPT Instruction Execution",
 	[ESR_EC_VECTOR_CATCH]	= "A32: Vector Catch Exception"
 };
 const char *
 eclass_trapname(uint32_t eclass)
+{
 	static char trapnamebuf[sizeof("Unknown trap 0x????????")];
 	if (eclass >= __arraycount(trap_names) || trap_names[eclass] == NULL) {
 		snprintf(trapnamebuf, sizeof(trapnamebuf),
 		    "Unknown trap %#02x", eclass);
 		return trapnamebuf;
+	}
 	return trap_names[eclass];
+}
 void
 userret(struct lwp *l)
+{
 	mi_userret(l);
+}
 void
 trap_doast(struct trapframe *tf)
+{
 	struct lwp * const l = curlwp;
 	/*
 	 * allow to have a chance of context switch just prior to user
 	 * exception return.
 	 */
 #ifdef __HAVE_PREEMPTION
 	kpreempt_disable();
 #endif
 	struct cpu_info * const ci = curcpu();
 	ci->ci_data.cpu_ntrap++;
 	KDASSERT(ci->ci_cpl == IPL_NONE);
 	const int want_resched = ci->ci_want_resched;
 #ifdef __HAVE_PREEMPTION
 	kpreempt_enable();
 #endif
 	if (l->l_pflag & LP_OWEUPC) {
 		l->l_pflag &= ~LP_OWEUPC;
 		ADDUPROF(l);
+	}
 	/* Allow a forced task switch. */
 	if (want_resched)
 		preempt();
 	userret(l);
+}
 void
 trap_el1h_sync(struct trapframe *tf)
+{
 	const uint32_t esr = tf->tf_esr;
 	const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */
 	/* re-enable traps and interrupts */
 	if (!(tf->tf_spsr & SPSR_I))
 		daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F);
 	else
 		daif_enable(DAIF_D|DAIF_A);
 #ifdef KDTRACE_HOOKS
 	if (dtrace_trap_func != NULL && (*dtrace_trap_func)(tf, eclass))
 		return;
 #endif
 	switch (eclass) {
 	case ESR_EC_INSN_ABT_EL1:
 	case ESR_EC_DATA_ABT_EL1:
 		data_abort_handler(tf, eclass);
 		break;
 	case ESR_EC_BKPT_INSN_A64:
 #ifdef KDTRACE_HOOKS
 		if (__SHIFTOUT(esr, ESR_ISS) == 0x40d &&
 		    dtrace_invop_jump_addr != 0) {
 			(*dtrace_invop_jump_addr)(tf);
 			break;
+		}
 		/* FALLTHROUGH */
 #endif
 	case ESR_EC_BRKPNT_EL1:
 	case ESR_EC_SW_STEP_EL1:
 	case ESR_EC_WTCHPNT_EL1:
 #ifdef DDB
 		if (eclass == ESR_EC_BRKPNT_EL1)
 			kdb_trap(DB_TRAP_BREAKPOINT, tf);
 		else if (eclass == ESR_EC_BKPT_INSN_A64)
 			kdb_trap(DB_TRAP_BKPT_INSN, tf);
 		else if (eclass == ESR_EC_WTCHPNT_EL1)
 			kdb_trap(DB_TRAP_WATCHPOINT, tf);
 		else if (eclass == ESR_EC_SW_STEP_EL1)
 			kdb_trap(DB_TRAP_SW_STEP, tf);
 		else
 			kdb_trap(DB_TRAP_UNKNOWN, tf);
 #else
 		panic("No debugger in kernel");
 #endif
 		break;
 	case ESR_EC_FP_ACCESS:
 	case ESR_EC_FP_TRAP_A64:
 	case ESR_EC_PC_ALIGNMENT:
 	case ESR_EC_SP_ALIGNMENT:
 	case ESR_EC_ILL_STATE:
 	default:
 		panic("Trap: fatal %s: pc=%016" PRIx64 " sp=%016" PRIx64
 		    " esr=%08x", eclass_trapname(eclass), tf->tf_pc, tf->tf_sp,
 		    esr);
 		break;
+	}
+}
 void
 trap_el0_sync(struct trapframe *tf)
+{
 	struct lwp * const l = curlwp;
 	const uint32_t esr = tf->tf_esr;
 	const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */
 	/* disable trace */
 	reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS);
 	/* enable traps and interrupts */
 	daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F);
 	switch (eclass) {
 	case ESR_EC_INSN_ABT_EL0:
 	case ESR_EC_DATA_ABT_EL0:
 		data_abort_handler(tf, eclass);
 		userret(l);
 		break;
 	case ESR_EC_SVC_A64:
 		(*l->l_proc->p_md.md_syscall)(tf);
 		break;
 	case ESR_EC_FP_ACCESS:
 		fpu_load(l);
 		userret(l);
 		break;
 	case ESR_EC_FP_TRAP_A64:
 		do_trapsignal(l, SIGFPE, FPE_FLTUND, NULL, esr); /* XXX */
 		userret(l);
 		break;
 	case ESR_EC_PC_ALIGNMENT:
 		do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_pc, esr);
 		userret(l);
 		break;
 	case ESR_EC_SP_ALIGNMENT:
 		do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_sp, esr);
 		userret(l);
 		break;
 	case ESR_EC_BKPT_INSN_A64:
 	case ESR_EC_BRKPNT_EL0:
 	case ESR_EC_WTCHPNT_EL0:
 		do_trapsignal(l, SIGTRAP, TRAP_BRKPT, (void *)tf->tf_pc, esr);
 		userret(l);
 		break;
 	case ESR_EC_SW_STEP_EL0:
 		/* disable trace, and send trace trap */
 		tf->tf_spsr &= ~SPSR_SS;
 		do_trapsignal(l, SIGTRAP, TRAP_TRACE, (void *)tf->tf_pc, esr);
 		userret(l);
 		break;
 	default:
 	case ESR_EC_UNKNOWN:
 #ifdef DDB
 		if (sigill_debug) {
 			/* show illegal instruction */
 			printf("TRAP: pid %d (%s), uid %d: %s:"
 			    " esr=0x%lx: pc=0x%lx: %s\n",
 			    curlwp->l_proc->p_pid, curlwp->l_proc->p_comm,
 			    l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1,
 			    eclass_trapname(eclass), tf->tf_esr, tf->tf_pc,
 			    strdisasm(tf->tf_pc));
+		}
 #endif
 		/* illegal or not implemented instruction */
 		do_trapsignal(l, SIGILL, ILL_ILLTRP, (void *)tf->tf_pc, esr);
 		userret(l);
 		break;
+	}
+}
 void
 interrupt(struct trapframe *tf)
+{
 	struct cpu_info * const ci = curcpu();
 #ifdef STACKCHECKS
 	struct lwp *l = curlwp;
 	void *sp = (void *)reg_sp_read();
 	if (l->l_addr >= sp) {
 		panic("lwp/interrupt stack overflow detected."
 		    " lwp=%p, sp=%p, l_addr=%p", l, sp, l->l_addr);
+	}
 #endif
 	/* disable trace */
 	reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS);
 	/* enable traps */
 	daif_enable(DAIF_D|DAIF_A);
 	ci->ci_intr_depth++;
 	ARM_IRQ_HANDLER(tf);
 	ci->ci_intr_depth--;
 	cpu_dosoftints();
+}
 #ifdef COMPAT_NETBSD32
 /*
  * 32-bit length Thumb instruction. See ARMv7 DDI0406A A6.3.
  */
 #define THUMB_32BIT(hi) (((hi) & 0xe000) == 0xe000 && ((hi) & 0x1800))
 static int
 fetch_arm_insn(struct trapframe *tf, uint32_t *insn)
+{
 	/* THUMB? */
 	if (tf->tf_spsr & SPSR_A32_T) {
 		uint16_t *pc = (uint16_t *)(tf->tf_pc & ~1UL); /* XXX */
 		uint16_t hi, lo;
 		if (ufetch_16(pc, &hi))
 			return -1;
 		if (!THUMB_32BIT(hi)) {
 			/* 16-bit Thumb instruction */
 			*insn = hi;
 			return 2;
+		}
 		/* 32-bit Thumb instruction */
 		if (ufetch_16(pc + 1, &lo))
 			return -1;
 		*insn = ((uint32_t)hi << 16) | lo;
 		return 4;
+	}
 	if (ufetch_32((uint32_t *)tf->tf_pc, insn))
 		return -1;
 	return 4;
+}
 enum emul_arm_result {
 	EMUL_ARM_SUCCESS = 0,
 	EMUL_ARM_UNKNOWN,
 	EMUL_ARM_FAULT,
 };
 static enum emul_arm_result
 emul_arm_insn(struct trapframe *tf)
+{
 	struct lwp * const l = curlwp;
 	uint32_t insn;
 	int insn_size;
 	insn_size = fetch_arm_insn(tf, &insn);
 	switch (insn_size) {
 	case 2:
 		/* T32-16bit instruction */
 		/*
 		 * Breakpoint used by GDB.
 		 */
 		if (insn == 0xdefe)
 			goto trap;
 		/* XXX: some T32 IT instruction deprecated should be emulated */
 		break;
 	case 4:
 		/* T32-32bit instruction, or A32 instruction */
 		/*
 		 * Breakpoint used by GDB.
 		 */
 		if (insn == 0xe6000011 || insn == 0xe7ffdefe) {
  trap:
 			do_trapsignal(l, SIGTRAP, TRAP_BRKPT,
 			    (void *)tf->tf_pc, 0);
 			return 0;
+		}
 		/*
 		 * Emulate ARMv6 instructions with cache operations
 		 * register (c7), that can be used in user mode.
 		 */
 		switch (insn & 0x0fff0fff) {
 		case 0x0e070f95:
 			/*
 			 * mcr p15, 0, <Rd>, c7, c5, 4
 			 * (flush prefetch buffer)
 			 */
 			__asm __volatile("isb sy" ::: "memory");
 			goto emulated;
 		case 0x0e070f9a:
 			/*
 			 * mcr p15, 0, <Rd>, c7, c10, 4
 			 * (data synchronization barrier)
 			 */
 			__asm __volatile("dsb sy" ::: "memory");
 			goto emulated;
 		case 0x0e070fba:
 			/*
 			 * mcr p15, 0, <Rd>, c7, c10, 5
 			 * (data memory barrier)
 			 */
 			__asm __volatile("dmb sy" ::: "memory");
 			goto emulated;
 		default:
 			break;
+		}
 		break;
 	default:
 		return EMUL_ARM_FAULT;
+	}
 	/* unknown, or unsupported instruction */
 	return EMUL_ARM_UNKNOWN;
  emulated:
 	tf->tf_pc += insn_size;
 	return EMUL_ARM_SUCCESS;
+}
 #endif /* COMPAT_NETBSD32 */
 void
 trap_el0_32sync(struct trapframe *tf)
+{
 	struct lwp * const l = curlwp;
 	const uint32_t esr = tf->tf_esr;
 	const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */
 	/* disable trace */
 	reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS);
 	/* enable traps and interrupts */
 	daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F);
 	switch (eclass) {
 #ifdef COMPAT_NETBSD32
 	case ESR_EC_INSN_ABT_EL0:
 	case ESR_EC_DATA_ABT_EL0:
 		data_abort_handler(tf, eclass);
 		userret(l);
 		break;
 	case ESR_EC_SVC_A32:
 		(*l->l_proc->p_md.md_syscall)(tf);
 		break;
 	case ESR_EC_FP_ACCESS:
 		fpu_load(l);
 		userret(l);
 		break;
 	case ESR_EC_FP_TRAP_A32:
 		do_trapsignal(l, SIGFPE, FPE_FLTUND, NULL, esr); /* XXX */
 		userret(l);
 		break;
 	case ESR_EC_PC_ALIGNMENT:
 		do_trapsignal(l, SIGBUS, BUS_ADRALN, (void *)tf->tf_pc, esr);
 		userret(l);
 		break;
 	case ESR_EC_SP_ALIGNMENT:
 		do_trapsignal(l, SIGBUS, BUS_ADRALN,
 		    (void *)tf->tf_reg[13], esr); /* sp is r13 on AArch32 */
 		userret(l);
 		break;
 	case ESR_EC_BKPT_INSN_A32:
 		do_trapsignal(l, SIGTRAP, TRAP_BRKPT, (void *)tf->tf_pc, esr);
 		userret(l);
 		break;
 	case ESR_EC_UNKNOWN:
 		switch (emul_arm_insn(tf)) {
 		case EMUL_ARM_SUCCESS:
 			break;
 		case EMUL_ARM_UNKNOWN:
 			goto unknown;
 		case EMUL_ARM_FAULT:
 			do_trapsignal(l, SIGSEGV, SEGV_MAPERR,
 			    (void *)tf->tf_pc, esr);
 			break;
+		}
 		userret(l);
 		break;
 	case ESR_EC_CP15_RT:
 	case ESR_EC_CP15_RRT:
 	case ESR_EC_CP14_RT:
 	case ESR_EC_CP14_DT:
 	case ESR_EC_CP14_RRT:
 unknown:
 #endif /* COMPAT_NETBSD32 */
 	default:
 #ifdef DDB
 		if (sigill_debug) {
 			/* show illegal instruction */
 			printf("TRAP: pid %d (%s), uid %d: %s:"
 			    " esr=0x%lx: pc=0x%lx: %s\n",
 			    curlwp->l_proc->p_pid, curlwp->l_proc->p_comm,
 			    l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1,
 			    eclass_trapname(eclass), tf->tf_esr, tf->tf_pc,
 			    strdisasm_aarch32(tf->tf_pc));
+		}
 #endif
 		/* illegal or not implemented instruction */
 		do_trapsignal(l, SIGILL, ILL_ILLTRP, (void *)tf->tf_pc, esr);
 		userret(l);
 		break;
+	}
+}
 #define bad_trap_panic(trapfunc)	\
 void					\
 trapfunc(struct trapframe *tf)		\
 {					\
 	panic("%s", __func__);		\
+}
 bad_trap_panic(trap_el1t_sync)
 bad_trap_panic(trap_el1t_irq)
 bad_trap_panic(trap_el1t_fiq)
 bad_trap_panic(trap_el1t_error)
 bad_trap_panic(trap_el1h_fiq)
 bad_trap_panic(trap_el1h_error)
 bad_trap_panic(trap_el0_fiq)
 bad_trap_panic(trap_el0_error)
 bad_trap_panic(trap_el0_32fiq)
 bad_trap_panic(trap_el0_32error)
 void
 cpu_jump_onfault(struct trapframe *tf, const struct faultbuf *fb, int val)
+{
 	tf->tf_reg[19] = fb->fb_reg[FB_X19];
 	tf->tf_reg[20] = fb->fb_reg[FB_X20];
 	tf->tf_reg[21] = fb->fb_reg[FB_X21];
 	tf->tf_reg[22] = fb->fb_reg[FB_X22];
 	tf->tf_reg[23] = fb->fb_reg[FB_X23];
 	tf->tf_reg[24] = fb->fb_reg[FB_X24];
 	tf->tf_reg[25] = fb->fb_reg[FB_X25];
 	tf->tf_reg[26] = fb->fb_reg[FB_X26];
 	tf->tf_reg[27] = fb->fb_reg[FB_X27];
 	tf->tf_reg[28] = fb->fb_reg[FB_X28];
 	tf->tf_reg[29] = fb->fb_reg[FB_X29];
 	tf->tf_sp = fb->fb_reg[FB_SP];
 	tf->tf_pc = fb->fb_reg[FB_LR];
 	tf->tf_reg[0] = val;
+}
 #ifdef TRAP_SIGDEBUG
 static void
 frame_dump(const struct trapframe *tf)
+{
 	const struct reg *r = &tf->tf_regs;
 	printf("trapframe %p\n", tf);
 	for (size_t i = 0; i < __arraycount(r->r_reg); i++) {
 		printf(" r%.2zu %#018" PRIx64 "%c", i, r->r_reg[i],
 		    " \n"[i && (i & 1) == 0]);
+	}
 	printf("\n");
 	printf("   sp %#018" PRIx64 "    pc %#018" PRIx64 "\n",
 	    r->r_sp, r->r_pc);
 	printf(" spsr %#018" PRIx64 " tpidr %#018" PRIx64 "\n",
 	    r->r_spsr, r->r_tpidr);
 	printf("  esr %#018" PRIx64 "   far %#018" PRIx64 "\n",
 	    tf->tf_esr, tf->tf_far);
 	printf("\n");
 	hexdump(printf, "Stack dump", tf, 256);
+}
 static void
 sigdebug(const struct trapframe *tf, const ksiginfo_t *ksi)
+{
 	struct lwp *l = curlwp;
 	struct proc *p = l->l_proc;
 	const uint32_t eclass = __SHIFTOUT(ksi->ksi_trap, ESR_EC);
 	printf("pid %d.%d (%s): signal %d (trap %#x) "
 	    "@pc %#" PRIx64 ", addr %p, error=%s\n",
 	    p->p_pid, l->l_lid, p->p_comm, ksi->ksi_signo, ksi->ksi_trap,
 	    tf->tf_regs.r_pc, ksi->ksi_addr, eclass_trapname(eclass));
 	frame_dump(tf);
+}
 #endif
 void do_trapsignal1(
 #ifdef TRAP_SIGDEBUG
     const char *func,
     size_t line,
     struct trapframe *tf,
 #endif
     struct lwp *l, int signo, int code, void *addr, int trap)
+{
 	ksiginfo_t ksi;
 	KSI_INIT_TRAP(&ksi);
 	ksi.ksi_signo = signo;
 	ksi.ksi_code = code;
 	ksi.ksi_addr = addr;
 	ksi.ksi_trap = trap;
 #ifdef TRAP_SIGDEBUG
 	printf("%s, %zu: ", func, line);
 	sigdebug(tf, &ksi);
 #endif
 	(*l->l_proc->p_emul->e_trapsignal)(l, &ksi);
+}

 @@ -1,110 +1,131 @@
-/*	$NetBSD: netbsd32_machdep.h,v 1.2 2018/10/12 01:28:58 ryo Exp $	*/
+/*	$NetBSD: netbsd32_machdep.h,v 1.2.4.1 2021/01/01 12:58:35 martin Exp $	*/
 #ifndef _MACHINE_NETBSD32_H_
 #define _MACHINE_NETBSD32_H_
 #include <sys/ucontext.h>
 #include <compat/sys/ucontext.h>
 #include <compat/sys/siginfo.h>
 /*
  * arm ptrace constants
  * Please keep in sync with sys/arch/arm/include/ptrace.h.
  */
 #define PT32_STEP	(PT_FIRSTMACH + 0) /* Not implemented */
 #define PT32_GETREGS	(PT_FIRSTMACH + 1)
 #define PT32_SETREGS	(PT_FIRSTMACH + 2)
 #define PT32_GETFPREGS	(PT_FIRSTMACH + 5)
 #define PT32_SETFPREGS	(PT_FIRSTMACH + 6)
 #define PT32_SETSTEP	(PT_FIRSTMACH + 7) /* Not implemented */
 #define PT32_CLEARSTEP	(PT_FIRSTMACH + 8) /* Not implemented */
 #define NETBSD32_POINTER_TYPE uint32_t
 typedef	struct { NETBSD32_POINTER_TYPE i32; } netbsd32_pointer_t;
 /* earm has 64bit aligned 64bit integers */
 #define NETBSD32_INT64_ALIGN __attribute__((__aligned__(8)))
 typedef netbsd32_pointer_t netbsd32_sigcontextp_t;
 struct netbsd32_sigcontext13 {
 	int32_t		sc_onstack;		/* sigstack state to restore */
 	int32_t		__sc_mask13;		/* signal mask to restore (old style) */
 	uint32_t	sc_spsr;
 	uint32_t	sc_r0;
 	uint32_t	sc_r1;
 	uint32_t	sc_r2;
 	uint32_t	sc_r3;
 	uint32_t	sc_r4;
 	uint32_t	sc_r5;
 	uint32_t	sc_r6;
 	uint32_t	sc_r7;
 	uint32_t	sc_r8;
 	uint32_t	sc_r9;
 	uint32_t	sc_r10;
 	uint32_t	sc_r11;
 	uint32_t	sc_r12;
 	uint32_t	sc_usr_sp;
 	uint32_t	sc_usr_lr;
 	uint32_t	sc_svc_lr;
 	uint32_t	sc_pc;
 };
 struct netbsd32_sigcontext {
 	int32_t		sc_onstack;		/* sigstack state to restore */
 	int32_t		__sc_mask13;		/* signal mask to restore (old style) */
 	uint32_t	sc_spsr;
 	uint32_t	sc_r0;
 	uint32_t	sc_r1;
 	uint32_t	sc_r2;
 	uint32_t	sc_r3;
 	uint32_t	sc_r4;
 	uint32_t	sc_r5;
 	uint32_t	sc_r6;
 	uint32_t	sc_r7;
 	uint32_t	sc_r8;
 	uint32_t	sc_r9;
 	uint32_t	sc_r10;
 	uint32_t	sc_r11;
 	uint32_t	sc_r12;
 	uint32_t	sc_usr_sp;
 	uint32_t	sc_usr_lr;
 	uint32_t	sc_svc_lr;
 	uint32_t	sc_pc;
 	sigset_t	sc_mask;		/* signal mask to restore (new style) */
 };
 struct netbsd32_sigframe_siginfo {
 	siginfo32_t sf_si;
 	ucontext32_t sf_uc;
 };
 struct reg32 {
 	uint32_t r[13];
 	uint32_t r_sp;
 	uint32_t r_lr;
 	uint32_t r_pc;
 	uint32_t r_cpsr;
 };
 struct vfpreg32 {
 	uint32_t vfp_fpexc;
 	uint32_t vfp_fpscr;
 	uint32_t vfp_fpinst;
 	uint32_t vfp_fpinst2;
 	uint64_t vfp_regs[33];	/* In case we need fstmx format. */
 };
 struct fpreg32 {
 	struct vfpreg32 fpr_vfp;
 };
 /* same as cpustate in arm/arm/core_machdep.c  */
 struct netbsd32_cpustate {
 	struct reg32 regs;
 	struct fpreg32 fpregs;
 };
 /* compat netbsd/arm sysarch(2) */
 #define ARM_SYNC_ICACHE		0
 #define ARM_DRAIN_WRITEBUF	1
 #define ARM_VFP_FPSCR		2
 #define ARM_FPU_USED		3
 struct netbsd32_arm_sync_icache_args {
-	netbsd32_uintptr_t addr;	/* Virtual start address */
+	uint32_t addr;		/* Virtual start address */
-	netbsd32_size_t len;		/* Region size */
+	uint32_t len;		/* Region size */
 };
 /* Translate ptrace() PT_* request from 32-bit userland to kernel. */
 int netbsd32_ptrace_translate_request(int);
 int netbsd32_process_read_regs(struct lwp *, struct reg32 *);
 int netbsd32_process_read_fpregs(struct lwp *, struct fpreg32 *, size_t *);
 int netbsd32_process_write_regs(struct lwp *, const struct reg32 *);
 int netbsd32_process_write_fpregs(struct lwp *, const struct fpreg32 *, size_t);
 #endif /* _MACHINE_NETBSD32_H_ */