 @@ -1,55 +1,55 @@
-/*	$NetBSD: pxa2x0_intr.c,v 1.22 2021/01/04 15:13:06 skrll Exp $	*/
+/*	$NetBSD: pxa2x0_intr.c,v 1.23 2021/01/04 15:13:50 skrll Exp $	*/
 /*
  * Copyright (c) 2002  Genetec Corporation.  All rights reserved.
  * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed for the NetBSD Project by
  *	Genetec Corporation.
  * 4. The name of Genetec Corporation may not be used to endorse or
  *    promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * IRQ handler for the Intel PXA2X0 processor.
  * It has integrated interrupt controller.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.22 2021/01/04 15:13:06 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.23 2021/01/04 15:13:50 skrll Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/malloc.h>
 #include <sys/bus.h>
 #include <machine/intr.h>
 #include <machine/lock.h>
 #include <arm/xscale/pxa2x0cpu.h>
 #include <arm/xscale/pxa2x0reg.h>
 #include <arm/xscale/pxa2x0var.h>
 #include <arm/xscale/pxa2x0_intr.h>
 @@ -60,27 +60,27 @@ __KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.
  */
 static int	pxaintc_match(device_t, cfdata_t, void *);
 static void	pxaintc_attach(device_t, device_t, void *);
 CFATTACH_DECL_NEW(pxaintc, 0,
     pxaintc_match, pxaintc_attach, NULL, NULL);
 static int pxaintc_attached;
 static int stray_interrupt(void *);
 static void init_interrupt_masks(void);
 /*
  * interrupt dispatch table.
  */
 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
 struct intrhand {
 	TAILQ_ENTRY(intrhand) ih_list;	/* link on intrq list */
 	int (*ih_func)(void *);		/* handler */
 	void *ih_arg;			/* arg for handler */
 };
 #endif
 static struct intrhandler {
 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
 	TAILQ_HEAD(,intrhand) list;
 #else
 @@ -163,34 +163,34 @@ pxa2x0_irq_handler(void *arg)
 	irqbits = read_icu(SAIPIC_IP);
 	while ((irqno = find_first_bit(irqbits)) >= 0) {
 		/* XXX: Shuould we handle IRQs in priority order? */
 		/* raise spl to stop interrupts of lower priorities */
 		if (saved_spl_level < extirq_level[irqno])
 			pxa2x0_setipl(extirq_level[irqno]);
 #ifdef notyet
 		/* Enable interrupt */
 #endif
 #ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ
 		(* handler[irqno].func)(
 			handler[irqno].cookie == 0
 			? frame : handler[irqno].cookie );
 #else
 		/* process all handlers for this interrupt.
 		   XXX not yet */
 #endif
 #ifdef notyet
 		/* Disable interrupt */
 #endif
 		irqbits &= ~(1<<irqno);
+	}
 	/* restore spl to that was when this interrupt happen */
 	pxa2x0_setipl(saved_spl_level);
 #ifdef __HAVE_FAST_SOFTINTS
 	cpu_dosoftints();
 #endif

 @@ -1,14 +1,14 @@
-/*	$NetBSD: wdc.c,v 1.304 2021/01/04 15:13:06 skrll Exp $ */
+/*	$NetBSD: wdc.c,v 1.305 2021/01/04 15:13:50 skrll Exp $ */
 /*
  * Copyright (c) 1998, 2001, 2003 Manuel Bouyer.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
 @@ -48,27 +48,27 @@
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * CODE UNTESTED IN THE CURRENT REVISION:
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.304 2021/01/04 15:13:06 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.305 2021/01/04 15:13:50 skrll Exp $");
 #include "opt_ata.h"
 #include "opt_wdc.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/conf.h>
 #include <sys/buf.h>
 #include <sys/device.h>
 #include <sys/malloc.h>
 #include <sys/kmem.h>
 #include <sys/syslog.h>
 @@ -708,28 +708,28 @@ wdcprobe1(struct ata_channel *chp, int p
 		bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh],
 , WDSD_IBM | 0x10);
 		bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0,
 		    ATAPI_SOFT_RESET);
+	}
 	delay(5000);
 #endif
 	wdc->reset(chp, RESET_POLL);
 	DELAY(2000);
 	(void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0);
 	if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL))
 		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
 		    WDCTL_4BIT);
 #ifdef WDC_NO_IDS
 	ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL);
 #else
 	ret_value = __wdcwait_reset(chp, ret_value, poll);
 #endif
 	ATADEBUG_PRINT(("%s:%d: after reset, ret_value=%#x\n",
 	    __func__, chp->ch_channel, ret_value), DEBUG_PROBE);
 	/* if reset failed, there's nothing here */
 	if (ret_value == 0) {
 		return 0;
 @@ -1028,69 +1028,69 @@ wdcreset(struct ata_channel *chp, int po
 	struct wdc_softc *wdc = CHAN_TO_WDC(chp);
 	struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
 	int drv_mask1, drv_mask2;
 	ata_channel_lock_owned(chp);
 #ifdef WDC_NO_IDS
 	poll = RESET_POLL;
 #endif
 	wdc->reset(chp, poll);
 	drv_mask1 = (chp->ch_drive[0].drive_type !=  ATA_DRIVET_NONE)
 	    ? 0x01 : 0x00;
 	if (chp->ch_ndrives > 1)
 		drv_mask1 |= (chp->ch_drive[1].drive_type != ATA_DRIVET_NONE)
 		    ? 0x02 : 0x00;
 	drv_mask2 = __wdcwait_reset(chp, drv_mask1,
 	    (poll == RESET_SLEEP) ? 0 : 1);
 	if (drv_mask2 != drv_mask1) {
 		aprint_error("%s channel %d: reset failed for",
 		    device_xname(atac->atac_dev), chp->ch_channel);
 		if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0)
 			aprint_normal(" drive 0");
 		if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0)
 			aprint_normal(" drive 1");
 		aprint_normal("\n");
+	}
 	if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL))
 		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
 		    WDCTL_4BIT);
 	return  (drv_mask1 != drv_mask2) ? 1 : 0;
+}
 void
 wdc_do_reset(struct ata_channel *chp, int poll)
+{
 	struct wdc_softc *wdc = CHAN_TO_WDC(chp);
 	struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
 	int s = 0;
 	if (poll != RESET_SLEEP)
 		s = splbio();
 	if (wdc->select)
 		wdc->select(chp,0);
 	/* master */
 	bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM);
 	delay(10);	/* 400ns delay */
 	/* assert SRST, wait for reset to complete */
 	if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) {
 		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
 		    WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
 		delay(2000);
+	}
 	(void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0);
 	if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL))
 		bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
 		    WDCTL_4BIT | WDCTL_IDS);
 	delay(10);	/* 400ns delay */
 	if (poll != RESET_SLEEP) {
 		/* ACK interrupt in case there is one pending left */
 		if (wdc->irqack)
 			wdc->irqack(chp);
 		splx(s);
+	}
+}
 static int
 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll)
 @@ -1441,28 +1441,28 @@ __wdccommand_start(struct ata_channel *c
 	    WDSD_IBM | (drive << 4));
 	switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ,
 	    ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) {
 	case WDCWAIT_OK:
 		break;
 	case WDCWAIT_TOUT:
 		ata_c->flags |= AT_TIMEOU;
 		return ATASTART_ABORT;
 	case WDCWAIT_THR:
 		return ATASTART_TH;
+	}
 	if (ata_c->flags & AT_POLL) {
 		/* polled command, disable interrupts */
 		if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL))
 			bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh,
 			    wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS);
+	}
 	if ((ata_c->flags & AT_LBA48) != 0) {
 		wdccommandext(chp, drive, ata_c->r_command,
 		    ata_c->r_lba, ata_c->r_count, ata_c->r_features,
 		    ata_c->r_device & ~0x10);
 	} else {
 		wdccommand(chp, drive, ata_c->r_command,
 		    (ata_c->r_lba >> 8) & 0xffff,
 		    WDSD_IBM | (drive << 4) |
 		    (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) |
 		    ((ata_c->r_lba >> 24) & 0x0f),
 		    ata_c->r_lba & 0xff,
 @@ -1646,68 +1646,68 @@ __wdccommand_done(struct ata_channel *ch
 		    wdr->cmd_iohs[wd_seccnt], 0);
 		ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot,
 		    wdr->cmd_iohs[wd_sector], 0) << 0;
 		ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot,
 		    wdr->cmd_iohs[wd_cyl_lo], 0) << 8;
 		ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot,
 		    wdr->cmd_iohs[wd_cyl_hi], 0) << 16;
 		ata_c->r_device = bus_space_read_1(wdr->cmd_iot,
 		    wdr->cmd_iohs[wd_sdh], 0);
 		if ((ata_c->flags & AT_LBA48) != 0) {
 			if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) {
 				if ((ata_c->flags & AT_POLL) != 0)
 					bus_space_write_1(wdr->ctl_iot,
 					    wdr->ctl_ioh, wd_aux_ctlr,
 					    WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS);
 				else
 					bus_space_write_1(wdr->ctl_iot,
 					    wdr->ctl_ioh, wd_aux_ctlr,
 					    WDCTL_HOB|WDCTL_4BIT);
+			}
 			ata_c->r_count |= bus_space_read_1(wdr->cmd_iot,
 			    wdr->cmd_iohs[wd_seccnt], 0) << 8;
 			ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot,
 			    wdr->cmd_iohs[wd_sector], 0) << 24;
 			ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot,
 			    wdr->cmd_iohs[wd_cyl_lo], 0) << 32;
 			ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot,
 			    wdr->cmd_iohs[wd_cyl_hi], 0) << 40;
 			if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) {
 				if ((ata_c->flags & AT_POLL) != 0)
 					bus_space_write_1(wdr->ctl_iot,
 					    wdr->ctl_ioh, wd_aux_ctlr,
 					    WDCTL_4BIT|WDCTL_IDS);
 				else
 					bus_space_write_1(wdr->ctl_iot,
 					    wdr->ctl_ioh, wd_aux_ctlr,
 					    WDCTL_4BIT);
+			}
 		} else {
 			ata_c->r_lba |=
 			    (uint64_t)(ata_c->r_device & 0x0f) << 24;
+		}
 		ata_c->r_device &= 0xf0;
+	}
 	__wdccommand_done_end(chp, xfer);
 	ata_deactivate_xfer(chp, xfer);
 out:
 	if (ata_c->flags & AT_POLL) {
 		/* enable interrupts */
 		if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL))
 			bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh,
 			    wd_aux_ctlr, WDCTL_4BIT);
 		delay(10); /* some drives need a little delay here */
+	}
 	if (start)
 		atastart(chp);
+}
 static void
 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer)
+{
 	struct ata_command *ata_c = &xfer->c_ata_c;

 @@ -1,27 +1,27 @@
- /* $NetBSD: TODO,v 1.30 2021/01/04 15:13:06 skrll Exp $ */
+/* $NetBSD: TODO,v 1.31 2021/01/04 15:13:50 skrll Exp $ */
 Things to be done:
 common:
 - make %g6 point to curcpu
 - make %g7 point to curlwp
 - change run-time checks for cpu type to function pointers
 sun4u:
 - GENERIC.UP kernel hangs on v445 (missing interrupt?)
 sun4v:
  - current status: The kernel boots and starts the init process.
    The following processes seem to crash on and on so more debugging to be done...
 - 64-bit kernel support
 - 32-bit kernel support
 - libkvm
 - ofwboot: tlb_init_sun4v() hardcodes number of slots to 64
 - locore.s: sun4v_datatrap missing implementation for trap level 1
 - check build without SUN4V defined
 - replace relevant references to %ver with GET_MAXCWP
 - pmap_mp_init(): sun4v missing handling
 - replace constructs like "wrpr %g0, PSTATE_KERN, %pstate" with NORMAL_GLOBALS
 - replace constructs line "wrpr %g0, PSTATE_INTR, %pstate" with ALTERNATE_GOBALS
 - sun4v tsb no need to lock... per cpu... anyway...