Mon Jan 11 17:12:13 2021 UTC ()

Small simplification


(skrll)

diff -r1.26 -r1.27 src/sys/arch/aarch64/aarch64/cpufunc.c

--- src/sys/arch/aarch64/aarch64/cpufunc.c 2020/10/22 07:31:15	1.26
+++ src/sys/arch/aarch64/aarch64/cpufunc.c 2021/01/11 17:12:13	1.27

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpufunc.c,v 1.26 2020/10/22 07:31:15 skrll Exp $	*/
+/*	$NetBSD: cpufunc.c,v 1.27 2021/01/11 17:12:13 skrll Exp $	*/
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -20,27 +20,27 @@
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include "opt_cpuoptions.h"
 #include "opt_multiprocessor.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.26 2020/10/22 07:31:15 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.27 2021/01/11 17:12:13 skrll Exp $");
 #include <sys/param.h>
 #include <sys/types.h>
 #include <sys/kmem.h>
 #include <sys/cpu.h>
 #include <uvm/uvm.h>
 #include <uvm/uvm_page.h>
 #include <arm/cpufunc.h>
 u_int cputype;			/* compat arm */
 u_int arm_dcache_align;		/* compat arm */
 @@ -429,50 +429,51 @@ aarch64_dcache_wb_all(void)
 		dsb(ish);
 		ln_dcache_wb_all(level, &cinfo[level].dcache);
+	}
 	dsb(ish);
+}
 int
 set_cpufuncs(void)
+{
 	struct cpu_info * const ci = curcpu();
 	const uint64_t ctr = reg_ctr_el0_read();
 	const uint64_t clidr = reg_clidr_el1_read();
 	const uint32_t midr __unused = reg_midr_el1_read();
 	/* install default functions */
 	ci->ci_cpufuncs.cf_set_ttbr0 = aarch64_set_ttbr0;
 	ci->ci_cpufuncs.cf_icache_sync_range = aarch64_icache_sync_range;
 	/*
 	 * install core/cluster specific functions
 	 */
 	/* Icache sync op */
 	if (__SHIFTOUT(ctr, CTR_EL0_DIC) == 1) {
 		/* Icache invalidation to the PoU is not required */
 		ci->ci_cpufuncs.cf_icache_sync_range =
 		    aarch64_icache_barrier_range;
 	} else if (__SHIFTOUT(ctr, CTR_EL0_IDC) == 1 ||
 	    __SHIFTOUT(clidr, CLIDR_LOC) == 0 ||
 	    (__SHIFTOUT(clidr, CLIDR_LOUIS) == 0 && __SHIFTOUT(clidr, CLIDR_LOUU) == 0)) {
 		/* Dcache clean to the PoU is not required for Icache */
 		ci->ci_cpufuncs.cf_icache_sync_range =
 		    aarch64_icache_inv_range;
+	}
 #ifdef CPU_THUNDERX
 	const uint32_t midr = reg_midr_el1_read();
 	/* Cavium erratum 27456 */
 	if ((midr == CPU_ID_THUNDERXP1d0) ||
 	    (midr == CPU_ID_THUNDERXP1d1) ||
 	    (midr == CPU_ID_THUNDERXP2d1) ||
 	    (midr == CPU_ID_THUNDERX81XXRX)) {
 		ci->ci_cpufuncs.cf_set_ttbr0 = aarch64_set_ttbr0_thunderx;
+	}
 #endif
 	return 0;
+}
 void