 @@ -1,14 +1,14 @@
-/* $NetBSD: motoi2c.c,v 1.9 2021/01/24 18:01:13 jmcneill Exp $ */
+/* $NetBSD: motoi2c.c,v 1.10 2021/01/25 12:08:47 jmcneill Exp $ */
 /*-
  * Copyright (c) 2007, 2010 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -20,27 +20,27 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: motoi2c.c,v 1.9 2021/01/24 18:01:13 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: motoi2c.c,v 1.10 2021/01/25 12:08:47 jmcneill Exp $");
 #if defined(__arm__) || defined(__aarch64__)
 #include "opt_fdt.h"
 #endif
 #include <sys/param.h>
 #include <sys/device.h>
 #include <sys/systm.h>
 #include <sys/mutex.h>
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <dev/i2c/i2cvar.h>
 @@ -99,104 +99,126 @@ motoi2c_attach_common(device_t self, str
 	iic_tag_init(&sc->sc_i2c);
 	sc->sc_i2c.ic_cookie = sc;
 	sc->sc_i2c.ic_acquire_bus = motoi2c_acquire_bus;
 	sc->sc_i2c.ic_release_bus = motoi2c_release_bus;
 	sc->sc_i2c.ic_exec = motoi2c_exec;
 	if (sc->sc_iord == NULL)
 		sc->sc_iord = motoi2c_iord1;
 	if (sc->sc_iowr == NULL)
 		sc->sc_iowr = motoi2c_iowr1;
 	memset(&iba, 0, sizeof(iba));
 	iba.iba_tag = &sc->sc_i2c;
 	iba.iba_child_devices = sc->sc_child_devices;
-	I2C_WRITE(I2CCR, 0);		/* reset before changing anything */
+	if ((sc->sc_flags & MOTOI2C_F_ENABLE_INV) != 0) {
 		sc->sc_enable_mask = 0;
 		sc->sc_disable_mask = CR_MEN;
 	} else {
 		sc->sc_enable_mask = CR_MEN;
 		sc->sc_disable_mask = 0;
+	}
 	I2C_WRITE(I2CCR, sc->sc_disable_mask);	/* reset before config */
 	I2C_WRITE(I2CDFSRR, i2c->i2c_dfsrr);	/* sampling units */
 	I2C_WRITE(I2CFDR, i2c->i2c_fdr);	/* divider 3072 (0x31) */
 	I2C_WRITE(I2CADR, i2c->i2c_adr);	/* our slave address is 0x7f */
-	I2C_WRITE(I2CSR, 0);		/* clear status flags */
+	if ((sc->sc_flags & MOTOI2C_F_STATUS_W1C) != 0) {
 		I2C_WRITE(I2CSR, I2C_READ(I2CSR)); /* clear status flags */
 	} else {
 		I2C_WRITE(I2CSR, 0);		/* clear status flags */
+	}
 #ifdef FDT
 	if (sc->sc_phandle != 0) {
 		fdtbus_register_i2c_controller(&sc->sc_i2c, sc->sc_phandle);
 		fdtbus_attach_i2cbus(self, sc->sc_phandle, &sc->sc_i2c,
 		    iicbus_print);
 	} else
 #endif
 	config_found_ia(self, "i2cbus", &iba, iicbus_print);
+}
 static int
 motoi2c_acquire_bus(void *v, int flags)
+{
 	struct motoi2c_softc * const sc = v;
-	I2C_WRITE(I2CCR, CR_MEN);	/* enable the I2C module */
+	I2C_WRITE(I2CCR, sc->sc_enable_mask);	/* enable the I2C module */
 	return 0;
+}
 static void
 motoi2c_release_bus(void *v, int flags)
+{
 	struct motoi2c_softc * const sc = v;
-	I2C_WRITE(I2CCR, 0);		/* reset before changing anything */
+	I2C_WRITE(I2CCR, sc->sc_disable_mask);	/* disable the I2C module */
+}
 static int
 motoi2c_stop_wait(struct motoi2c_softc *sc)
+{
 	u_int timo;
 	int error = 0;
 	timo = 1000;
 	while ((I2C_READ(I2CSR) & SR_MBB) != 0 && --timo)
 		DELAY(1);
 	if (timo == 0) {
 		DPRINTF(("%s: timeout (sr=%#x)\n", __func__, I2C_READ(I2CSR)));
 		error = ETIMEDOUT;
+	}
 	return error;
+}
 static void
 motoi2c_clear_status(struct motoi2c_softc *sc, uint8_t sr)
+{
 	if ((sc->sc_flags & MOTOI2C_F_STATUS_W1C) != 0) {
 		I2C_WRITE(I2CSR, sr);
 	} else {
 		I2C_WRITE(I2CSR, 0);
+	}
+}
 /* busy waiting for byte data transfer completion */
 static int
 motoi2c_busy_wait(struct motoi2c_softc *sc, uint8_t cr)
+{
 	uint8_t sr;
 	u_int timo;
 	int error = 0;
 	timo = 1000;
 	while (((sr = I2C_READ(I2CSR)) & SR_MIF) == 0 && --timo)
 		DELAY(10);
 	if (timo == 0) {
 		DPRINTF(("%s: timeout (sr=%#x, cr=%#x)\n",
 		    __func__, sr, I2C_READ(I2CCR)));
 		error = ETIMEDOUT;
+	}
 	/*
 	 * RXAK is only valid when transmitting.
 	 */
 	if ((cr & CR_MTX) && (sr & SR_RXAK)) {
 		DPRINTF(("%s: missing rx ack (%#x): spin=%u\n",
 		    __func__, sr, 1000 - timo));
 		error = EIO;
+	}
-	I2C_WRITE(I2CSR, 0);
+	motoi2c_clear_status(sc, sr);
 	return error;
+}
 int
 motoi2c_intr(void *v)
+{
 	struct motoi2c_softc * const sc = v;
 	panic("%s(%p)", __func__, sc);
 	return 0;
+}
 @@ -218,45 +240,45 @@ motoi2c_exec(void *v, i2c_op_t op, i2c_a
 	DPRINTF(("%s(%#x,%#x,%p,%zu,%p,%zu,%#x): sr=%#x cr=%#x\n",
 	    __func__, op, addr, cmdbuf, cmdlen, databuf, datalen, flags,
 	    sr, cr));
 #endif
 	if ((cr & CR_MSTA) == 0 && (sr & SR_MBB) != 0) {
 		/* wait for bus becoming available */
 		error = motoi2c_stop_wait(sc);
 		if (error)
 			return ETIMEDOUT;
+	}
 	/* reset interrupt and arbitration-lost flags (all others are RO) */
-	I2C_WRITE(I2CSR, 0);
+	motoi2c_clear_status(sc, sr);
 	sr = I2C_READ(I2CSR);
 	/*
 	 * Generate start condition
 	 */
-	cr = CR_MEN | CR_MTX | CR_MSTA;
+	cr = sc->sc_enable_mask | CR_MTX | CR_MSTA;
 	I2C_WRITE(I2CCR, cr);
 	DPRINTF(("%s: started: sr=%#x cr=%#x/%#x\n",
 	    __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR)));
 	sr = I2C_READ(I2CSR);
 	if (sr & SR_MAL) {
 		DPRINTF(("%s: lost bus: sr=%#x cr=%#x/%#x\n",
 		    __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR)));
-		I2C_WRITE(I2CCR, 0);
+		I2C_WRITE(I2CCR, sc->sc_disable_mask);
 		DELAY(10);
-		I2C_WRITE(I2CCR, CR_MEN | CR_MTX | CR_MSTA);
+		I2C_WRITE(I2CCR, sc->sc_enable_mask | CR_MTX | CR_MSTA);
 		DELAY(10);
 		sr = I2C_READ(I2CSR);
 		if (sr & SR_MAL) {
 			error = EBUSY;
 			goto out;
+		}
 		DPRINTF(("%s: reacquired bus: sr=%#x cr=%#x/%#x\n",
 		    __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR)));
+	}
 	/* send target address and transfer direction */
 	uint8_t addr_byte = (addr << 1)
 	    | (cmdlen == 0 && I2C_OP_READ_P(op) ? 1 : 0);
 @@ -319,34 +341,34 @@ motoi2c_exec(void *v, i2c_op_t op, i2c_a
 			 * the transmit acknowledge bit (I2CCR[TXAK])) before
 			 * reading the next-to-last byte of data.
 			 */
 			error = motoi2c_busy_wait(sc, cr);
 			if (error) {
 				DPRINTF(("%s: error reading byte %zu: %d\n",
 				    __func__, i, error));
 				goto out;
+			}
 			if (i == datalen - 2) {
 				cr |= CR_TXAK;
 				I2C_WRITE(I2CCR, cr);
 			} else if (i == datalen - 1 && I2C_OP_STOP_P(op)) {
-				cr = CR_MEN | CR_TXAK;
+				cr = sc->sc_enable_mask | CR_TXAK;
 				I2C_WRITE(I2CCR, cr);
+			}
 			*dataptr++ = I2C_READ(I2CDR);
+		}
 		if (datalen == 0) {
 			if (I2C_OP_STOP_P(op)) {
-				cr = CR_MEN | CR_TXAK;
+				cr = sc->sc_enable_mask | CR_TXAK;
 				I2C_WRITE(I2CCR, cr);
+			}
 			(void)I2C_READ(I2CDR);	/* dummy read */
 			error = motoi2c_busy_wait(sc, cr);
 			if (error) {
 				DPRINTF(("%s: error reading dummy last byte:"
 				    "%d\n", __func__, error));
 				goto out;
+			}
+		}
 	} else {
 		const uint8_t *dataptr = databuf;
 		for (size_t i = 0; i < datalen; i++) {
 @@ -356,25 +378,25 @@ motoi2c_exec(void *v, i2c_op_t op, i2c_a
 				DPRINTF(("%s: error sending data byte %zu:"
 				    " %d\n", __func__, i, error));
 				goto out;
+			}
+		}
+	}
  out:
 	/*
 	 * If we encountered an error condition or caller wants a STOP,
 	 * send a STOP.
 	 */
 	if (error || (cr & CR_TXAK) || ((cr & CR_MSTA) && I2C_OP_STOP_P(op))) {
-		cr = CR_MEN;
+		cr = sc->sc_enable_mask;
 		I2C_WRITE(I2CCR, cr);
 		motoi2c_stop_wait(sc);
 		DPRINTF(("%s: stopping: cr=%#x/%#x\n", __func__,
 		    cr, I2C_READ(I2CCR)));
+	}
 	DPRINTF(("%s: exit sr=%#x cr=%#x: %d\n", __func__,
 	    I2C_READ(I2CSR), I2C_READ(I2CCR), error));
 	return error;
+}

 @@ -1,14 +1,14 @@
-/* $NetBSD: motoi2cvar.h,v 1.7 2021/01/24 18:01:13 jmcneill Exp $ */
+/* $NetBSD: motoi2cvar.h,v 1.8 2021/01/25 12:08:47 jmcneill Exp $ */
 /*-
  * Copyright (c) 2007, 2010 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -42,26 +42,31 @@ struct motoi2c_settings {
 	uint8_t			i2c_adr;
 	uint8_t			i2c_fdr;
 	uint8_t			i2c_dfsrr;
 };
 struct motoi2c_softc {
 	bus_space_tag_t		sc_iot;
 	bus_space_handle_t	sc_ioh;
 	struct i2c_controller	sc_i2c;
 	motoi2c_iord_t		sc_iord;
 	motoi2c_iowr_t		sc_iowr;
 	int			sc_phandle;
 	prop_array_t		sc_child_devices;
 	int			sc_flags;
 #define	MOTOI2C_F_ENABLE_INV	__BIT(0)
 #define	MOTOI2C_F_STATUS_W1C	__BIT(1)
 	uint8_t			sc_enable_mask;
 	uint8_t			sc_disable_mask;
 };
 #define	MOTOI2C_ADR_DEFAULT	(0x7e << 1)
 #define	MOTOI2C_FDR_DEFAULT	0x31	/* 3072 */
 #define	MOTOI2C_DFSRR_DEFAULT	0x10
 #ifdef _KERNEL
 void	motoi2c_attach_common(device_t, struct motoi2c_softc *,
 	    const struct motoi2c_settings *);
 int	motoi2c_intr(void *);
 #endif
 #endif /* !_DEV_I2C_MOTOI2CVAR_H_ */