Wed Jan 27 01:47:40 2021 UTC ()
Use DEVICE_COMPAT_EOL.


(thorpej)
diff -r1.6 -r1.7 src/sys/arch/arm/altera/cycv_clkmgr.c
cvs diff -r1.6 -r1.7 src/sys/arch/arm/altera/cycv_clkmgr.c (expand / switch to unified diff)

--- src/sys/arch/arm/altera/cycv_clkmgr.c 2021/01/25 14:20:37 1.6
+++ src/sys/arch/arm/altera/cycv_clkmgr.c 2021/01/27 01:47:40 1.7
@@ -1,19 +1,19 @@ @@ -1,19 +1,19 @@
1/* $NetBSD: cycv_clkmgr.c,v 1.6 2021/01/25 14:20:37 thorpej Exp $ */ 1/* $NetBSD: cycv_clkmgr.c,v 1.7 2021/01/27 01:47:40 thorpej Exp $ */
2 2
3/* This file is in the public domain. */ 3/* This file is in the public domain. */
4 4
5#include <sys/cdefs.h> 5#include <sys/cdefs.h>
6__KERNEL_RCSID(0, "$NetBSD: cycv_clkmgr.c,v 1.6 2021/01/25 14:20:37 thorpej Exp $"); 6__KERNEL_RCSID(0, "$NetBSD: cycv_clkmgr.c,v 1.7 2021/01/27 01:47:40 thorpej Exp $");
7 7
8#include <sys/param.h> 8#include <sys/param.h>
9#include <sys/bus.h> 9#include <sys/bus.h>
10#include <sys/device.h> 10#include <sys/device.h>
11#include <sys/intr.h> 11#include <sys/intr.h>
12#include <sys/systm.h> 12#include <sys/systm.h>
13#include <sys/kernel.h> 13#include <sys/kernel.h>
14#include <sys/atomic.h> 14#include <sys/atomic.h>
15#include <sys/kmem.h> 15#include <sys/kmem.h>
16 16
17#include <dev/clk/clk_backend.h> 17#include <dev/clk/clk_backend.h>
18 18
19#include <arm/altera/cycv_reg.h> 19#include <arm/altera/cycv_reg.h>
@@ -103,27 +103,27 @@ struct cycv_clkmgr_softc { @@ -103,27 +103,27 @@ struct cycv_clkmgr_softc {
103static void cycv_clkmgr_init(struct cycv_clkmgr_softc *, int); 103static void cycv_clkmgr_init(struct cycv_clkmgr_softc *, int);
104static void cycv_clkmgr_clock_parse(struct cycv_clkmgr_softc *, int, u_int); 104static void cycv_clkmgr_clock_parse(struct cycv_clkmgr_softc *, int, u_int);
105static u_int cycv_clkmgr_clocks_traverse(struct cycv_clkmgr_softc *, int, 105static u_int cycv_clkmgr_clocks_traverse(struct cycv_clkmgr_softc *, int,
106 void (*)(struct cycv_clkmgr_softc *, int, u_int), u_int); 106 void (*)(struct cycv_clkmgr_softc *, int, u_int), u_int);
107static struct cycv_clk_mux_info *cycv_clkmgr_get_mux_info(const char *); 107static struct cycv_clk_mux_info *cycv_clkmgr_get_mux_info(const char *);
108static void cycv_clkmgr_clock_print(struct cycv_clkmgr_softc *, 108static void cycv_clkmgr_clock_print(struct cycv_clkmgr_softc *,
109 struct cycv_clk *); 109 struct cycv_clk *);
110 110
111CFATTACH_DECL_NEW(cycvclkmgr, sizeof (struct cycv_clkmgr_softc), 111CFATTACH_DECL_NEW(cycvclkmgr, sizeof (struct cycv_clkmgr_softc),
112 cycv_clkmgr_match, cycv_clkmgr_attach, NULL, NULL); 112 cycv_clkmgr_match, cycv_clkmgr_attach, NULL, NULL);
113 113
114static const struct device_compatible_entry compat_data[] = { 114static const struct device_compatible_entry compat_data[] = {
115 { .compat = "altr,clk-mgr" }, 115 { .compat = "altr,clk-mgr" },
116 { } 116 DEVICE_COMPAT_EOL
117}; 117};
118 118
119static int 119static int
120cycv_clkmgr_match(device_t parent, cfdata_t cf, void *aux) 120cycv_clkmgr_match(device_t parent, cfdata_t cf, void *aux)
121{ 121{
122 struct fdt_attach_args *faa = aux; 122 struct fdt_attach_args *faa = aux;
123 123
124 return of_match_compat_data(faa->faa_phandle, compat_data); 124 return of_match_compat_data(faa->faa_phandle, compat_data);
125} 125}
126 126
127static void 127static void
128cycv_clkmgr_attach(device_t parent, device_t self, void *aux) 128cycv_clkmgr_attach(device_t parent, device_t self, void *aux)
129{ 129{
@@ -208,27 +208,27 @@ static struct cycv_clk_mux_info { @@ -208,27 +208,27 @@ static struct cycv_clk_mux_info {
208 3, 0xac, 0x00000030 }, 208 3, 0xac, 0x00000030 },
209 209
210 /* Don't special case bypass */ 210 /* Don't special case bypass */
211 { "dbg_base_clk", { "main_pll" }, 1, 0, 0 }, 211 { "dbg_base_clk", { "main_pll" }, 1, 0, 0 },
212 /* Bug in dtb */ 212 /* Bug in dtb */
213 { "nand_clk", { "nand_x_clk" }, 1, 0, 0 }, 213 { "nand_clk", { "nand_x_clk" }, 1, 0, 0 },
214}; 214};
215 215
216static const struct device_compatible_entry clock_types[] = { 216static const struct device_compatible_entry clock_types[] = {
217 { .compat = "fixed-clock", .value = CYCV_CLK_TYPE_FIXED }, 217 { .compat = "fixed-clock", .value = CYCV_CLK_TYPE_FIXED },
218 { .compat = "altr,socfpga-pll-clock", .value = CYCV_CLK_TYPE_PLL }, 218 { .compat = "altr,socfpga-pll-clock", .value = CYCV_CLK_TYPE_PLL },
219 { .compat = "altr,socfpga-perip-clk", .value = CYCV_CLK_TYPE_PERIP }, 219 { .compat = "altr,socfpga-perip-clk", .value = CYCV_CLK_TYPE_PERIP },
220 { .compat = "altr,socfpga-gate-clk", .value = CYCV_CLK_TYPE_PERIP }, 220 { .compat = "altr,socfpga-gate-clk", .value = CYCV_CLK_TYPE_PERIP },
221 { } 221 DEVICE_COMPAT_EOL
222}; 222};
223 223
224static void 224static void
225cycv_clkmgr_clock_parse(struct cycv_clkmgr_softc *sc, int handle, u_int clkno) 225cycv_clkmgr_clock_parse(struct cycv_clkmgr_softc *sc, int handle, u_int clkno)
226{ 226{
227 struct cycv_clk *clk = &sc->sc_clocks[clkno]; 227 struct cycv_clk *clk = &sc->sc_clocks[clkno];
228 int flags = 0; 228 int flags = 0;
229 const uint8_t *buf; 229 const uint8_t *buf;
230 int len; 230 int len;
231 231
232 clk->base.domain = &sc->sc_clkdom; 232 clk->base.domain = &sc->sc_clkdom;
233 clk->base.name = fdtbus_get_string(handle, "name"); 233 clk->base.name = fdtbus_get_string(handle, "name");
234 clk->base.flags = 0; 234 clk->base.flags = 0;