 @@ -1,427 +1,427 @@
-/* $NetBSD: tegra_ahcisata.c,v 1.16 2021/01/25 14:20:38 thorpej Exp $ */
+/* $NetBSD: tegra_ahcisata.c,v 1.17 2021/01/27 01:58:15 thorpej Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.16 2021/01/25 14:20:38 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.17 2021/01/27 01:58:15 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <dev/ata/atavar.h>
 #include <dev/ic/ahcisatavar.h>
 #include <arm/nvidia/tegra_var.h>
 #include <arm/nvidia/tegra_pmcreg.h>
 #include <arm/nvidia/tegra_ahcisatareg.h>
 #include <arm/nvidia/tegra_xusbpad.h>
 #include <dev/fdt/fdtvar.h>
 #define TEGRA_AHCISATA_OFFSET	0x7000
 static int	tegra_ahcisata_match(device_t, cfdata_t, void *);
 static void	tegra_ahcisata_attach(device_t, device_t, void *);
 struct tegra_ahcisata_softc {
 	struct ahci_softc	sc;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	void			*sc_ih;
 	int			sc_phandle;
 	struct clk		*sc_clk_sata;
 	struct clk		*sc_clk_sata_oob;
 	struct clk		*sc_clk_cml1;
 	struct clk		*sc_clk_pll_e;
 	struct fdtbus_reset	*sc_rst_sata;
 	struct fdtbus_reset	*sc_rst_sata_oob;
 	struct fdtbus_reset	*sc_rst_sata_cold;
 	struct tegra_gpio_pin	*sc_pin_power;
 	const struct tegra_ahcisata_data
 				*sc_tad;
 };
 static const char * const tegra124_ahcisata_supplies[] = {
     "hvdd-supply",
     "vddio-supply",
     "avdd-supply",
     "target-5v-supply",
     "target-12v-supply"
 };
 enum tegra_ahcisata_type {
 	TEGRA124,
 	TEGRA210
 };
 struct tegra_ahcisata_data {
 	enum tegra_ahcisata_type	tad_type;
 	const char * const *		tad_supplies;
 	size_t				tad_nsupplies;
 };
 struct tegra_ahcisata_data tegra124_ahcisata_data = {
 	.tad_type = TEGRA124,
 	.tad_supplies = tegra124_ahcisata_supplies,
 	.tad_nsupplies = __arraycount(tegra124_ahcisata_supplies),
 };
 struct tegra_ahcisata_data tegra210_ahcisata_data = {
 	.tad_type = TEGRA210,
 };
 static const struct device_compatible_entry compat_data[] = {
 	{ .compat = "nvidia,tegra124-ahci", .data = &tegra124_ahcisata_data },
 	{ .compat = "nvidia,tegra210-ahci", .data = &tegra210_ahcisata_data },
-	{ },
+	DEVICE_COMPAT_EOL,
 };
 static void	tegra_ahcisata_init(struct tegra_ahcisata_softc *);
 static int	tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc *);
 CFATTACH_DECL_NEW(tegra_ahcisata, sizeof(struct tegra_ahcisata_softc),
 	tegra_ahcisata_match, tegra_ahcisata_attach, NULL, NULL);
 static int
 tegra_ahcisata_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 static void
 tegra_ahcisata_attach(device_t parent, device_t self, void *aux)
+{
 	struct tegra_ahcisata_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	bus_addr_t ahci_addr, sata_addr;
 	bus_size_t ahci_size, sata_size;
 	struct fdtbus_regulator *reg;
 	char intrstr[128];
 	int error, n;
 	if (fdtbus_get_reg(phandle, 0, &ahci_addr, &ahci_size) != 0) {
 		aprint_error(": couldn't get ahci registers\n");
 		return;
+	}
 	if (fdtbus_get_reg(phandle, 1, &sata_addr, &sata_size) != 0) {
 		aprint_error(": couldn't get sata registers\n");
 		return;
+	}
 	sc->sc_clk_sata = fdtbus_clock_get(phandle, "sata");
 	if (sc->sc_clk_sata == NULL) {
 		aprint_error(": couldn't get clock sata\n");
 		return;
+	}
 	sc->sc_clk_sata_oob = fdtbus_clock_get(phandle, "sata-oob");
 	if (sc->sc_clk_sata_oob == NULL) {
 		aprint_error(": couldn't get clock sata-oob\n");
 		return;
+	}
 	sc->sc_rst_sata = fdtbus_reset_get(phandle, "sata");
 	if (sc->sc_rst_sata == NULL) {
 		aprint_error(": couldn't get reset sata\n");
 		return;
+	}
 	sc->sc_rst_sata_oob = fdtbus_reset_get(phandle, "sata-oob");
 	if (sc->sc_rst_sata_oob == NULL) {
 		aprint_error(": couldn't get reset sata-oob\n");
 		return;
+	}
 	sc->sc_rst_sata_cold = fdtbus_reset_get(phandle, "sata-cold");
 	if(sc->sc_rst_sata_cold == NULL) {
 		aprint_error(": couldn't get reset sata-cold\n");
 		return;
+	}
 	sc->sc_tad = of_search_compatible(faa->faa_phandle, compat_data)->data;
 	if (sc->sc_tad->tad_type == TEGRA124) {
 		sc->sc_clk_cml1 = fdtbus_clock_get(phandle, "cml1");
 		if (sc->sc_clk_cml1 == NULL) {
 			aprint_error(": couldn't get clock cml1\n");
 			return;
+		}
 		sc->sc_clk_pll_e = fdtbus_clock_get(phandle, "pll_e");
 		if (sc->sc_clk_pll_e == NULL) {
 			aprint_error(": couldn't get clock pll_e\n");
 			return;
+		}
+	}
 	sc->sc_bst = faa->faa_bst;
 	error = bus_space_map(sc->sc_bst, sata_addr, sata_size, 0, &sc->sc_bsh);
 	if (error) {
 		aprint_error(": couldn't map sata registers: %d\n", error);
 		return;
+	}
 	sc->sc_phandle = faa->faa_phandle;
 	sc->sc.sc_atac.atac_dev = self;
 	sc->sc.sc_dmat = faa->faa_dmat;
 	sc->sc.sc_ahcit = faa->faa_bst;
 	sc->sc.sc_ahcis = ahci_size;
 	error = bus_space_map(sc->sc.sc_ahcit, ahci_addr, ahci_size, 0,
 	    &sc->sc.sc_ahcih);
 	if (error) {
 		aprint_error(": couldn't map ahci registers: %d\n", error);
 		return;
+	}
 	aprint_naive("\n");
 	aprint_normal(": SATA\n");
 	for (n = 0; n < sc->sc_tad->tad_nsupplies; n++) {
 		const char *supply = sc->sc_tad->tad_supplies[n];
 		reg = fdtbus_regulator_acquire(phandle, supply);
 		if (reg == NULL) {
 			aprint_error_dev(self, "couldn't acquire %s\n", supply);
 			continue;
+		}
 		if (fdtbus_regulator_enable(reg) != 0) {
 			aprint_error_dev(self, "couldn't enable %s\n", supply);
+		}
 		fdtbus_regulator_release(reg);
+	}
 	if (tegra_ahcisata_init_clocks(sc) != 0)
 		return;
 	tegra_xusbpad_sata_enable();
 	tegra_ahcisata_init(sc);
 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error_dev(self, "failed to decode interrupt\n");
 		return;
+	}
 	sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_BIO, 0,
 	    ahci_intr, &sc->sc, device_xname(self));
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(self, "failed to establish interrupt on %s\n",
 		    intrstr);
 		return;
+	}
 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
 	ahci_attach(&sc->sc);
+}
 static void
 tegra_ahcisata_init(struct tegra_ahcisata_softc *sc)
+{
 	bus_space_tag_t bst = sc->sc_bst;
 	bus_space_handle_t bsh = sc->sc_bsh;
 	/* Set RX idle detection source and disable RX idle detection interrupt */
 	tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG,
 	    TEGRA_SATA_AUX_MISC_CNTL_1_AUX_OR_CORE_IDLE_STATUS_SEL, 0);
 	tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_RX_STAT_INT_REG,
 	    TEGRA_SATA_AUX_RX_STAT_INT_SATA_RX_STAT_INT_DISABLE, 0);
 	/* Prevent automatic OOB sequence when coming out of reset */
 	tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG,
 , TEGRA_SATA_AUX_MISC_CNTL_1_OOB_ON_POR);
 	/* Disable device sleep */
 	tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG,
 , TEGRA_SATA_AUX_MISC_CNTL_1_SDS_SUPPORT);
 	/* Enable IFPS device block */
 	tegra_reg_set_clear(bst, bsh, TEGRA_SATA_CONFIGURATION_REG,
 	    TEGRA_SATA_CONFIGURATION_EN_FPCI, 0);
 	/* Electrical settings for better link stability */
 	bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL17_REG, 0x55010000);
 	bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL18_REG, 0x55010000);
 	bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL20_REG, 1);
 	bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL21_REG, 1);
 	tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_PHY_0_REG,
 	    TEGRA_T_SATA0_CFG_PHY_0_MASK_SQUELCH,
 	    TEGRA_T_SATA0_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD);
 	tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_NVOOB_REG,
 	    __SHIFTIN(0x7, TEGRA_T_SATA0_NVOOB_COMMA_CNT) |
 	    __SHIFTIN(0x3, TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH) |
 	    __SHIFTIN(0x1, TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_MODE),
 	    TEGRA_T_SATA0_NVOOB_COMMA_CNT |
 	    TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
 	    TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
 	tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_2NVOOB_2_REG,
 	    __SHIFTIN(0xc, TEGRA_T_SATA0_CFG_2NVOOB_2_COMWAKE_IDLE_CNT_LOW),
 	    TEGRA_T_SATA0_CFG_2NVOOB_2_COMWAKE_IDLE_CNT_LOW);
 	if (sc->sc_tad->tad_type == TEGRA124) {
 		const u_int gen1_tx_amp = 0x18;
 		const u_int gen1_tx_peak = 0x04;
 		const u_int gen2_tx_amp = 0x18;
 		const u_int gen2_tx_peak = 0x0a;
 		/* PHY config */
 		bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG,
 		    TEGRA_T_SATA0_INDEX_CH1);
 		tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_REG,
 		    __SHIFTIN(gen1_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP) |
 		    __SHIFTIN(gen1_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK),
 		    TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP |
 		    TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK);
 		tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_REG,
 		    __SHIFTIN(gen2_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP) |
 		    __SHIFTIN(gen2_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK),
 		    TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP |
 		    TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK);
 		bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL11_REG,
 		    __SHIFTIN(0x2800, TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ));
 		bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL2_REG,
 		    __SHIFTIN(0x23, TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1));
 		bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG, 0);
+	}
 	/* Backdoor update the programming interface field and class code */
 	tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG,
 	    TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN, 0);
 	bus_space_write_4(bst, bsh, TEGRA_T_SATA0_BKDOOR_CC_REG,
 	    __SHIFTIN(0x0106, TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE) |
 	    __SHIFTIN(0x1, TEGRA_T_SATA0_BKDOOR_CC_PROG_IF));
 	tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG,
 , TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN);
 	tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_REG,
 	    TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
 	    TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM |
 	    TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
 	    TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP, 0);
 	tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_PHY_1_REG,
 	    TEGRA_T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
 	    TEGRA_T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN, 0);
 	/* Enable IFPS device block */
 	tegra_reg_set_clear(bst, bsh, TEGRA_SATA_CONFIGURATION_REG,
 , TEGRA_SATA_CONFIGURATION_CLKEN_OVERRIDE);
 	/* Enable access and bus mastering */
 	tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG1_REG,
 	    TEGRA_T_SATA0_CFG1_SERR |
 	    TEGRA_T_SATA0_CFG1_BUS_MASTER |
 	    TEGRA_T_SATA0_CFG1_MEM_SPACE |
 	    TEGRA_T_SATA0_CFG1_IO_SPACE,
 );
 	/* MMIO setup */
 	bus_space_write_4(bst, bsh, TEGRA_SATA_FPCI_BAR5_REG,
 	    __SHIFTIN(0x10000, TEGRA_SATA_FPCI_BAR_START) |
 	    TEGRA_SATA_FPCI_BAR_ACCESS_TYPE);
 	bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CFG9_REG,
 	    __SHIFTIN(0x8000, TEGRA_T_SATA0_CFG9_BASE_ADDRESS));
 	/* Enable interrupts */
 	tegra_reg_set_clear(bst, bsh, TEGRA_SATA_INTR_MASK_REG,
 	    TEGRA_SATA_INTR_MASK_IP_INT, 0);
+}
 static int
 tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc *sc)
+{
 	device_t self = sc->sc.sc_atac.atac_dev;
 	int error;
 	/* Assert resets */
 	fdtbus_reset_assert(sc->sc_rst_sata);
 	fdtbus_reset_assert(sc->sc_rst_sata_cold);
 	/* Set SATA_OOB clock source to 204MHz */
 	error = clk_set_rate(sc->sc_clk_sata_oob, 204000000);
 	if (error) {
 		aprint_error_dev(self, "couldn't set sata-oob rate: %d\n",
 		    error);
 		return error;
+	}
 	/* Set SATA clock source to 102MHz */
 	error = clk_set_rate(sc->sc_clk_sata, 102000000);
 	if (error) {
 		aprint_error_dev(self, "couldn't set sata rate: %d\n", error);
 		return error;
+	}
 	/* Ungate SAX partition in the PMC */
 	tegra_pmc_power(PMC_PARTID_SAX, true);
 	delay(20);
 	/* Remove clamping from SAX partition in the PMC */
 	tegra_pmc_remove_clamping(PMC_PARTID_SAX);
 	delay(20);
 	/* Un-gate clocks for SATA */
 	error = clk_enable(sc->sc_clk_sata);
 	if (error) {
 		aprint_error_dev(self, "couldn't enable sata: %d\n", error);
 		return error;
+	}
 	error = clk_enable(sc->sc_clk_sata_oob);
 	if (error) {
 		aprint_error_dev(self, "couldn't enable sata-oob: %d\n", error);
 		return error;
+	}
 	if (sc->sc_clk_cml1) {
 		/* Enable CML clock for SATA */
 		error = clk_enable(sc->sc_clk_cml1);
 		if (error) {
 			aprint_error_dev(self, "couldn't enable cml1: %d\n", error);
 			return error;
+		}
+	}
 	/* Enable PHYs */
 	struct fdtbus_phy *phy;
 	for (u_int n = 0; (phy = fdtbus_phy_get_index(sc->sc_phandle, n)) != NULL; n++)
 		if (fdtbus_phy_enable(phy, true) != 0)
 			aprint_error_dev(self, "failed to enable PHY #%d\n", n);
 	/* De-assert resets */
 	fdtbus_reset_deassert(sc->sc_rst_sata);
 	fdtbus_reset_deassert(sc->sc_rst_sata_cold);
 	return 0;
+}

 @@ -1,818 +1,818 @@
-/* $NetBSD: tegra_pcie.c,v 1.34 2021/01/25 14:20:38 thorpej Exp $ */
+/* $NetBSD: tegra_pcie.c,v 1.35 2021/01/27 01:58:15 thorpej Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.34 2021/01/25 14:20:38 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.35 2021/01/27 01:58:15 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/kmem.h>
 #include <sys/kernel.h>
 #include <sys/lwp.h>
 #include <sys/mutex.h>
 #include <sys/queue.h>
 #include <sys/systm.h>
 #include <machine/cpu.h>
 #include <arm/cpufunc.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pciconf.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_pciereg.h>
 #include <arm/nvidia/tegra_pmcreg.h>
 #include <arm/nvidia/tegra_var.h>
 #include <dev/fdt/fdtvar.h>
 /* Interrupt handle flags */
 #define	IH_MPSAFE	0x80000000
 static int	tegra_pcie_match(device_t, cfdata_t, void *);
 static void	tegra_pcie_attach(device_t, device_t, void *);
 #define TEGRA_PCIE_NBUS 256
 #define TEGRA_PCIE_ECFB (1<<(12 - 8))	/* extended conf frags per bus */
 enum tegra_pcie_type {
 	TEGRA_PCIE_124		= 0,
 	TEGRA_PCIE_210		= 1,
 };
 struct tegra_pcie_ih {
 	int			(*ih_callback)(void *);
 	void			*ih_arg;
 	int			ih_ipl;
 	int			ih_mpsafe;
 	TAILQ_ENTRY(tegra_pcie_ih) ih_entry;
 };
 struct tegra_pcie_softc {
 	device_t		sc_dev;
 	bus_dma_tag_t		sc_dmat;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh_afi;
 	bus_space_handle_t	sc_bsh_pads;
 	bus_space_handle_t	sc_bsh_rpconf;
 	int			sc_phandle;
 	enum tegra_pcie_type	sc_type;
 	struct arm32_pci_chipset sc_pc;
 	void			*sc_ih;
 	kmutex_t		sc_lock;
 	TAILQ_HEAD(, tegra_pcie_ih) sc_intrs;
 	u_int			sc_intrgen;
 	bus_space_handle_t	sc_bsh_extc[TEGRA_PCIE_NBUS-1][TEGRA_PCIE_ECFB];
 };
 static int	tegra_pcie_intr(void *);
 static void	tegra_pcie_init(pci_chipset_tag_t, void *);
 static void	tegra_pcie_enable(struct tegra_pcie_softc *);
 static void	tegra_pcie_enable_ports(struct tegra_pcie_softc *);
 static void	tegra_pcie_enable_clocks(struct tegra_pcie_softc *);
 static void	tegra_pcie_setup(struct tegra_pcie_softc * const);
 static void	tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const,
 					 uint, uint);
 static void	tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const, uint);
 static void	tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const);
 static void	tegra_pcie_attach_hook(device_t, device_t,
 				       struct pcibus_attach_args *);
 static int	tegra_pcie_bus_maxdevs(void *, int);
 static pcitag_t	tegra_pcie_make_tag(void *, int, int, int);
 static void	tegra_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *);
 static pcireg_t	tegra_pcie_conf_read(void *, pcitag_t, int);
 static void	tegra_pcie_conf_write(void *, pcitag_t, int, pcireg_t);
 static int	tegra_pcie_conf_hook(void *, int, int, int, pcireg_t);
 static void	tegra_pcie_conf_interrupt(void *, int, int, int, int, int *);
 static int	tegra_pcie_intr_map(const struct pci_attach_args *,
 				    pci_intr_handle_t *);
 static const char *tegra_pcie_intr_string(void *, pci_intr_handle_t,
 					  char *, size_t);
 const struct evcnt *tegra_pcie_intr_evcnt(void *, pci_intr_handle_t);
 static int	tegra_pcie_intr_setattr(void *, pci_intr_handle_t *, int,
 					uint64_t);
 static void *	tegra_pcie_intr_establish(void *, pci_intr_handle_t,
 					 int, int (*)(void *), void *,
 					 const char *);
 static void	tegra_pcie_intr_disestablish(void *, void *);
 CFATTACH_DECL_NEW(tegra_pcie, sizeof(struct tegra_pcie_softc),
 	tegra_pcie_match, tegra_pcie_attach, NULL, NULL);
 static const struct device_compatible_entry compat_data[] = {
 	{ .compat = "nvidia,tegra210-pcie",	.value = TEGRA_PCIE_210 },
 	{ .compat = "nvidia,tegra124-pcie",	.value = TEGRA_PCIE_124 },
-	{ }
+	DEVICE_COMPAT_EOL
 };
 static int
 tegra_pcie_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 static void
 tegra_pcie_attach(device_t parent, device_t self, void *aux)
+{
 	struct tegra_pcie_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const struct device_compatible_entry *dce;
 	struct pciconf_resources *pcires;
 	struct pcibus_attach_args pba;
 	bus_addr_t afi_addr, cs_addr, pads_addr;
 	bus_size_t afi_size, cs_size, pads_size;
 	char intrstr[128];
 	int error;
 	if (fdtbus_get_reg_byname(faa->faa_phandle, "afi", &afi_addr, &afi_size) != 0) {
 		aprint_error(": couldn't get afi registers\n");
 		return;
+	}
 	if (fdtbus_get_reg_byname(faa->faa_phandle, "pads", &pads_addr, &pads_size) != 0) {
 		aprint_error(": couldn't get pads registers\n");
 		return;
+	}
 #if notyet
 	if (fdtbus_get_reg(faa->faa_phandle, 2, &cs_addr, &cs_size) != 0) {
 		aprint_error(": couldn't get cs registers\n");
 		return;
+	}
 #else
 	cs_addr = TEGRA_PCIE_RPCONF_BASE;
 	cs_size = TEGRA_PCIE_RPCONF_SIZE;
 #endif
 	sc->sc_dev = self;
 	sc->sc_dmat = faa->faa_dmat;
 	sc->sc_bst = faa->faa_bst;
 	sc->sc_phandle = faa->faa_phandle;
 	error = bus_space_map(sc->sc_bst, afi_addr, afi_size, 0,
 	    &sc->sc_bsh_afi);
 	if (error) {
 		aprint_error(": couldn't map afi registers: %d\n", error);
 		return;
+	}
 	error = bus_space_map(sc->sc_bst, pads_addr, pads_size, 0,
 	    &sc->sc_bsh_pads);
 	if (error) {
 		aprint_error(": couldn't map pads registers: %d\n", error);
 		return;
+	}
 	error = bus_space_map(sc->sc_bst, cs_addr, cs_size,
 	    _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, &sc->sc_bsh_rpconf);
 	if (error) {
 		aprint_error(": couldn't map cs registers: %d\n", error);
 		return;
+	}
 	dce = of_search_compatible(faa->faa_phandle, compat_data);
 	KASSERT(dce != NULL);
 	sc->sc_type = dce->value;
 	tegra_pcie_conf_map_buses(sc);
 	TAILQ_INIT(&sc->sc_intrs);
 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
 	aprint_naive("\n");
 	aprint_normal(": PCIE\n");
 	tegra_pmc_power(PMC_PARTID_PCX, true);
 	tegra_pmc_remove_clamping(PMC_PARTID_PCX);
 	tegra_pcie_enable_clocks(sc);
 	if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error_dev(self, "failed to decode interrupt\n");
 		return;
+	}
 	sc->sc_ih = fdtbus_intr_establish_xname(faa->faa_phandle, 0, IPL_VM,
 	    FDT_INTR_MPSAFE, tegra_pcie_intr, sc, device_xname(self));
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(self, "failed to establish interrupt on %s\n",
 		    intrstr);
 		return;
+	}
 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
 	tegra_pcie_setup(sc);
 	tegra_pcie_init(&sc->sc_pc, sc);
 	pcires = pciconf_resource_init();
 	pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
 	    TEGRA_PCIE_IO_BASE, TEGRA_PCIE_IO_SIZE);
 	pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
 	    TEGRA_PCIE_MEM_BASE, TEGRA_PCIE_MEM_SIZE);
 	pciconf_resource_add(pcires, PCICONF_RESOURCE_PREFETCHABLE_MEM,
 	    TEGRA_PCIE_PMEM_BASE, TEGRA_PCIE_PMEM_SIZE);
 	error = pci_configure_bus(&sc->sc_pc, pcires, 0,
 	    arm_dcache_align);
 	pciconf_resource_fini(pcires);
 	if (error) {
 		aprint_error_dev(self, "configuration failed (%d)\n",
 		    error);
 		return;
+	}
 	tegra_pcie_enable(sc);
 	tegra_pcie_enable_ports(sc);
 	memset(&pba, 0, sizeof(pba));
 	pba.pba_flags = PCI_FLAGS_MRL_OKAY |
 			PCI_FLAGS_MRM_OKAY |
 			PCI_FLAGS_MWI_OKAY |
 			PCI_FLAGS_MEM_OKAY |
 			PCI_FLAGS_IO_OKAY;
 	pba.pba_iot = sc->sc_bst;
 	pba.pba_memt = sc->sc_bst;
 	pba.pba_dmat = sc->sc_dmat;
 	pba.pba_pc = &sc->sc_pc;
 	pba.pba_bus = 0;
 	config_found_ia(self, "pcibus", &pba, pcibusprint);
+}
 static int
 tegra_pcie_legacy_intr(struct tegra_pcie_softc *sc)
+{
 	const uint32_t msg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi,
 	    AFI_MSG_REG);
 	struct tegra_pcie_ih *pcie_ih;
 	int rv = 0;
 	if (msg & (AFI_MSG_INT0|AFI_MSG_INT1)) {
 		mutex_enter(&sc->sc_lock);
 		const u_int lastgen = sc->sc_intrgen;
 		TAILQ_FOREACH(pcie_ih, &sc->sc_intrs, ih_entry) {
 			int (*callback)(void *) = pcie_ih->ih_callback;
 			void *arg = pcie_ih->ih_arg;
 			const int mpsafe = pcie_ih->ih_mpsafe;
 			mutex_exit(&sc->sc_lock);
 			if (!mpsafe)
 				KERNEL_LOCK(1, curlwp);
 			rv += callback(arg);
 			if (!mpsafe)
 				KERNEL_UNLOCK_ONE(curlwp);
 			mutex_enter(&sc->sc_lock);
 			if (lastgen != sc->sc_intrgen)
 				break;
+		}
 		mutex_exit(&sc->sc_lock);
 	} else if (msg & (AFI_MSG_PM_PME0|AFI_MSG_PM_PME1)) {
 		device_printf(sc->sc_dev, "PM PME message; AFI_MSG=%08x\n",
 		    msg);
 	} else {
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_MSG_REG, msg);
 		rv = 1;
+	}
 	return rv;
+}
 static int
 tegra_pcie_intr(void *priv)
+{
 	struct tegra_pcie_softc *sc = priv;
 	int rv;
 	const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi,
 	    AFI_INTR_CODE_REG);
 	const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi,
 	    AFI_INTR_SIGNATURE_REG);
 	switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) {
 	case AFI_INTR_CODE_SM_MSG:
 		rv = tegra_pcie_legacy_intr(sc);
 		break;
 	default:
 		device_printf(sc->sc_dev, "intr: code %#x sig %#x\n",
 		    code, sig);
 		rv = 1;
 		break;
+	}
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0);
 	return rv;
+}
 static void
 tegra_pcie_enable_clocks(struct tegra_pcie_softc * const sc)
+{
 	const char *clock_names[] = { "pex", "afi", "pll_e", "cml" };
 	const char *reset_names[] = { "pex", "afi", "pcie_x" };
 	struct fdtbus_reset *rst;
 	struct clk *clk;
 	int n;
 	for (n = 0; n < __arraycount(clock_names); n++) {
 		clk = fdtbus_clock_get(sc->sc_phandle, clock_names[n]);
 		if (clk == NULL || clk_enable(clk) != 0)
 			aprint_error_dev(sc->sc_dev, "couldn't enable clock %s\n",
 			    clock_names[n]);
+	}
 	for (n = 0; n < __arraycount(reset_names); n++) {
 		rst = fdtbus_reset_get(sc->sc_phandle, reset_names[n]);
 		if (rst == NULL || fdtbus_reset_deassert(rst) != 0)
 			aprint_error_dev(sc->sc_dev, "couldn't de-assert reset %s\n",
 			    reset_names[n]);
+	}
+}
 #if 0
 static void
 tegra_pcie_reset_port(struct tegra_pcie_softc * const sc, int index)
+{
 	uint32_t val;
 	val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index));
 	val &= ~AFI_PEXn_CTRL_RST_L;
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val);
 	delay(2000);
 	val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index));
 	val |= AFI_PEXn_CTRL_RST_L;
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val);
+}
 #endif
 static void
 tegra_pcie_enable_ports(struct tegra_pcie_softc * const sc)
+{
 	struct fdtbus_phy *phy;
 	const u_int *data;
 	int child, len, n;
 	uint32_t val;
 	for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) {
 		if (!fdtbus_status_okay(child))
 			continue;
 		/* Enable PHYs */
 		for (n = 0; (phy = fdtbus_phy_get_index(child, n)) != NULL; n++)
 			if (fdtbus_phy_enable(phy, true) != 0)
 				aprint_error_dev(sc->sc_dev, "couldn't enable %s phy #%d\n",
 				    fdtbus_get_string(child, "name"), n);
 		data = fdtbus_get_prop(child, "reg", &len);
 		if (data == NULL || len < 4)
 			continue;
 		const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1;
 		val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index));
 		val |= AFI_PEXn_CTRL_CLKREQ_EN;
 		val |= AFI_PEXn_CTRL_REFCLK_EN;
 		val |= AFI_PEXn_CTRL_REFCLK_OVERRIDE_EN;
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val);
 #if 0
 		tegra_pcie_reset_port(sc, index);
 #endif
+	}
+}
 static void
 tegra_pcie_setup(struct tegra_pcie_softc * const sc)
+{
 	uint32_t val, cfg, lanes;
 	int child, len;
 	const u_int *data;
 	size_t i;
 	/* Enable PLLE control */
 	val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG);
 	val &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
 	val |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG, val);
 	/* Disable PEX clock bias pad power down */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXBIAS_CTRL_REG, 0);
 	/* Configure PCIE mode and enable ports */
 	cfg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG);
 	cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(0);
 	cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(1);
 	cfg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG;
 	lanes = 0;
 	for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) {
 		if (!fdtbus_status_okay(child))
 			continue;
 		data = fdtbus_get_prop(child, "reg", &len);
 		if (data == NULL || len < 4)
 			continue;
 		const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1;
 		if (of_getprop_uint32(child, "nvidia,num-lanes", &val) != 0)
 			continue;
 		lanes |= (val << (index << 3));
 		cfg &= ~AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(index);
+	}
 	switch (lanes) {
 	case 0x0104:
 		aprint_normal_dev(sc->sc_dev, "lane config: x4 x1\n");
 		cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_4_1,
 				 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG);
 		break;
 	case 0x0102:
 		aprint_normal_dev(sc->sc_dev, "lane config: x2 x1\n");
 		cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_2_1,
 				 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG);
 		break;
+	}
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG, cfg);
 	/* Configure refclk pad */
 	if (sc->sc_type == TEGRA_PCIE_124) {
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads,
 		    PADS_REFCLK_CFG0_REG, 0x44ac44ac);
+	}
 	if (sc->sc_type == TEGRA_PCIE_210) {
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads,
 		    PADS_REFCLK_CFG0_REG, 0x90b890b8);
+	}
 	/*
 	 * Map PCI address spaces into ARM address space via
 	 * HyperTransport-like "FPCI".
 	 */
 	static const struct { uint32_t size, base, fpci; } pcie_init_table[] = {
 		/*
 		 * === BEWARE ===
+		 *
 		 * We depend on our TEGRA_PCIE_IO window overlaping the
 		 * TEGRA_PCIE_A1 window to allow us to use the same
 		 * bus_space_tag for both PCI IO and Memory spaces.
+		 *
 		 * 0xfdfc000000-0xfdfdffffff is the FPCI/HyperTransport
 		 * mapping for 0x0000000-0x1ffffff of PCI IO space.
 		 */
 		{ TEGRA_PCIE_IO_SIZE >> 12, TEGRA_PCIE_IO_BASE,
 		  (0xfdfc000000 + TEGRA_PCIE_IO_BASE) >> 8 | 0, },
 		/* HyperTransport Technology Type 1 Address Format */
 		{ TEGRA_PCIE_CONF_SIZE >> 12, TEGRA_PCIE_CONF_BASE,
 xfdff000000 >> 8 | 0, },
 		/* 1:1 MMIO mapping */
 		{ TEGRA_PCIE_MEM_SIZE >> 12, TEGRA_PCIE_MEM_BASE,
 		  TEGRA_PCIE_MEM_BASE >> 8 | 1, },
 		/* Extended HyperTransport Technology Type 1 Address Format */
 		{ TEGRA_PCIE_EXTC_SIZE >> 12, TEGRA_PCIE_EXTC_BASE,
 xfe10000000 >> 8 | 0, },
 		/* 1:1 prefetchable MMIO mapping */
 		{ TEGRA_PCIE_PMEM_SIZE >> 12, TEGRA_PCIE_PMEM_BASE,
 		  TEGRA_PCIE_PMEM_BASE >> 8 | 1, },
 	};
 	for (i = 0; i < AFI_AXI_NBAR; i++) {
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi,
 		    AFI_AXI_BARi_SZ(i), 0);
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi,
 		    AFI_AXI_BARi_START(i), 0);
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi,
 		    AFI_FPCI_BARi(i), 0);
+	}
 	for (i = 0; i < __arraycount(pcie_init_table); i++) {
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi,
 		    AFI_AXI_BARi_START(i), pcie_init_table[i].base);
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi,
 		    AFI_FPCI_BARi(i), pcie_init_table[i].fpci);
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi,
 		    AFI_AXI_BARi_SZ(i), pcie_init_table[i].size);
+	}
+}
 static void
 tegra_pcie_enable(struct tegra_pcie_softc *sc)
+{
 	/* disable MSI */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi,
 	    AFI_MSI_BAR_SZ_REG, 0);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi,
 	    AFI_MSI_FPCI_BAR_ST_REG, 0);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi,
 	    AFI_MSI_AXI_BAR_ST_REG, 0);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi,
 	    AFI_SM_INTR_ENABLE_REG, 0xffffffff);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi,
 	    AFI_AFI_INTR_ENABLE_REG, 0);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi,
 	    AFI_INTR_MASK_REG, AFI_INTR_MASK_INT);
+}
 static void
 tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const sc, uint bus,
     uint frg)
+{
 	bus_addr_t a;
 	KASSERT(bus >= 1);
 	KASSERT(bus < TEGRA_PCIE_NBUS);
 	KASSERT(frg < TEGRA_PCIE_ECFB);
 	if (sc->sc_bsh_extc[bus-1][frg] != 0) {
 		device_printf(sc->sc_dev, "bus %u fragment %#x already "
 		    "mapped\n", bus, frg);
 		return;
+	}
 	a = TEGRA_PCIE_EXTC_BASE + (bus << 16) + (frg << 24);
 	if (bus_space_map(sc->sc_bst, a, 1 << 16,
 	    _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED,
 	    &sc->sc_bsh_extc[bus-1][frg]) != 0)
 		device_printf(sc->sc_dev, "couldn't map PCIE "
 		    "configuration for bus %u fragment %#x", bus, frg);
+}
 /* map non-non-extended configuration space for full bus range */
 static void
 tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const sc, uint bus)
+{
 	uint i;
 	for (i = 1; i < TEGRA_PCIE_ECFB; i++) {
 		tegra_pcie_conf_frag_map(sc, bus, i);
+	}
+}
 /* map non-extended configuration space for full bus range */
 static void
 tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const sc)
+{
 	uint b;
 	for (b = 1; b < TEGRA_PCIE_NBUS; b++) {
 		tegra_pcie_conf_frag_map(sc, b, 0);
+	}
+}
 void
 tegra_pcie_init(pci_chipset_tag_t pc, void *priv)
+{
 	pc->pc_conf_v = priv;
 	pc->pc_attach_hook = tegra_pcie_attach_hook;
 	pc->pc_bus_maxdevs = tegra_pcie_bus_maxdevs;
 	pc->pc_make_tag = tegra_pcie_make_tag;
 	pc->pc_decompose_tag = tegra_pcie_decompose_tag;
 	pc->pc_conf_read = tegra_pcie_conf_read;
 	pc->pc_conf_write = tegra_pcie_conf_write;
 	pc->pc_conf_hook = tegra_pcie_conf_hook;
 	pc->pc_conf_interrupt = tegra_pcie_conf_interrupt;
 	pc->pc_intr_v = priv;
 	pc->pc_intr_map = tegra_pcie_intr_map;
 	pc->pc_intr_string = tegra_pcie_intr_string;
 	pc->pc_intr_evcnt = tegra_pcie_intr_evcnt;
 	pc->pc_intr_setattr = tegra_pcie_intr_setattr;
 	pc->pc_intr_establish = tegra_pcie_intr_establish;
 	pc->pc_intr_disestablish = tegra_pcie_intr_disestablish;
+}
 static void
 tegra_pcie_attach_hook(device_t parent, device_t self,
     struct pcibus_attach_args *pba)
+{
 	const pci_chipset_tag_t pc = pba->pba_pc;
 	struct tegra_pcie_softc * const sc = pc->pc_conf_v;
 	if (pba->pba_bus >= 1) {
 		tegra_pcie_conf_map_bus(sc, pba->pba_bus);
+	}
+}
 static int
 tegra_pcie_bus_maxdevs(void *v, int busno)
+{
 	return busno == 0 ? 2 : 32;
+}
 static pcitag_t
 tegra_pcie_make_tag(void *v, int b, int d, int f)
+{
 	return (b << 16) | (d << 11) | (f << 8);
+}
 static void
 tegra_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
+{
 	if (bp)
 		*bp = (tag >> 16) & 0xff;
 	if (dp)
 		*dp = (tag >> 11) & 0x1f;
 	if (fp)
 		*fp = (tag >> 8) & 0x7;
+}
 static pcireg_t
 tegra_pcie_conf_read(void *v, pcitag_t tag, int offset)
+{
 	struct tegra_pcie_softc *sc = v;
 	bus_space_handle_t bsh;
 	int b, d, f;
 	u_int reg;
 	if ((unsigned int)offset >= PCI_EXTCONF_SIZE)
 		return (pcireg_t) -1;
 	tegra_pcie_decompose_tag(v, tag, &b, &d, &f);
 	if (b >= TEGRA_PCIE_NBUS)
 		return (pcireg_t) -1;
 	if (b == 0) {
 		if (d >= 2 || f != 0)
 			return (pcireg_t) -1;
 		reg = d * 0x1000 + offset;
 		bsh = sc->sc_bsh_rpconf;
 	} else {
 		reg = (d << 11) | (f << 8) | (offset & 0xff);
 		bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf];
 		if (bsh == 0)
 			return (pcireg_t) -1;
+	}
 	return bus_space_read_4(sc->sc_bst, bsh, reg);
+}
 static void
 tegra_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
+{
 	struct tegra_pcie_softc *sc = v;
 	bus_space_handle_t bsh;
 	int b, d, f;
 	u_int reg;
 	if ((unsigned int)offset >= PCI_EXTCONF_SIZE)
 		return;
 	tegra_pcie_decompose_tag(v, tag, &b, &d, &f);
 	if (b >= TEGRA_PCIE_NBUS)
 		return;
 	if (b == 0) {
 		if (d >= 2 || f != 0)
 			return;
 		reg = d * 0x1000 + offset;
 		bsh = sc->sc_bsh_rpconf;
 	} else {
 		reg = (d << 11) | (f << 8) | (offset & 0xff);
 		bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf];
 		if (bsh == 0)
 			return;
+	}
 	bus_space_write_4(sc->sc_bst, bsh, reg, val);
+}
 static int
 tegra_pcie_conf_hook(void *v, int b, int d, int f, pcireg_t id)
+{
 	return PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM;
+}
 static void
 tegra_pcie_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz,
     int *ilinep)
+{
 	*ilinep = 5;
+}
 static int
 tegra_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih)
+{
 	if (pa->pa_intrpin == 0)
 		return EINVAL;
 	*ih = pa->pa_intrpin;
 	return 0;
+}
 static const char *
 tegra_pcie_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
+{
 	struct tegra_pcie_softc *sc = v;
 	if (ih == PCI_INTERRUPT_PIN_NONE)
 		return NULL;
 	if (!fdtbus_intr_str(sc->sc_phandle, 0, buf, len))
 		return NULL;
 	return buf;
+}
 const struct evcnt *
 tegra_pcie_intr_evcnt(void *v, pci_intr_handle_t ih)
+{
 	return NULL;
+}
 static int
 tegra_pcie_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data)
+{
 	switch (attr) {
 	case PCI_INTR_MPSAFE:
 		if (data)
 			*ih |= IH_MPSAFE;
 		else
 			*ih &= ~IH_MPSAFE;
 		return 0;
 	default:
 		return ENODEV;
+	}
+}
 static void *
 tegra_pcie_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
     int (*callback)(void *), void *arg, const char *xname)
+{
 	struct tegra_pcie_softc *sc = v;
 	struct tegra_pcie_ih *pcie_ih;
 	if (ih == 0)
 		return NULL;
 	pcie_ih = kmem_alloc(sizeof(*pcie_ih), KM_SLEEP);
 	pcie_ih->ih_callback = callback;
 	pcie_ih->ih_arg = arg;
 	pcie_ih->ih_ipl = ipl;
 	pcie_ih->ih_mpsafe = (ih & IH_MPSAFE) != 0;
 	mutex_enter(&sc->sc_lock);
 	TAILQ_INSERT_TAIL(&sc->sc_intrs, pcie_ih, ih_entry);
 	sc->sc_intrgen++;
 	mutex_exit(&sc->sc_lock);
 	return pcie_ih;
+}
 static void
 tegra_pcie_intr_disestablish(void *v, void *vih)
+{
 	struct tegra_pcie_softc *sc = v;
 	struct tegra_pcie_ih *pcie_ih = vih;
 	mutex_enter(&sc->sc_lock);
 	TAILQ_REMOVE(&sc->sc_intrs, pcie_ih, ih_entry);
 	mutex_exit(&sc->sc_lock);
 	kmem_free(pcie_ih, sizeof(*pcie_ih));
+}

 @@ -1,407 +1,407 @@
-/* $NetBSD: tegra_soctherm.c,v 1.11 2021/01/25 14:20:38 thorpej Exp $ */
+/* $NetBSD: tegra_soctherm.c,v 1.12 2021/01/27 01:58:15 thorpej Exp $ */
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_soctherm.c,v 1.11 2021/01/25 14:20:38 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_soctherm.c,v 1.12 2021/01/27 01:58:15 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/kmem.h>
 #include <dev/sysmon/sysmonvar.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_socthermreg.h>
 #include <arm/nvidia/tegra_var.h>
 #include <dev/fdt/fdtvar.h>
 #define FUSE_TSENSOR_CALIB_CP_TS_BASE	__BITS(12,0)
 #define FUSE_TSENSOR_CALIB_FT_TS_BASE	__BITS(25,13)
 #define FUSE_TSENSOR8_CALIB_REG		0x180
 #define FUSE_TSENSOR8_CALIB_CP_TS_BASE	__BITS(9,0)
 #define FUSE_TSENSOR8_CALIB_FT_TS_BASE	__BITS(20,10)
 #define FUSE_SPARE_REALIGNMENT_REG	0x1fc
 #define FUSE_SPARE_REALIGNMENT_CP	__BITS(5,0)
 #define FUSE_SPARE_REALIGNMENT_FT	__BITS(25,21)
 static int	tegra_soctherm_match(device_t, cfdata_t, void *);
 static void	tegra_soctherm_attach(device_t, device_t, void *);
 struct tegra_soctherm_config {
 	uint32_t init_pdiv;
 	uint32_t init_hotspot_off;
 	uint32_t nominal_calib_ft;
 	uint32_t nominal_calib_cp;
 	uint32_t tall;
 	uint32_t tsample;
 	uint32_t tiddq_en;
 	uint32_t ten_count;
 	uint32_t pdiv;
 	uint32_t tsample_ate;
 	uint32_t pdiv_ate;
 };
 static const struct tegra_soctherm_config tegra124_soctherm_config = {
 	.init_pdiv = 0x8888,
 	.init_hotspot_off = 0x60600,
 	.nominal_calib_ft = 105,
 	.nominal_calib_cp = 25,
 	.tall = 16300,
 	.tsample = 120,
 	.tiddq_en = 1,
 	.ten_count = 1,
 	.pdiv = 8,
 	.tsample_ate = 480,
 	.pdiv_ate = 8
 };
 struct tegra_soctherm_sensor {
 	envsys_data_t		s_data;
 	u_int			s_base;
 	u_int			s_fuse;
 	int			s_fuse_corr_alpha;
 	int			s_fuse_corr_beta;
 	int16_t			s_therm_a;
 	int16_t			s_therm_b;
 };
 static const struct tegra_soctherm_sensor tegra_soctherm_sensors[] = {
 	{ .s_data = { .desc = "CPU0" }, .s_base = 0x0c0, .s_fuse = 0x098,
 	  .s_fuse_corr_alpha = 1135400, .s_fuse_corr_beta = -6266900 },
 	{ .s_data = { .desc = "CPU1" }, .s_base = 0x0e0, .s_fuse = 0x084,
 	  .s_fuse_corr_alpha = 1122220, .s_fuse_corr_beta = -5700700 },
 	{ .s_data = { .desc = "CPU2" }, .s_base = 0x100, .s_fuse = 0x088,
 	  .s_fuse_corr_alpha = 1127000, .s_fuse_corr_beta = -6768200 },
 	{ .s_data = { .desc = "CPU3" }, .s_base = 0x120, .s_fuse = 0x12c,
 	  .s_fuse_corr_alpha = 1110900, .s_fuse_corr_beta = -6232000 },
 	{ .s_data = { .desc = "MEM0" }, .s_base = 0x140, .s_fuse = 0x158,
 	  .s_fuse_corr_alpha = 1122300, .s_fuse_corr_beta = -5936400 },
 	{ .s_data = { .desc = "MEM1" }, .s_base = 0x160, .s_fuse = 0x15c,
 	  .s_fuse_corr_alpha = 1145700, .s_fuse_corr_beta = -7124600 },
 	{ .s_data = { .desc = "GPU" },  .s_base = 0x180, .s_fuse = 0x154,
 	  .s_fuse_corr_alpha = 1120100, .s_fuse_corr_beta = -6000500 },
 	{ .s_data = { .desc = "PLLX" }, .s_base = 0x1a0, .s_fuse = 0x160,
 	  .s_fuse_corr_alpha = 1106500, .s_fuse_corr_beta = -6729300 },
 };
 struct tegra_soctherm_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	struct clk		*sc_clk_tsensor;
 	struct clk		*sc_clk_soctherm;
 	struct fdtbus_reset	*sc_rst_soctherm;
 	struct sysmon_envsys	*sc_sme;
 	struct tegra_soctherm_sensor *sc_sensors;
 	const struct tegra_soctherm_config *sc_config;
 	uint32_t		sc_base_cp;
 	uint32_t		sc_base_ft;
 	int32_t			sc_actual_temp_cp;
 	int32_t			sc_actual_temp_ft;
 };
 static int	tegra_soctherm_init_clocks(struct tegra_soctherm_softc *);
 static void	tegra_soctherm_init_sensors(device_t);
 static void	tegra_soctherm_init_sensor(struct tegra_soctherm_softc *,
 		    struct tegra_soctherm_sensor *);
 static void	tegra_soctherm_refresh(struct sysmon_envsys *, envsys_data_t *);
 static int	tegra_soctherm_decodeint(uint32_t, uint32_t);
 static int64_t	tegra_soctherm_divide(int64_t, int64_t);
 CFATTACH_DECL_NEW(tegra_soctherm, sizeof(struct tegra_soctherm_softc),
 	tegra_soctherm_match, tegra_soctherm_attach, NULL, NULL);
 #define SOCTHERM_READ(sc, reg)			\
     bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
 #define SOCTHERM_WRITE(sc, reg, val)		\
     bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
 #define SOCTHERM_SET_CLEAR(sc, reg, set, clr)	\
     tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))
 #define SENSOR_READ(sc, s, reg)			\
     bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg))
 #define SENSOR_WRITE(sc, s, reg, val)		\
     bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg), (val))
 #define SENSOR_SET_CLEAR(sc, s, reg, set, clr)	\
     tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg), (set), (clr))
 static const struct device_compatible_entry compat_data[] = {
 	{ .compat = "nvidia,tegra124-soctherm",
 	  .data = &tegra124_soctherm_config },
-	{ }
+	DEVICE_COMPAT_EOL
 };
 static int
 tegra_soctherm_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 static void
 tegra_soctherm_attach(device_t parent, device_t self, void *aux)
+{
 	struct tegra_soctherm_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	bus_addr_t addr;
 	bus_size_t size;
 	int error;
 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	sc->sc_clk_tsensor = fdtbus_clock_get(phandle, "tsensor");
 	if (sc->sc_clk_tsensor == NULL) {
 		aprint_error(": couldn't get clock tsensor\n");
 		return;
+	}
 	sc->sc_clk_soctherm = fdtbus_clock_get(phandle, "soctherm");
 	if (sc->sc_clk_soctherm == NULL) {
 		aprint_error(": couldn't get clock soctherm\n");
 		return;
+	}
 	sc->sc_rst_soctherm = fdtbus_reset_get(phandle, "soctherm");
 	if (sc->sc_rst_soctherm == NULL) {
 		aprint_error(": couldn't get reset soctherm\n");
 		return;
+	}
 	sc->sc_dev = self;
 	sc->sc_bst = faa->faa_bst;
 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
 	if (error) {
 		aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
 		return;
+	}
 	aprint_naive("\n");
 	aprint_normal(": SOC_THERM\n");
 	sc->sc_config = of_search_compatible(phandle, compat_data)->data;
 	if (sc->sc_config == NULL) {
 		aprint_error_dev(self, "unsupported SoC\n");
 		return;
+	}
 	if (tegra_soctherm_init_clocks(sc) != 0)
 		return;
 	config_defer(self, tegra_soctherm_init_sensors);
+}
 static int
 tegra_soctherm_init_clocks(struct tegra_soctherm_softc *sc)
+{
 	int error;
 	fdtbus_reset_assert(sc->sc_rst_soctherm);
 	error = clk_set_rate(sc->sc_clk_soctherm, 51000000);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't set soctherm rate: %d\n", error);
 		return error;
+	}
 	error = clk_set_rate(sc->sc_clk_tsensor, 400000);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't set tsensor rate: %d\n", error);
 		return error;
+	}
 	error = clk_enable(sc->sc_clk_tsensor);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "couldn't enable tsensor: %d\n",
 		    error);
 		return error;
+	}
 	error = clk_enable(sc->sc_clk_soctherm);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "couldn't enable soctherm: %d\n",
 		    error);
 		return error;
+	}
 	fdtbus_reset_deassert(sc->sc_rst_soctherm);
 	return 0;
+}
 static void
 tegra_soctherm_init_sensors(device_t dev)
+{
 	struct tegra_soctherm_softc * const sc = device_private(dev);
 	const struct tegra_soctherm_config *config = sc->sc_config;
 	const u_int nsensors = __arraycount(tegra_soctherm_sensors);
 	const size_t len = sizeof(*sc->sc_sensors) * nsensors;
 	uint32_t val;
 	u_int n;
 	val = tegra_fuse_read(FUSE_TSENSOR8_CALIB_REG);
 	sc->sc_base_cp = __SHIFTOUT(val, FUSE_TSENSOR8_CALIB_CP_TS_BASE);
 	sc->sc_base_ft = __SHIFTOUT(val, FUSE_TSENSOR8_CALIB_FT_TS_BASE);
 	val = tegra_fuse_read(FUSE_SPARE_REALIGNMENT_REG);
 	const int calib_cp = tegra_soctherm_decodeint(val,
 	    FUSE_SPARE_REALIGNMENT_CP);
 	const int calib_ft = tegra_soctherm_decodeint(val,
 	    FUSE_SPARE_REALIGNMENT_FT);
 	sc->sc_actual_temp_cp = 2 * config->nominal_calib_cp + calib_cp;
 	sc->sc_actual_temp_ft = 2 * config->nominal_calib_ft + calib_ft;
 	sc->sc_sme = sysmon_envsys_create();
 	sc->sc_sme->sme_name = device_xname(sc->sc_dev);
 	sc->sc_sme->sme_cookie = sc;
 	sc->sc_sme->sme_refresh = tegra_soctherm_refresh;
 	sc->sc_sensors = kmem_zalloc(len, KM_SLEEP);
 	for (n = 0; n < nsensors; n++) {
 		sc->sc_sensors[n] = tegra_soctherm_sensors[n];
 		tegra_soctherm_init_sensor(sc, &sc->sc_sensors[n]);
+	}
 	SOCTHERM_WRITE(sc, SOC_THERM_TSENSOR_PDIV_REG, config->init_pdiv);
 	SOCTHERM_WRITE(sc, SOC_THERM_TSENSOR_HOTSPOT_OFF_REG,
 	    config->init_hotspot_off);
 	sysmon_envsys_register(sc->sc_sme);
+}
 static void
 tegra_soctherm_init_sensor(struct tegra_soctherm_softc *sc,
     struct tegra_soctherm_sensor *s)
+{
 	const struct tegra_soctherm_config *config = sc->sc_config;
 	int64_t temp_a, temp_b, tmp;
 	uint32_t val;
 	val = tegra_fuse_read(s->s_fuse);
 	const int calib_cp = tegra_soctherm_decodeint(val,
 	    FUSE_TSENSOR_CALIB_CP_TS_BASE);
 	const int calib_ft = tegra_soctherm_decodeint(val,
 	    FUSE_TSENSOR_CALIB_FT_TS_BASE);
 	const int actual_cp = sc->sc_base_cp * 64 + calib_cp;
 	const int actual_ft = sc->sc_base_ft * 32 + calib_ft;
 	const int64_t d_sensor = actual_ft - actual_cp;
 	const int64_t d_temp = sc->sc_actual_temp_ft - sc->sc_actual_temp_cp;
 	const int mult = config->pdiv * config->tsample_ate;
 	const int div = config->tsample * config->pdiv_ate;
 	temp_a = tegra_soctherm_divide(d_temp * 0x2000 * mult,
 	    d_sensor * div);
 	tmp = (int64_t)actual_ft * sc->sc_actual_temp_cp -
 	      (int64_t)actual_cp * sc->sc_actual_temp_ft;
 	temp_b = tegra_soctherm_divide(tmp, d_sensor);
 	temp_a = tegra_soctherm_divide(
 	    temp_a * s->s_fuse_corr_alpha, 1000000);
 	temp_b = (uint16_t)tegra_soctherm_divide(
 	    temp_b * s->s_fuse_corr_alpha + s->s_fuse_corr_beta, 1000000);
 	s->s_therm_a = (int16_t)temp_a;
 	s->s_therm_b = (int16_t)temp_b;
 	SENSOR_SET_CLEAR(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET,
 	    SOC_THERM_TSENSOR_CONFIG0_STATUS_CLR |
 	    SOC_THERM_TSENSOR_CONFIG0_STOP, 0);
 	SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET,
 	    __SHIFTIN(config->tall, SOC_THERM_TSENSOR_CONFIG0_TALL) |
 	    SOC_THERM_TSENSOR_CONFIG0_STOP);
 	SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG1_OFFSET,
 	    __SHIFTIN(config->tsample - 1, SOC_THERM_TSENSOR_CONFIG1_TSAMPLE) |
 	    __SHIFTIN(config->tiddq_en, SOC_THERM_TSENSOR_CONFIG1_TIDDQ_EN) |
 	    __SHIFTIN(config->ten_count, SOC_THERM_TSENSOR_CONFIG1_TEN_COUNT) |
 	    SOC_THERM_TSENSOR_CONFIG1_TEMP_ENABLE);
 	SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG2_OFFSET,
 	    __SHIFTIN((uint16_t)s->s_therm_a,
 		      SOC_THERM_TSENSOR_CONFIG2_THERM_A) |
 	    __SHIFTIN((uint16_t)s->s_therm_b,
 		      SOC_THERM_TSENSOR_CONFIG2_THERM_B));
 	SENSOR_SET_CLEAR(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET,
 , SOC_THERM_TSENSOR_CONFIG0_STOP);
 	s->s_data.units = ENVSYS_STEMP;
 	s->s_data.state = ENVSYS_SINVALID;
 	sysmon_envsys_sensor_attach(sc->sc_sme, &s->s_data);
+}
 static void
 tegra_soctherm_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
+{
 	struct tegra_soctherm_softc * const sc = sme->sme_cookie;
 	struct tegra_soctherm_sensor *s = (struct tegra_soctherm_sensor *)edata;
 	uint32_t status;
 	status = SENSOR_READ(sc, s, SOC_THERM_TSENSOR_STATUS1_OFFSET);
 	if (status & SOC_THERM_TSENSOR_STATUS1_TEMP_VALID) {
 		const u_int temp = __SHIFTOUT(status,
 		    SOC_THERM_TSENSOR_STATUS1_TEMP);
 		int64_t val = ((temp >> 8) & 0xff) * 1000000;
 		if (temp & 0x80)
 			val += 500000;
 		if (temp & 0x02)
 			val = -val;
 		edata->value_cur = val + 273150000;
 		edata->state = ENVSYS_SVALID;
 	} else {
 		edata->state = ENVSYS_SINVALID;
+	}
+}
 static int
 tegra_soctherm_decodeint(uint32_t val, uint32_t bitmask)
+{
 	const uint32_t v = __SHIFTOUT(val, bitmask);
 	const int bits = popcount32(bitmask);
 	int ret = v << (32 - bits);
 	return ret >> (32 - bits);
+}
 static int64_t
 tegra_soctherm_divide(int64_t num, int64_t denom)
+{
 	int64_t ret = ((num << 16) * 2 + 1) / (2 * denom);
 	return ret >> 16;
+}

 @@ -1,1008 +1,1008 @@
-/* $NetBSD: tegra_xusb.c,v 1.24 2021/01/25 14:20:38 thorpej Exp $ */
+/* $NetBSD: tegra_xusb.c,v 1.25 2021/01/27 01:58:15 thorpej Exp $ */
 /*
  * Copyright (c) 2016 Jonathan A. Kollasch
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include "locators.h"
 #include "opt_tegra.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.24 2021/01/25 14:20:38 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.25 2021/01/27 01:58:15 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_var.h>
 #include <arm/nvidia/tegra_xusbpad.h>
 #include <arm/nvidia/tegra_xusbreg.h>
 #include <arm/nvidia/tegra_pmcreg.h>
 #include <dev/pci/pcireg.h>
 #include <dev/fdt/fdtvar.h>
 #include <dev/firmload.h>
 #include <dev/usb/usb.h>
 #include <dev/usb/usbdi.h>
 #include <dev/usb/usbdivar.h>
 #include <dev/usb/usb_mem.h>
 #include <dev/usb/xhcireg.h>
 #include <dev/usb/xhcivar.h>
 #ifdef TEGRA_XUSB_DEBUG
 int tegra_xusb_debug = 1;
 #else
 int tegra_xusb_debug = 0;
 #endif
 #define DPRINTF(...)	if (tegra_xusb_debug) device_printf(__VA_ARGS__)
 static int	tegra_xusb_match(device_t, cfdata_t, void *);
 static void	tegra_xusb_attach(device_t, device_t, void *);
 static void	tegra_xusb_mountroot(device_t);
 static int	tegra_xusb_intr_mbox(void *);
 #ifdef TEGRA124_XUSB_BIN_STATIC
 extern const char _binary_tegra124_xusb_bin_start[];
 extern const char _binary_tegra124_xusb_bin_end[];
 __asm__(
 ".section \".rodata\"\n"
 "_binary_tegra124_xusb_bin_start:\n"
 ".incbin \"../external/nvidia-firmware/tegra/dist/tegra124/xusb.bin\"\n"
 ".size _binary_tegra124_xusb_bin_start, . - _binary_tegra124_xusb_bin_start\n"
 "_binary_tegra124_xusb_bin_end:\n"
 ".previous\n"
 );
 #endif
 #ifdef TEGRA210_XUSB_BIN_STATIC
 extern const char _binary_tegra210_xusb_bin_start[];
 extern const char _binary_tegra210_xusb_bin_end[];
 __asm__(
 ".section \".rodata\"\n"
 "_binary_tegra210_xusb_bin_start:\n"
 ".incbin \"../external/nvidia-firmware/tegra/dist/tegra210/xusb.bin\"\n"
 ".size _binary_tegra210_xusb_bin_start, . - _binary_tegra210_xusb_bin_start\n"
 "_binary_tegra210_xusb_bin_end:\n"
 ".previous\n"
 );
 #endif
 enum xusb_type {
 	XUSB_T124 = 1,
 	XUSB_T210
 };
 struct tegra_xhci_data {
 	enum xusb_type		txd_type;
 	const char * const *	txd_supplies;
 	size_t			txd_nsupplies;
 	bool			txd_scale_ss_clock;
 };
 const char *tegra124_xhci_supplies[] = {
 	"dvddio-pex-supply",
 	"hvddio-pex-supply",
 	"avdd-usb-supply",
 	"avdd-pll-utmip-supply",
 	"avdd-pll-uerefe-supply",
 	"dvdd-usb-ss-pll-supply",
 	"hvdd-usb-ss-pll-e-supply"
 };
 struct tegra_xhci_data tegra124_xhci_data = {
 	.txd_type = XUSB_T124,
 	.txd_supplies = tegra124_xhci_supplies,
 	.txd_nsupplies = __arraycount(tegra124_xhci_supplies),
 	.txd_scale_ss_clock = true,
 };
 const char *tegra210_xhci_supplies[] = {
 	"dvddio-pex",
 	"hvddio-pex",
 	"avdd-usb",
 	"avdd-pll-utmip",
 	"avdd-pll-uerefe",
 	"dvdd-pex-pll",
 	"hvdd-pex-pll-e",
 };
 struct tegra_xhci_data tegra210_xhci_data = {
 	.txd_type = XUSB_T210,
 	.txd_supplies = tegra210_xhci_supplies,
 	.txd_nsupplies = __arraycount(tegra210_xhci_supplies),
 	.txd_scale_ss_clock = false,
 };
 static const struct device_compatible_entry compat_data[] = {
 	{ .compat = "nvidia,tegra124-xusb", .data = &tegra124_xhci_data },
 	{ .compat = "nvidia,tegra210-xusb", .data = &tegra210_xhci_data },
-	{ }
+	DEVICE_COMPAT_EOL
 };
 struct fw_dma {
 	bus_dmamap_t            map;
 	void *                  addr;
 	bus_dma_segment_t       segs[1];
 	int                     nsegs;
 	size_t                  size;
 };
 struct tegra_xusb_softc {
 	struct xhci_softc	sc_xhci;
 	int			sc_phandle;
 	bus_space_handle_t	sc_bsh_xhci;
 	bus_space_handle_t	sc_bsh_fpci;
 	bus_space_handle_t	sc_bsh_ipfs;
 	void			*sc_ih;
 	void			*sc_ih_mbox;
 	struct fw_dma		sc_fw_dma;
 	struct clk		*sc_clk_ss_src;
 	const struct tegra_xhci_data *sc_txd;
 };
 static uint32_t	csb_read_4(struct tegra_xusb_softc * const, bus_size_t);
 static void	csb_write_4(struct tegra_xusb_softc * const, bus_size_t,
     uint32_t);
 static void	tegra_xusb_init(struct tegra_xusb_softc * const);
 static int	tegra_xusb_open_fw(struct tegra_xusb_softc * const);
 static int	tegra_xusb_load_fw(struct tegra_xusb_softc * const, void *,
     size_t);
 static void	tegra_xusb_init_regulators(struct tegra_xusb_softc * const);
 static int	xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t);
 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc),
 	tegra_xusb_match, tegra_xusb_attach, NULL, NULL);
 static int
 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 #define tegra_xusb_attach_check(sc, cond, fmt, ...)			\
     do {								\
 	if (cond) {							\
 		aprint_error_dev(sc->sc_dev, fmt, ## __VA_ARGS__);	\
 		return;							\
 	}								\
     } while (0)
 static void
 tegra_xusb_attach(device_t parent, device_t self, void *aux)
+{
 	struct tegra_xusb_softc * const psc = device_private(self);
 	struct xhci_softc * const sc = &psc->sc_xhci;
 	struct fdt_attach_args * const faa = aux;
 	bool wait_for_root = true;
 	char intrstr[128];
 	bus_addr_t addr;
 	bus_size_t size;
 	struct fdtbus_reset *rst;
 	struct fdtbus_phy *phy;
 	struct clk *clk;
 	uint32_t rate;
 	int error, n;
 	aprint_naive("\n");
 	aprint_normal(": XUSB\n");
 	sc->sc_dev = self;
 	sc->sc_iot = faa->faa_bst;
 	sc->sc_bus.ub_hcpriv = sc;
 	sc->sc_bus.ub_dmatag = faa->faa_dmat;
 	sc->sc_quirks = XHCI_DEFERRED_START;
 	psc->sc_phandle = faa->faa_phandle;
 	psc->sc_txd = of_search_compatible(faa->faa_phandle, compat_data)->data;
 	if (fdtbus_get_reg_byname(faa->faa_phandle, "hcd", &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh);
 	if (error) {
 		aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
 		return;
+	}
 	DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr);
 	sc->sc_ios = size;
 	if (fdtbus_get_reg_byname(faa->faa_phandle, "fpci", &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci);
 	if (error) {
 		aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
 		return;
+	}
 	DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr);
 	if (fdtbus_get_reg_byname(faa->faa_phandle, "ipfs", &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs);
 	if (error) {
 		aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
 		return;
+	}
 	DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr);
 	if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error_dev(self, "failed to decode interrupt\n");
 		return;
+	}
 	psc->sc_ih = fdtbus_intr_establish_xname(faa->faa_phandle, 0, IPL_USB,
 	    FDT_INTR_MPSAFE, xhci_intr, sc, device_xname(self));
 	if (psc->sc_ih == NULL) {
 		aprint_error_dev(self, "failed to establish interrupt on %s\n",
 		    intrstr);
 		return;
+	}
 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
 	if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) {
 		aprint_error_dev(self, "failed to decode interrupt\n");
 		return;
+	}
 	psc->sc_ih_mbox = fdtbus_intr_establish_xname(faa->faa_phandle, 1,
 	    IPL_VM, FDT_INTR_MPSAFE, tegra_xusb_intr_mbox, psc,
 	    device_xname(self));
 	if (psc->sc_ih_mbox == NULL) {
 		aprint_error_dev(self, "failed to establish interrupt on %s\n",
 		    intrstr);
 		return;
+	}
 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
 	/* Enable PHYs */
 	for (n = 0; (phy = fdtbus_phy_get_index(faa->faa_phandle, n)) != NULL; n++)
 		if (fdtbus_phy_enable(phy, true) != 0)
 			aprint_error_dev(self, "failed to enable PHY #%d\n", n);
 	/* Enable XUSB power rails */
 	tegra_pmc_power(PMC_PARTID_XUSBC, true);	/* Host/USB2.0 */
 	tegra_pmc_remove_clamping(PMC_PARTID_XUSBC);
 	tegra_pmc_power(PMC_PARTID_XUSBA, true);	/* SuperSpeed */
 	tegra_pmc_remove_clamping(PMC_PARTID_XUSBA);
 	/* Enable XUSB clocks */
 	clk = fdtbus_clock_get(faa->faa_phandle, "pll_e");
 	rate = clk_get_rate(clk);
 	error = clk_enable(clk); /* XXX set frequency */
 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
 	tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock");
 	clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src");
 	rate = clk_get_rate(clk);
 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
 	error = clk_set_rate(clk, 102000000);
 	tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate");
 	rate = clk_get_rate(clk);
 	error = clk_enable(clk); /* XXX set frequency */
 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
 	tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock");
 	clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src");
 	rate = clk_get_rate(clk);
 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
 	error = clk_set_rate(clk, 204000000);
 	tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate");
 	rate = clk_get_rate(clk);
 	error = clk_enable(clk);
 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
 	tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock");
 	clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host");
 	rate = clk_get_rate(clk);
 	error = clk_enable(clk); /* XXX set frequency */
 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
 	clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss");
 	rate = clk_get_rate(clk);
 	error = clk_enable(clk); /* XXX set frequency */
 	DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error);
 	tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock");
 	psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src");
 	tegra_xusb_attach_check(sc, psc->sc_clk_ss_src == NULL,
 		"failed to get xusb_ss_src clock");
 	if (psc->sc_txd->txd_scale_ss_clock) {
 		rate = clk_get_rate(psc->sc_clk_ss_src);
 		DPRINTF(sc->sc_dev, "xusb_ss_src rate %u\n", rate);
 		error = clk_set_rate(psc->sc_clk_ss_src, 2000000);
 		rate = clk_get_rate(psc->sc_clk_ss_src);
 		DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error);
 		tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate");
 		rate = clk_get_rate(psc->sc_clk_ss_src);
 		DPRINTF(sc->sc_dev, "ss_src rate %u\n", rate);
 		tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate");
 		error = clk_set_rate(psc->sc_clk_ss_src, 120000000);
 		rate = clk_get_rate(psc->sc_clk_ss_src);
 		DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error);
 		tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate");
+	}
 	rate = clk_get_rate(psc->sc_clk_ss_src);
 	error = clk_enable(psc->sc_clk_ss_src);
 	DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error);
 	tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock");
 #if 0
 	clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src");
 	error = 0;
 	rate = clk_get_rate(clk);
 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
 #endif
 	clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src");
 	rate = clk_get_rate(clk);
 	error = clk_enable(clk); /* XXX set frequency */
 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
 	tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock");
 	rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host");
 	fdtbus_reset_deassert(rst);
 	rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src");
 	fdtbus_reset_deassert(rst);
 	rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss");
 	fdtbus_reset_deassert(rst);
 	DELAY(1);
 	tegra_xusb_init_regulators(psc);
 	tegra_xusb_init(psc);
 #if defined(TEGRA124_XUSB_BIN_STATIC)
 	if (psc->sc_txd->txd_type == XUSB_T124)
 		wait_for_root = false;
 #endif
 #if defined(TEGRA210_XUSB_BIN_STATIC)
 	if (psc->sc_txd->txd_type == XUSB_T210)
 		wait_for_root = false;
 #endif
 	if (wait_for_root)
 		config_mountroot(sc->sc_dev, tegra_xusb_mountroot);
 	else
 		tegra_xusb_mountroot(sc->sc_dev);
+}
 static void
 tegra_xusb_mountroot(device_t self)
+{
 	struct tegra_xusb_softc * const psc = device_private(self);
 	struct xhci_softc * const sc = &psc->sc_xhci;
 	const bus_space_tag_t bst = sc->sc_iot;
 	const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs;
 	struct clk *clk;
 	struct fdtbus_reset *rst;
 	uint32_t rate;
 	uint32_t val;
 	int error;
 	DPRINTF(sc->sc_dev, "%s()\n", __func__);
 	val = bus_space_read_4(bst, ipfsh, 0x0);
 	DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val);
 	if (tegra_xusb_open_fw(psc) != 0)
 		return;
 	DPRINTF(sc->sc_dev, "post fw\n");
 	tegra_xusbpad_xhci_enable();
 	clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src");
 	rate = clk_get_rate(clk);
 	error = clk_enable(clk);
 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
 	clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src");
 	rate = clk_get_rate(clk);
 	error = clk_enable(clk);
 	DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error);
 	val = bus_space_read_4(bst, ipfsh, 0x0);
 	DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val);
 	rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host");
 	fdtbus_reset_deassert(rst);
 	rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src");
 	fdtbus_reset_deassert(rst);
 	rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss");
 	fdtbus_reset_deassert(rst);
 	val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG);
 	DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val);
 	val = bus_space_read_4(bst, psc->sc_bsh_fpci, PCI_USBREV)
 	    & PCI_USBREV_MASK;
 	switch (val) {
 	case PCI_USBREV_3_0:
 		sc->sc_bus.ub_revision = USBREV_3_0;
 		break;
 	case PCI_USBREV_3_1:
 		sc->sc_bus.ub_revision = USBREV_3_1;
 		break;
 	default:
 		if (val < PCI_USBREV_3_0) {
 			aprint_error_dev(self, "Unknown revision (%02x)\n", val);
 			sc->sc_bus.ub_revision = USBREV_UNKNOWN;
 		} else {
 			/* Default to the latest revision */
 			aprint_normal_dev(self,
 			    "Unknown revision (%02x). Set to 3.1.\n", val);
 			sc->sc_bus.ub_revision = USBREV_3_1;
+		}
 		break;
+	}
 	error = xhci_init(sc);
 	if (error) {
 		aprint_error_dev(self, "init failed, error=%d\n", error);
 		return;
+	}
 	sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint);
 	sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint);
 	xhci_start(sc);
 	error = xusb_mailbox_send(psc, 0x01000000);
 	if (error) {
 		aprint_error_dev(self, "send failed, error=%d\n", error);
+	}
+}
 static int
 tegra_xusb_intr_mbox(void *v)
+{
 	struct tegra_xusb_softc * const psc = v;
 	struct xhci_softc * const sc = &psc->sc_xhci;
 	const bus_space_tag_t bst = sc->sc_iot;
 	const bus_space_handle_t fpcih = psc->sc_bsh_fpci;
 	uint32_t val;
 	uint32_t irv;
 	uint32_t msg;
 	int error;
 	DPRINTF(sc->sc_dev, "%s()\n", __func__);
 	irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG);
 	DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv);
 	bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv);
 	if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG)
 		aprint_error_dev(sc->sc_dev, "firmware hang\n");
 	msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG);
 	DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg);
 	val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG);
 	DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val);
 	val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI;
 	bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val);
 	bool sendresp = true;
 	u_int rate;
 	const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA);
 	const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE);
 	switch (type) {
 	case 2:
 	case 3:
 		DPRINTF(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000);
 		break;
 	case 4:
 	case 5:
 		if (psc->sc_txd->txd_scale_ss_clock) {
 			DPRINTF(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000);
 			rate = clk_get_rate(psc->sc_clk_ss_src);
 			DPRINTF(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n",
 			    rate);
 			error = clk_set_rate(psc->sc_clk_ss_src, data * 1000);
 			if (error != 0)
 				goto clk_fail;
 			rate = clk_get_rate(psc->sc_clk_ss_src);
 			DPRINTF(sc->sc_dev,
 			    "rate of psc->sc_clk_ss_src %u after\n", rate);
 			if (data == (rate / 1000)) {
 				msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) |
 				      __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA);
 			} else
 clk_fail:
 				msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) |
 				      __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA);
 		} else {
 			msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) |
 			      __SHIFTIN(data, MAILBOX_DATA_DATA);
+		}
 		xusb_mailbox_send(psc, msg);
 		break;
 	case 9:
 		msg = __SHIFTIN(data, MAILBOX_DATA_DATA) |
 		      __SHIFTIN(128, MAILBOX_DATA_TYPE);
 		xusb_mailbox_send(psc, msg);
 		break;
 	case 6:
 	case 128:
 	case 129:
 		sendresp = false;
 		break;
 	default:
 		sendresp = false;
 		break;
+	}
 	if (sendresp == false)
 		bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG,
 		    MAILBOX_OWNER_NONE);
 	return irv;
+}
 static void
 tegra_xusb_init_regulators(struct tegra_xusb_softc * const psc)
+{
 	device_t dev = psc->sc_xhci.sc_dev;
 	const int phandle = psc->sc_phandle;
 	struct fdtbus_regulator *reg;
 	int n, error;
 	for (n = 0; n < psc->sc_txd->txd_nsupplies; n++) {
 		if (!of_hasprop(phandle, psc->sc_txd->txd_supplies[n]))
 			continue;
 		reg = fdtbus_regulator_acquire(phandle, psc->sc_txd->txd_supplies[n]);
 		if (reg == NULL) {
 			aprint_error_dev(dev, "couldn't acquire supply '%s'\n",
 			    psc->sc_txd->txd_supplies[n]);
 			continue;
+		}
 		error = fdtbus_regulator_enable(reg);
 		if (error != 0)
 			aprint_error_dev(dev, "couldn't enable supply '%s': %d\n",
 			    psc->sc_txd->txd_supplies[n], error);
+	}
+}
 static void
 tegra_xusb_init(struct tegra_xusb_softc * const psc)
+{
 	struct xhci_softc * const sc = &psc->sc_xhci;
 	const bus_space_tag_t bst = sc->sc_iot;
 	const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs;
 	const bus_space_handle_t fpcih = psc->sc_bsh_fpci;
 	DPRINTF(sc->sc_dev, "%s()\n", __func__);
 	DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__,
 	    bus_space_read_4(bst, ipfsh, 0x0));
 	DPRINTF(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__,
 	    bus_space_read_4(bst, ipfsh, 0x40));
 	DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__,
 	    bus_space_read_4(bst, ipfsh, 0x80));
 	/* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */
 	bus_space_write_4(bst, ipfsh, 0x80, 0x00100000);
 	DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__,
 	    bus_space_read_4(bst, ipfsh, 0x80));
 	DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__,
 	    bus_space_read_4(bst, ipfsh, 0x180));
 	/* EN_FPCI */
 	tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0);
 	DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__,
 	    bus_space_read_4(bst, ipfsh, 0x180));
 	DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n",
 	    __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG));
 	tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG,
 	    PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0);
 	DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n",
 	    __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG));
 	DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__,
 	    bus_space_read_4(bst, fpcih, PCI_BAR0));
 	/* match FPCI BAR0 to above */
 	bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000);
 	DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__,
 	    bus_space_read_4(bst, fpcih, PCI_BAR0));
 	DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__,
 	    bus_space_read_4(bst, ipfsh, 0x188));
 	tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0);
 	DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__,
 	    bus_space_read_4(bst, ipfsh, 0x188));
 	DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__,
 	    bus_space_read_4(bst, fpcih, 0x1bc));
 	bus_space_write_4(bst, fpcih, 0x1bc, 0x80);
 	DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__,
 	    bus_space_read_4(bst, fpcih, 0x1bc));
+}
 static int
 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align,
     struct fw_dma * const p)
+{
 	struct xhci_softc * const sc = &psc->sc_xhci;
 	const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag;
 	int err;
 	p->size = size;
 	err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs,
 	    sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT);
 	if (err)
 		return err;
 	err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr,
 	    BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
 	if (err)
 		goto free;
 	err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT,
 	    &p->map);
 	if (err)
 		goto unmap;
 	err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL,
 	    BUS_DMA_NOWAIT);
 	if (err)
 		goto destroy;
 	return 0;
 destroy:
 	bus_dmamap_destroy(dmat, p->map);
 unmap:
 	bus_dmamem_unmap(dmat, p->addr, p->size);
 free:
 	bus_dmamem_free(dmat, p->segs, p->nsegs);
 	return err;
+}
 static void
 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p)
+{
 	const struct xhci_softc * const sc = &psc->sc_xhci;
 	const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag;
 	bus_dmamap_unload(dmat, p->map);
 	bus_dmamap_destroy(dmat, p->map);
 	bus_dmamem_unmap(dmat, p->addr, p->size);
 	bus_dmamem_free(dmat, p->segs, p->nsegs);
+}
 #define FWHEADER_BOOT_CODETAG 8
 #define FWHEADER_BOOT_CODESIZE 12
 #define FWHEADER_FWIMG_LEN 100
 #define FWHEADER__LEN 256
 static int
 tegra_xusb_open_fw(struct tegra_xusb_softc * const psc)
+{
 	struct xhci_softc * const sc = &psc->sc_xhci;
 	firmware_handle_t fw;
 	size_t firmware_size = 0;
 	void *firmware_image;
 	const char *fw_path = NULL;
 	void *fw_static = NULL;
 	int error;
 	switch (psc->sc_txd->txd_type) {
 	case XUSB_T124:
 #if defined(TEGRA124_XUSB_BIN_STATIC)
 		firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_end
 		    - (uintptr_t)&_binary_tegra124_xusb_bin_start;
 		fw_static = __UNCONST(_binary_tegra124_xusb_bin_start);
 #else
 		fw_path = "nvidia/tegra124";
 #endif
 		break;
 	case XUSB_T210:
 #if defined(TEGRA210_XUSB_BIN_STATIC)
 		firmware_size = (uintptr_t)&_binary_tegra210_xusb_bin_end
 		    - (uintptr_t)&_binary_tegra210_xusb_bin_start;
 		fw_static = __UNCONST(_binary_tegra210_xusb_bin_start);
 #else
 		fw_path = "nvidia/tegra210";
 #endif
 		break;
 	default:
 		return EINVAL;
+	}
 	if (fw_path != NULL) {
 		error = firmware_open(fw_path, "xusb.bin", &fw);
 		if (error != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "couldn't load firmware from %s/xusb.bin: %d\n",
 			    fw_path, error);
 			return error;
+		}
 		firmware_size = firmware_get_size(fw);
+	}
 	error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE,
 	    &psc->sc_fw_dma);
 	if (error != 0)
 		return error;
 	firmware_image = psc->sc_fw_dma.addr;
 	if (fw_path != NULL) {
 		error = firmware_read(fw, 0, firmware_image, firmware_size);
 		if (error != 0) {
 			fw_dma_free(psc, &psc->sc_fw_dma);
 			firmware_close(fw);
 			return error;
+		}
 		firmware_close(fw);
 	} else {
 		memcpy(firmware_image, fw_static, firmware_size);
+	}
 	return tegra_xusb_load_fw(psc, firmware_image, firmware_size);
+}
 static int
 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc, void *firmware_image,
     size_t firmware_size)
+{
 	struct xhci_softc * const sc = &psc->sc_xhci;
 	const uint8_t *header;
 	header = firmware_image;
 	const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]);
 	const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]);
 	const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]);
 	if (fwimg_len != firmware_size)
 		aprint_error_dev(sc->sc_dev, "fwimg_len mismatch %u != %zu\n",
 		    fwimg_len, firmware_size);
 	bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0,
 	    firmware_size, BUS_DMASYNC_PREWRITE);
 	DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG));
 	DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG));
 	DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG));
 	csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG,
 	    fwimg_len);
 	DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG));
 	const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr +
 	    FWHEADER__LEN;
 	csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32);
 	csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase);
 	DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG));
 	DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG));
 	DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG));
 	csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG,
 	    XUSB_CSB_MEMPOOL_APMAP_BOOTPATH);
 	DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG));
 	DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG));
 	csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG,
 	    __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL,
 		XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION));
 	DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG));
 	const u_int code_tag_blocks =
 	    howmany(boot_codetag, IMEM_BLOCK_SIZE);
 	const u_int code_size_blocks =
 	    howmany(boot_codesize, IMEM_BLOCK_SIZE);
 	const u_int code_blocks = code_tag_blocks + code_size_blocks;
 	DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG));
 	csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG,
 	    __SHIFTIN(code_tag_blocks,
 		XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) |
 	    __SHIFTIN(code_size_blocks,
 		XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT));
 	DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG));
 	DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG));
 	csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG,
 	    __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT,
 		XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION));
 	DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG));
 	DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG));
 	csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks);
 	DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG));
 	DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG));
 	csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG,
 	    __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) |
 	    __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI));
 	DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG));
 	DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG));
 	csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0);
 	DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG));
 	DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG));
 	csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG,
 	    boot_codetag);
 	DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG));
 	DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG));
 	csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG,
 	    XUSB_CSB_FALCON_CPUCTL_STARTCPU);
 	DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n",
 	    csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG));
 	return 0;
+}
 static uint32_t
 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset)
+{
 	const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE);
 	const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET);
 	const bus_space_tag_t bst = psc->sc_xhci.sc_iot;
 	const bus_space_handle_t fpcih = psc->sc_bsh_fpci;
 	bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range);
 	return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset);
+}
 static void
 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset,
     uint32_t value)
+{
 	const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE);
 	const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET);
 	const bus_space_tag_t bst = psc->sc_xhci.sc_iot;
 	const bus_space_handle_t fpcih = psc->sc_bsh_fpci;
 	bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range);
 	bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value);
+}
 static int
 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg)
+{
 	struct xhci_softc * const sc = &psc->sc_xhci;
 	const bus_space_tag_t bst = psc->sc_xhci.sc_iot;
 	const bus_space_handle_t fpcih = psc->sc_bsh_fpci;
 	uint32_t val;
 	bool wait = false;
 	const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE);
 	if (!(type == 128 || type == 129)) {
 		val = bus_space_read_4(bst, fpcih,
 		    T_XUSB_CFG_ARU_MAILBOX_OWNER_REG);
 		DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n",
 		    val);
 		if (val != MAILBOX_OWNER_NONE) {
 			return EBUSY;
+		}
 		bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG,
 		    MAILBOX_OWNER_SW);
 		val = bus_space_read_4(bst, fpcih,
 		    T_XUSB_CFG_ARU_MAILBOX_OWNER_REG);
 		DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n",
 		    val);
 		if (val != MAILBOX_OWNER_SW) {
 			return EBUSY;
+		}
 		wait = true;
+	}
 	bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg);
 	tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG,
 	    T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN |
 	    T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0);
 	if (wait) {
 		for (u_int i = 0; i < 2500; i++) {
 			val = bus_space_read_4(bst, fpcih,
 			    T_XUSB_CFG_ARU_MAILBOX_OWNER_REG);
 			DPRINTF(sc->sc_dev,
 			    "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val);
 			if (val == MAILBOX_OWNER_NONE) {
 				break;
+			}
 			DELAY(10);
+		}
 		val = bus_space_read_4(bst, fpcih,
 		    T_XUSB_CFG_ARU_MAILBOX_OWNER_REG);
 		DPRINTF(sc->sc_dev,
 		    "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val);
 		if (val != MAILBOX_OWNER_NONE) {
 			aprint_error_dev(sc->sc_dev,
 			    "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val);
+		}
+	}
 	return 0;
+}