 @@ -1,527 +1,527 @@
-/* $NetBSD: rk3399_iomux.c,v 1.8 2021/01/25 14:20:38 thorpej Exp $ */
+/* $NetBSD: rk3399_iomux.c,v 1.9 2021/01/27 02:00:02 thorpej Exp $ */
 /*-
  * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 //#define RK3399_IOMUX_DEBUG
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rk3399_iomux.c,v 1.8 2021/01/25 14:20:38 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rk3399_iomux.c,v 1.9 2021/01/27 02:00:02 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/mutex.h>
 #include <sys/kmem.h>
 #include <sys/gpio.h>
 #include <sys/lwp.h>
 #include <dev/fdt/fdtvar.h>
 #include <dev/fdt/syscon.h>
 /* PU/PD control */
 #define	 GRF_GPIO_P_CTL(_idx)		(0x3 << (((_idx) & 7) * 2))
 #define	 GRF_GPIO_P_WRITE_EN(_idx)	(0x3 << (((_idx) & 7) * 2 + 16))
 /* Different bias value mapping based on pull type of pin */
 #define	  IO_DEF_GPIO_P_CTL_Z		0
 #define	  IO_DEF_GPIO_P_CTL_PULLUP	1
 #define	  IO_DEF_GPIO_P_CTL_PULLDOWN	2
 #define	  IO_DEF_GPIO_P_CTL_RESERVED	3
 #define	  IO_1V8_GPIO_P_CTL_Z		0
 #define	  IO_1V8_GPIO_P_CTL_PULLDOWN	1
 #define	  IO_1V8_GPIO_P_CTL_Z_ALT	2
 #define	  IO_1V8_GPIO_P_CTL_PULLUP	3
 /* Drive strength control */
 /* Different drive strength value mapping for GRF and PMU registers */
 #define	  GRF_GPIO_E_CTL_2MA		0
 #define	  GRF_GPIO_E_CTL_4MA		1
 #define	  GRF_GPIO_E_CTL_8MA		2
 #define	  GRF_GPIO_E_CTL_12MA		3
 #define	  PMU_GPIO_E_CTL_5MA		0
 #define	  PMU_GPIO_E_CTL_10MA		1
 #define	  PMU_GPIO_E_CTL_15MA		2
 #define	  PMU_GPIO_E_CTL_20MA		3
 enum rk3399_drv_type {
 	RK3399_DRV_TYPE_IO_DEFAULT,
 	RK3399_DRV_TYPE_IO_1V8_3V0,
 	RK3399_DRV_TYPE_IO_1V8,
 	RK3399_DRV_TYPE_IO_1V8_3V0_AUTO,
 	RK3399_DRV_TYPE_IO_3V3,
 };
 static int rk3399_drv_strength[5][9] = {
 	[RK3399_DRV_TYPE_IO_DEFAULT] =		{ 2, 4, 8, 12, -1 },
 	[RK3399_DRV_TYPE_IO_1V8_3V0] =		{ 3, 6, 9, 12, -1 },
 	[RK3399_DRV_TYPE_IO_1V8] =		{ 5, 10, 15, 20, -1 },
 	[RK3399_DRV_TYPE_IO_1V8_3V0_AUTO] =	{ 4, 6, 8, 10, 12, 14, 16, 18, -1 },
 	[RK3399_DRV_TYPE_IO_3V3] =		{ 4, 7, 10, 13, 16, 19, 22, 26, -1 },
 };
 enum rk3399_pull_type {
 	RK3399_PULL_TYPE_IO_DEFAULT,
 	RK3399_PULL_TYPE_IO_1V8_ONLY,
 };
 struct rk3399_iomux {
 	enum rk3399_drv_type	drv_type;
 	enum rk3399_pull_type	pull_type;
 };
 struct rk3399_iomux_bank {
 	struct rk3399_iomux	iomux[5];
 	u_int			regs;
 #define	RK_IOMUX_REGS_GRF	0
 #define	RK_IOMUX_REGS_PMU	1
 };
 static const struct rk3399_iomux_bank rk3399_iomux_banks[] = {
 	[0] = {
 		.regs = RK_IOMUX_REGS_PMU,
 		.iomux = {
 			[0] = { .drv_type = RK3399_DRV_TYPE_IO_1V8,
 				.pull_type = RK3399_PULL_TYPE_IO_1V8_ONLY },
 			[1] = { .drv_type = RK3399_DRV_TYPE_IO_1V8,
 				.pull_type = RK3399_PULL_TYPE_IO_1V8_ONLY },
 			[2] = { .drv_type = RK3399_DRV_TYPE_IO_DEFAULT,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 			[3] = { .drv_type = RK3399_DRV_TYPE_IO_DEFAULT,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 		},
 	},
 	[1] = {
 		.regs = RK_IOMUX_REGS_PMU,
 		.iomux = {
 			[0] = { .drv_type = RK3399_DRV_TYPE_IO_1V8_3V0,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 			[1] = { .drv_type = RK3399_DRV_TYPE_IO_1V8_3V0,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 			[2] = { .drv_type = RK3399_DRV_TYPE_IO_1V8_3V0,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 			[3] = { .drv_type = RK3399_DRV_TYPE_IO_1V8_3V0,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
+		}
 	},
 	[2] = {
 		.regs = RK_IOMUX_REGS_GRF,
 		.iomux = {
 			[0] = { .drv_type = RK3399_DRV_TYPE_IO_1V8_3V0,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 			[1] = { .drv_type = RK3399_DRV_TYPE_IO_1V8_3V0,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 			[2] = { .drv_type = RK3399_DRV_TYPE_IO_1V8,
 				.pull_type = RK3399_PULL_TYPE_IO_1V8_ONLY },
 			[3] = { .drv_type = RK3399_DRV_TYPE_IO_1V8,
 				.pull_type = RK3399_PULL_TYPE_IO_1V8_ONLY },
 		},
 	},
 	[3] = {
 		.regs = RK_IOMUX_REGS_GRF,
 		.iomux = {
 			[0] = { .drv_type = RK3399_DRV_TYPE_IO_3V3,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 			[1] = { .drv_type = RK3399_DRV_TYPE_IO_3V3,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 			[2] = { .drv_type = RK3399_DRV_TYPE_IO_3V3,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 			[3] = { .drv_type = RK3399_DRV_TYPE_IO_1V8_3V0,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 		},
 	},
 	[4] = {
 		.regs = RK_IOMUX_REGS_GRF,
 		.iomux = {
 			[0] = { .drv_type = RK3399_DRV_TYPE_IO_1V8_3V0,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 			[1] = { .drv_type = RK3399_DRV_TYPE_IO_1V8_3V0_AUTO,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 			[2] = { .drv_type = RK3399_DRV_TYPE_IO_1V8_3V0,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 			[3] = { .drv_type = RK3399_DRV_TYPE_IO_1V8_3V0,
 				.pull_type = RK3399_PULL_TYPE_IO_DEFAULT },
 		},
 	},
 };
 #define	RK3399_IOMUX_BANK_IS_PMU(_bank)	(rk3399_iomux_banks[(_bank)].regs == RK_IOMUX_REGS_PMU)
 struct rk3399_iomux_conf {
 	const struct rk3399_iomux_bank *banks;
 	u_int nbanks;
 };
 static const struct rk3399_iomux_conf rk3399_iomux_conf = {
 	.banks = rk3399_iomux_banks,
 	.nbanks = __arraycount(rk3399_iomux_banks),
 };
 static const struct device_compatible_entry compat_data[] = {
 	{ .compat = "rockchip,rk3399-pinctrl",	.data = &rk3399_iomux_conf },
-	{ }
+	DEVICE_COMPAT_EOL
 };
 struct rk3399_iomux_softc {
 	device_t sc_dev;
 	struct syscon *sc_syscon[2];
 	const struct rk3399_iomux_conf *sc_conf;
 };
 #define	LOCK(syscon) 		\
 	syscon_lock(syscon)
 #define	UNLOCK(syscon)		\
 	syscon_unlock(syscon)
 #define	RD4(syscon, reg) 	\
 	syscon_read_4(syscon, (reg))
 #define	WR4(syscon, reg, val) 	\
 	syscon_write_4(syscon, (reg), (val))
 static int	rk3399_iomux_match(device_t, cfdata_t, void *);
 static void	rk3399_iomux_attach(device_t, device_t, void *);
 CFATTACH_DECL_NEW(rk3399_iomux, sizeof(struct rk3399_iomux_softc),
 	rk3399_iomux_match, rk3399_iomux_attach, NULL, NULL);
 static void
 rk3399_iomux_set_bias(struct rk3399_iomux_softc *sc, u_int bank, u_int idx, int flags)
+{
 	const struct rk3399_iomux_bank *banks = sc->sc_conf->banks;
 	bus_size_t reg;
 	u_int bias;
 	KASSERT(bank < sc->sc_conf->nbanks);
 	struct syscon * const syscon = sc->sc_syscon[banks[bank].regs];
 	if (RK3399_IOMUX_BANK_IS_PMU(bank)) {
 		reg = 0x00040 + (0x10 * bank);
 	} else {
 		reg = 0x0e040 + (0x10 * (bank - 2));
+	}
 	reg += 0x4 * (idx / 8);
 	const int pull_type = banks[bank].iomux[idx / 8].pull_type;
 	if (flags == GPIO_PIN_PULLUP) {
 		bias = pull_type == RK3399_PULL_TYPE_IO_DEFAULT ?
 		    IO_DEF_GPIO_P_CTL_PULLUP :
 		    IO_1V8_GPIO_P_CTL_PULLUP;
 	} else if (flags == GPIO_PIN_PULLDOWN) {
 		bias = pull_type == RK3399_PULL_TYPE_IO_DEFAULT ?
 		    IO_DEF_GPIO_P_CTL_PULLDOWN :
 		    IO_1V8_GPIO_P_CTL_PULLDOWN;
 	} else {
 		bias = pull_type == RK3399_PULL_TYPE_IO_DEFAULT ?
 		    IO_DEF_GPIO_P_CTL_Z :
 		    IO_1V8_GPIO_P_CTL_Z;
+	}
 	const uint32_t bias_val = __SHIFTIN(bias, GRF_GPIO_P_CTL(idx));
 	const uint32_t bias_mask = GRF_GPIO_P_WRITE_EN(idx);
 #ifdef RK3399_IOMUX_DEBUG
 	printf("%s: bank %d idx %d flags %#x: %08x -> ", __func__, bank, idx, flags, RD4(syscon, reg));
 #endif
 	WR4(syscon, reg, bias_val | bias_mask);
 #ifdef RK3399_IOMUX_DEBUG
 	printf("%08x (reg %#lx)\n", RD4(syscon, reg), reg);
 #endif
+}
 static int
 rk3399_iomux_map_drive_strength(struct rk3399_iomux_softc *sc, enum rk3399_drv_type drv_type, u_int val)
+{
 	for (int n = 0; rk3399_drv_strength[drv_type][n] != -1; n++)
 		if (rk3399_drv_strength[drv_type][n] == val)
 			return n;
 	return -1;
+}
 static int
 rk3399_iomux_set_drive_strength(struct rk3399_iomux_softc *sc, u_int bank, u_int idx, u_int val)
+{
 	const struct rk3399_iomux_bank *banks = sc->sc_conf->banks;
 	uint32_t drv_mask, drv_val;
 	bus_size_t reg;
 	KASSERT(bank < sc->sc_conf->nbanks);
 	if (idx >= 32)
 		return EINVAL;
 	const int drv = rk3399_iomux_map_drive_strength(sc, banks[bank].iomux[idx / 8].drv_type, val);
 	if (drv == -1)
 		return EINVAL;
 	struct syscon * const syscon = sc->sc_syscon[banks[bank].regs];
 	switch (bank) {
 	case 0:
 	case 1:
 		reg = 0x00040 + (0x10 * bank) + 0x4 * (idx / 4);
 		drv_mask = 0x3 << ((idx & 7) * 2);
 		break;
 	case 2:
 		reg = 0x0e100 + 0x4 * (idx / 4);
 		drv_mask = 0x3 << ((idx & 7) * 2);
 		break;
 	case 3:
 		switch (idx / 8) {
 		case 0:
 		case 1:
 		case 2:
 			reg = 0x0e110 + 0x8 * (idx / 4);
 			drv_mask = 0x7 << ((idx & 7) * 3);
 			break;
 		case 3:
 			reg = 0x0e128;
 			drv_mask = 0x3 << ((idx & 7) * 2);
 			break;
 		default:
 			return EINVAL;
+		}
 		break;
 	case 4:
 		switch (idx / 8) {
 		case 0:
 			reg = 0x0e12c;
 			drv_mask = 0x3 << ((idx & 7) * 2);
 			break;
 		case 1:
 			reg = 0x0e130;
 			drv_mask = 0x7 << ((idx & 7) * 3);
 			break;
 		case 2:
 			reg = 0x0e138;
 			drv_mask = 0x3 << ((idx & 7) * 2);
 			break;
 		case 3:
 			reg = 0x0e13c;
 			drv_mask = 0x3 << ((idx & 7) * 2);
 			break;
 		default:
 			return EINVAL;
+		}
 		break;
 	default:
 		return EINVAL;
+	}
 	drv_val = __SHIFTIN(val, drv_mask);
 	while (drv_mask) {
 		const uint32_t write_val = drv_val & 0xffff;
 		const uint32_t write_mask = (drv_mask & 0xffff) << 16;
 		if (write_mask) {
 #ifdef RK3399_IOMUX_DEBUG
 			printf("%s: bank %d idx %d val %d: %08x -> ", __func__, bank, idx, val, RD4(syscon, reg));
 #endif
 			WR4(syscon, reg, write_val | write_mask);
 #ifdef RK3399_IOMUX_DEBUG
 			printf("%08x (reg %#lx)\n", RD4(syscon, reg), reg);
 #endif
+		}
 		reg += 0x4;
 		drv_val >>= 16;
 		drv_mask >>= 16;
+	}
 	return 0;
+}
 static void
 rk3399_iomux_set_mux(struct rk3399_iomux_softc *sc, u_int bank, u_int idx, u_int mux)
+{
 	const struct rk3399_iomux_bank *banks = sc->sc_conf->banks;
 	bus_size_t reg;
 	uint32_t mask;
 	KASSERT(bank < sc->sc_conf->nbanks);
 	struct syscon * const syscon = sc->sc_syscon[banks[bank].regs];
 	if (RK3399_IOMUX_BANK_IS_PMU(bank)) {
 		reg = 0x00000 + (0x10 * bank);
 	} else {
 		reg = 0x0e000 + (0x10 * (bank - 2));
+	}
 	reg += 0x4 * (idx / 8);
 	mask = 3 << ((idx & 7) * 2);
 #ifdef RK3399_IOMUX_DEBUG
 	printf("%s: bank %d idx %d mux %#x: %08x -> ", __func__, bank, idx, mux, RD4(syscon, reg));
 #endif
 	WR4(syscon, reg, (mask << 16) | __SHIFTIN(mux, mask));
 #ifdef RK3399_IOMUX_DEBUG
 	printf("%08x (reg %#lx)\n", RD4(syscon, reg), reg);
 #endif
+}
 static int
 rk3399_iomux_config(struct rk3399_iomux_softc *sc, const int phandle, u_int bank, u_int idx, u_int mux)
+{
 	const int bias = fdtbus_pinctrl_parse_bias(phandle, NULL);
 	if (bias != -1)
 		rk3399_iomux_set_bias(sc, bank, idx, bias);
 	const int drv = fdtbus_pinctrl_parse_drive_strength(phandle);
 	if (drv != -1 &&
 	    rk3399_iomux_set_drive_strength(sc, bank, idx, drv) != 0)
 		return EINVAL;
 #if notyet
 	int output_value;
 	const int direction =
 	    fdtbus_pinctrl_parse_input_output(phandle, &output_value);
 	if (direction != -1) {
 		rk3399_iomux_set_direction(sc, bank, idx, direction,
 		    output_value);
+	}
 #endif
 	rk3399_iomux_set_mux(sc, bank, idx, mux);
 	return 0;
+}
 static int
 rk3399_iomux_pinctrl_set_config(device_t dev, const void *data, size_t len)
+{
 	struct rk3399_iomux_softc * const sc = device_private(dev);
 	const struct rk3399_iomux_bank *banks = sc->sc_conf->banks;
 	int pins_len;
 	if (len != 4)
 		return -1;
 	const int phandle = fdtbus_get_phandle_from_native(be32dec(data));
 	const u_int *pins = fdtbus_get_prop(phandle, "rockchip,pins", &pins_len);
 	while (pins_len >= 16) {
 		const u_int bank = be32toh(pins[0]);
 		const u_int idx = be32toh(pins[1]);
 		const u_int mux = be32toh(pins[2]);
 		const int cfg = fdtbus_get_phandle_from_native(be32toh(pins[3]));
 		struct syscon * const syscon = sc->sc_syscon[banks[bank].regs];
 		LOCK(syscon);
 		rk3399_iomux_config(sc, cfg, bank, idx, mux);
 		UNLOCK(syscon);
 		pins_len -= 16;
 		pins += 4;
+	}
 	return 0;
+}
 static struct fdtbus_pinctrl_controller_func rk3399_iomux_pinctrl_funcs = {
 	.set_config = rk3399_iomux_pinctrl_set_config,
 };
 static int
 rk3399_iomux_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 #ifdef RK3399_IOMUX_FORCE_ENABLE_SWJ_DP
 /*
  * This enables the SWJ-DP (Serial Wire JTAG Debug Port).
  * If you enable this you must also disable sdhc due to pin conflicts.
  */
 static void
 rk3399_iomux_force_enable_swj_dp(struct rk3399_iomux_softc * const sc)
+{
 	struct syscon * const syscon = sc->sc_syscon[RK_IOMUX_REGS_GRF];
 	uint32_t val;
 	aprint_normal_dev(sc->sc_dev, "enabling on-chip debugging\n");
 #define GRF_GPIO4B_IOMUX	0xe024
 #define GRF_GPIO4B_IOMUX_TCK	__BITS(5,4)
 #define GRF_GPIO4B_IOMUX_TMS	__BITS(7,6)
 #define GRF_SOC_CON7		0xe21c
 #define GRF_SOC_CON7_FORCE_JTAG	__BIT(12)
 	LOCK(syscon);
 	val = RD4(syscon, GRF_GPIO4B_IOMUX);
 	val &= ~(GRF_GPIO4B_IOMUX_TCK | GRF_GPIO4B_IOMUX_TMS);
 	val |= __SHIFTIN(0x2, GRF_GPIO4B_IOMUX_TCK);
 	val |= __SHIFTIN(0x2, GRF_GPIO4B_IOMUX_TMS);
 	WR4(syscon, GRF_GPIO4B_IOMUX, val);
 	val = RD4(syscon, GRF_SOC_CON7);
 	val |= GRF_SOC_CON7_FORCE_JTAG;
 	WR4(syscon, GRF_SOC_CON7, val);
 	UNLOCK(syscon);
+}
 #endif
 static void
 rk3399_iomux_attach(device_t parent, device_t self, void *aux)
+{
 	struct rk3399_iomux_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	int child, sub;
 	sc->sc_dev = self;
 	sc->sc_syscon[RK_IOMUX_REGS_GRF] = fdtbus_syscon_acquire(phandle, "rockchip,grf");
 	if (sc->sc_syscon[RK_IOMUX_REGS_GRF] == NULL) {
 		aprint_error(": couldn't acquire grf syscon\n");
 		return;
+	}
 	sc->sc_syscon[RK_IOMUX_REGS_PMU] = fdtbus_syscon_acquire(phandle, "rockchip,pmu");
 	if (sc->sc_syscon[RK_IOMUX_REGS_PMU] == NULL) {
 		aprint_error(": couldn't acquire pmu syscon\n");
 		return;
+	}
 	sc->sc_conf = of_search_compatible(phandle, compat_data)->data;
 	aprint_naive("\n");
 	aprint_normal(": RK3399 IOMUX control\n");
 	for (child = OF_child(phandle); child; child = OF_peer(child)) {
 		for (sub = OF_child(child); sub; sub = OF_peer(sub)) {
 			if (!of_hasprop(sub, "rockchip,pins"))
 				continue;
 			fdtbus_register_pinctrl_config(self, sub, &rk3399_iomux_pinctrl_funcs);
+		}
+	}
 	for (child = OF_child(phandle); child; child = OF_peer(child)) {
 		struct fdt_attach_args cfaa = *faa;
 		cfaa.faa_phandle = child;
 		cfaa.faa_name = fdtbus_get_string(child, "name");
 		cfaa.faa_quiet = false;
 		config_found(self, &cfaa, NULL);
+	}
 #ifdef RK3399_IOMUX_FORCE_ENABLE_SWJ_DP
 	rk3399_iomux_force_enable_swj_dp(sc);
 #endif
+}

 @@ -1,605 +1,605 @@
-/* $NetBSD: rk_vop.c,v 1.8 2021/01/25 14:20:38 thorpej Exp $ */
+/* $NetBSD: rk_vop.c,v 1.9 2021/01/27 02:00:02 thorpej Exp $ */
 /*-
  * Copyright (c) 2019 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rk_vop.c,v 1.8 2021/01/25 14:20:38 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rk_vop.c,v 1.9 2021/01/27 02:00:02 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/conf.h>
 #include <sys/sysctl.h>
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_plane_helper.h>
 #include <dev/fdt/fdtvar.h>
 #include <dev/fdt/fdt_port.h>
 #include <arm/rockchip/rk_drm.h>
 #define	VOP_REG_CFG_DONE		0x0000
 #define	 REG_LOAD_EN			__BIT(0)
 #define	VOP_SYS_CTRL			0x0008
 #define	 VOP_STANDBY_EN			__BIT(22)
 #define	 MIPI_OUT_EN			__BIT(15)
 #define	 EDP_OUT_EN			__BIT(14)
 #define	 HDMI_OUT_EN			__BIT(13)
 #define	 RGB_OUT_EN			__BIT(12)
 #define	VOP_DSP_CTRL0			0x0010
 #define	 DSP_OUT_MODE			__BITS(3,0)
 #define	  DSP_OUT_MODE_RGB888		0
 #define	  DSP_OUT_MODE_RGBaaa		15
 #define	VOP_DSP_CTRL1			0x0014
 #define	VOP_WIN0_CTRL			0x0030
 #define	 WIN0_LB_MODE			__BITS(7,5)
 #define	  WIN0_LB_MODE_RGB_3840X2	2
 #define	  WIN0_LB_MODE_RGB_2560X4	3
 #define	  WIN0_LB_MODE_RGB_1920X5	4
 #define	  WIN0_LB_MODE_RGB_1280X8	5
 #define	 WIN0_DATA_FMT			__BITS(3,1)
 #define	  WIN0_DATA_FMT_ARGB888		0
 #define	 WIN0_EN			__BIT(0)
 #define	VOP_WIN0_COLOR_KEY		0x0038
 #define	VOP_WIN0_VIR			0x003c
 #define	 WIN0_VIR_STRIDE		__BITS(13,0)
 #define	VOP_WIN0_YRGB_MST		0x0040
 #define	VOP_WIN0_ACT_INFO		0x0048
 #define	 WIN0_ACT_HEIGHT		__BITS(28,16)
 #define	 WIN0_ACT_WIDTH			__BITS(12,0)
 #define	VOP_WIN0_DSP_INFO		0x004c
 #define	 WIN0_DSP_HEIGHT		__BITS(27,16)
 #define	 WIN0_DSP_WIDTH			__BITS(11,0)
 #define	VOP_WIN0_DSP_ST			0x0050
 #define	 WIN0_DSP_YST			__BITS(28,16)
 #define	 WIN0_DSP_XST			__BITS(12,0)
 #define	VOP_POST_DSP_HACT_INFO		0x0170
 #define	 DSP_HACT_ST_POST		__BITS(28,16)
 #define	 DSP_HACT_END_POST		__BITS(12,0)
 #define	VOP_POST_DSP_VACT_INFO		0x0174
 #define	 DSP_VACT_ST_POST		__BITS(28,16)
 #define	 DSP_VACT_END_POST		__BITS(12,0)
 #define	VOP_DSP_HTOTAL_HS_END		0x0188
 #define	 DSP_HS_END			__BITS(28,16)
 #define	 DSP_HTOTAL			__BITS(12,0)
 #define	VOP_DSP_HACT_ST_END		0x018c
 #define	 DSP_HACT_ST			__BITS(28,16)
 #define	 DSP_HACT_END			__BITS(12,0)
 #define	VOP_DSP_VTOTAL_VS_END		0x0190
 #define	 DSP_VS_END			__BITS(28,16)
 #define	 DSP_VTOTAL			__BITS(12,0)
 #define	VOP_DSP_VACT_ST_END		0x0194
 #define	 DSP_VACT_ST			__BITS(28,16)
 #define	 DSP_VACT_END			__BITS(12,0)
 /*
  * Polarity fields are in different locations depending on SoC and output type,
  * but always in the same order.
  */
 #define	DSP_DCLK_POL			__BIT(3)
 #define	DSP_DEN_POL			__BIT(2)
 #define	DSP_VSYNC_POL			__BIT(1)
 #define	DSP_HSYNC_POL			__BIT(0)
 enum vop_ep_type {
 	VOP_EP_MIPI,
 	VOP_EP_EDP,
 	VOP_EP_HDMI,
 	VOP_EP_MIPI1,
 	VOP_EP_DP,
 	VOP_NEP
 };
 struct rk_vop_softc;
 struct rk_vop_config;
 struct rk_vop_crtc {
 	struct drm_crtc		base;
 	struct rk_vop_softc	*sc;
 };
 struct rk_vop_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	int			sc_phandle;
 	struct clk		*sc_dclk;
 	struct rk_vop_crtc	sc_crtc;
 	struct fdt_device_ports	sc_ports;
 	const struct rk_vop_config *sc_conf;
 };
 #define	to_rk_vop_crtc(x)	container_of(x, struct rk_vop_crtc, base)
 #define	RD4(sc, reg)				\
 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
 #define	WR4(sc, reg, val)			\
 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
 struct rk_vop_config {
 	const char		*descr;
 	u_int			out_mode;
 	void			(*init)(struct rk_vop_softc *);
 	void			(*set_polarity)(struct rk_vop_softc *,
 						enum vop_ep_type, uint32_t);
 };
 #define	RK3399_VOP_MIPI_POL	__BITS(31,28)
 #define	RK3399_VOP_EDP_POL	__BITS(27,24)
 #define	RK3399_VOP_HDMI_POL	__BITS(23,20)
 #define	RK3399_VOP_DP_POL	__BITS(19,16)
 #define	RK3399_VOP_SYS_CTRL_ENABLE	__BIT(11)
 static void
 rk3399_vop_set_polarity(struct rk_vop_softc *sc, enum vop_ep_type ep_type, uint32_t pol)
+{
 	uint32_t mask, val;
 	switch (ep_type) {
 	case VOP_EP_MIPI:
 	case VOP_EP_MIPI1:
 		mask = RK3399_VOP_MIPI_POL;
 		break;
 	case VOP_EP_EDP:
 		mask = RK3399_VOP_EDP_POL;
 		break;
 	case VOP_EP_HDMI:
 		mask = RK3399_VOP_HDMI_POL;
 		break;
 	case VOP_EP_DP:
 		mask = RK3399_VOP_DP_POL;
 		break;
 	default:
 		return;
+	}
 	val = RD4(sc, VOP_DSP_CTRL1);
 	val &= ~mask;
 	val |= __SHIFTIN(pol, mask);
 	WR4(sc, VOP_DSP_CTRL1, val);
+}
 static void
 rk3399_vop_init(struct rk_vop_softc *sc)
+{
 	uint32_t val;
 	val = RD4(sc, VOP_SYS_CTRL);
 	val |= RK3399_VOP_SYS_CTRL_ENABLE;
 	WR4(sc, VOP_SYS_CTRL, val);
+}
 static const struct rk_vop_config rk3399_vop_lit_config = {
 	.descr = "RK3399 VOPL",
 	.out_mode = DSP_OUT_MODE_RGB888,
 	.init = rk3399_vop_init,
 	.set_polarity = rk3399_vop_set_polarity,
 };
 static const struct rk_vop_config rk3399_vop_big_config = {
 	.descr = "RK3399 VOPB",
 	.out_mode = DSP_OUT_MODE_RGBaaa,
 	.init = rk3399_vop_init,
 	.set_polarity = rk3399_vop_set_polarity,
 };
 static const struct device_compatible_entry compat_data[] = {
 	{ .compat = "rockchip,rk3399-vop-big",
 	  .data = &rk3399_vop_big_config },
 	{ .compat = "rockchip,rk3399-vop-lit",
 	  .data = &rk3399_vop_lit_config },
-	{ }
+	DEVICE_COMPAT_EOL
 };
 static int
 rk_vop_mode_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb,
     int x, int y, int atomic)
+{
 	struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
 	struct rk_vop_softc * const sc = mixer_crtc->sc;
 	struct rk_drm_framebuffer *sfb = atomic?
 	    to_rk_drm_framebuffer(fb) :
 	    to_rk_drm_framebuffer(crtc->primary->fb);
 	uint64_t paddr = (uint64_t)sfb->obj->dmamap->dm_segs[0].ds_addr;
 	paddr += y * sfb->base.pitches[0];
 	paddr += x * drm_format_plane_cpp(sfb->base.pixel_format, 0);
 	KASSERT((paddr & ~0xffffffff) == 0);
 	const uint32_t vir = __SHIFTIN(sfb->base.pitches[0] / 4,
 	    WIN0_VIR_STRIDE);
 	WR4(sc, VOP_WIN0_VIR, vir);
 	/* Framebuffer start address */
 	WR4(sc, VOP_WIN0_YRGB_MST, (uint32_t)paddr);
 	return 0;
+}
 static void
 rk_vop_destroy(struct drm_crtc *crtc)
+{
 	drm_crtc_cleanup(crtc);
+}
 static const struct drm_crtc_funcs rk_vop_crtc_funcs = {
 	.set_config = drm_crtc_helper_set_config,
 	.destroy = rk_vop_destroy,
 };
 static void
 rk_vop_dpms(struct drm_crtc *crtc, int mode)
+{
 	struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
 	struct rk_vop_softc * const sc = mixer_crtc->sc;
 	uint32_t val;
 	val = RD4(sc, VOP_SYS_CTRL);
 	switch (mode) {
 	case DRM_MODE_DPMS_ON:
 		val &= ~VOP_STANDBY_EN;
 		break;
 	case DRM_MODE_DPMS_STANDBY:
 	case DRM_MODE_DPMS_SUSPEND:
 	case DRM_MODE_DPMS_OFF:
 		val |= VOP_STANDBY_EN;
 		break;
+	}
 	WR4(sc, VOP_SYS_CTRL, val);
 	/* Commit settings */
 	WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN);
+}
 static bool
 rk_vop_mode_fixup(struct drm_crtc *crtc,
     const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode)
+{
 	return true;
+}
 static int
 rk_vop_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
     struct drm_display_mode *adjusted_mode, int x, int y,
     struct drm_framebuffer *old_fb)
+{
 	struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
 	struct rk_vop_softc * const sc = mixer_crtc->sc;
 	uint32_t val;
 	u_int lb_mode;
 	int error;
 	u_int pol;
 	int connector_type = 0;
 	struct drm_connector * connector;
 	const u_int hactive = adjusted_mode->hdisplay;
 	const u_int hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 	const u_int hback_porch = adjusted_mode->htotal - adjusted_mode->hsync_end;
 	const u_int hfront_porch = adjusted_mode->hsync_start - adjusted_mode->hdisplay;
 	const u_int vactive = adjusted_mode->vdisplay;
 	const u_int vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
 	const u_int vback_porch = adjusted_mode->vtotal - adjusted_mode->vsync_end;
 	const u_int vfront_porch = adjusted_mode->vsync_start - adjusted_mode->vdisplay;
 	error = clk_set_rate(sc->sc_dclk, adjusted_mode->clock * 1000);
 	if (error != 0)
 		DRM_ERROR("couldn't set pixel clock: %d\n", error);
 	val = __SHIFTIN(hactive - 1, WIN0_ACT_WIDTH) |
 	      __SHIFTIN(vactive - 1, WIN0_ACT_HEIGHT);
 	WR4(sc, VOP_WIN0_ACT_INFO, val);
 	val = __SHIFTIN(hactive - 1, WIN0_DSP_WIDTH) |
 	      __SHIFTIN(vactive - 1, WIN0_DSP_HEIGHT);
 	WR4(sc, VOP_WIN0_DSP_INFO, val);
 	val = __SHIFTIN(hsync_len + hback_porch, WIN0_DSP_XST) |
 	      __SHIFTIN(vsync_len + vback_porch, WIN0_DSP_YST);
 	WR4(sc, VOP_WIN0_DSP_ST, val);
 	WR4(sc, VOP_WIN0_COLOR_KEY, 0);
 	if (adjusted_mode->hdisplay > 2560)
 		lb_mode = WIN0_LB_MODE_RGB_3840X2;
 	else if (adjusted_mode->hdisplay > 1920)
 		lb_mode = WIN0_LB_MODE_RGB_2560X4;
 	else if (adjusted_mode->hdisplay > 1280)
 		lb_mode = WIN0_LB_MODE_RGB_1920X5;
 	else
 		lb_mode = WIN0_LB_MODE_RGB_1280X8;
 	val = __SHIFTIN(lb_mode, WIN0_LB_MODE) |
 	      __SHIFTIN(WIN0_DATA_FMT_ARGB888, WIN0_DATA_FMT) |
 	      WIN0_EN;
 	WR4(sc, VOP_WIN0_CTRL, val);
 	rk_vop_mode_do_set_base(crtc, old_fb, x, y, 0);
 	pol = DSP_DCLK_POL;
 	if ((adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) != 0)
 		pol |= DSP_HSYNC_POL;
 	if ((adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) != 0)
 		pol |= DSP_VSYNC_POL;
 	drm_for_each_connector(connector, crtc->dev) {
 		if ((connector->encoder) == NULL)
 			continue;
 		if (connector->encoder->crtc == crtc) {
 			connector_type = connector->connector_type;
 			break;
+		}
+	}
 	switch (connector_type) {
 	case DRM_MODE_CONNECTOR_HDMIA:
 		sc->sc_conf->set_polarity(sc, VOP_EP_HDMI, pol);
 		break;
 	case DRM_MODE_CONNECTOR_eDP:
 		sc->sc_conf->set_polarity(sc, VOP_EP_EDP, pol);
 		break;
+	}
 	val = RD4(sc, VOP_SYS_CTRL);
 	val &= ~VOP_STANDBY_EN;
 	val &= ~(MIPI_OUT_EN|EDP_OUT_EN|HDMI_OUT_EN|RGB_OUT_EN);
 	switch (connector_type) {
 	case DRM_MODE_CONNECTOR_HDMIA:
 		val |= HDMI_OUT_EN;
 		break;
 	case DRM_MODE_CONNECTOR_eDP:
 		val |= EDP_OUT_EN;
 		break;
+	}
 	WR4(sc, VOP_SYS_CTRL, val);
 	val = RD4(sc, VOP_DSP_CTRL0);
 	val &= ~DSP_OUT_MODE;
 	val |= __SHIFTIN(sc->sc_conf->out_mode, DSP_OUT_MODE);
 	WR4(sc, VOP_DSP_CTRL0, val);
 	val = __SHIFTIN(hsync_len + hback_porch, DSP_HACT_ST_POST) |
 	      __SHIFTIN(hsync_len + hback_porch + hactive, DSP_HACT_END_POST);
 	WR4(sc, VOP_POST_DSP_HACT_INFO, val);
 	val = __SHIFTIN(hsync_len + hback_porch, DSP_HACT_ST) |
 	      __SHIFTIN(hsync_len + hback_porch + hactive, DSP_HACT_END);
 	WR4(sc, VOP_DSP_HACT_ST_END, val);
 	val = __SHIFTIN(hsync_len, DSP_HTOTAL) |
 	      __SHIFTIN(hsync_len + hback_porch + hactive + hfront_porch, DSP_HS_END);
 	WR4(sc, VOP_DSP_HTOTAL_HS_END, val);
 	val = __SHIFTIN(vsync_len + vback_porch, DSP_VACT_ST_POST) |
 	      __SHIFTIN(vsync_len + vback_porch + vactive, DSP_VACT_END_POST);
 	WR4(sc, VOP_POST_DSP_VACT_INFO, val);
 	val = __SHIFTIN(vsync_len + vback_porch, DSP_VACT_ST) |
 	      __SHIFTIN(vsync_len + vback_porch + vactive, DSP_VACT_END);
 	WR4(sc, VOP_DSP_VACT_ST_END, val);
 	val = __SHIFTIN(vsync_len, DSP_VTOTAL) |
 	      __SHIFTIN(vsync_len + vback_porch + vactive + vfront_porch, DSP_VS_END);
 	WR4(sc, VOP_DSP_VTOTAL_VS_END, val);
 	return 0;
+}
 static int
 rk_vop_mode_set_base(struct drm_crtc *crtc, int x, int y,
     struct drm_framebuffer *old_fb)
+{
 	struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
 	struct rk_vop_softc * const sc = mixer_crtc->sc;
 	rk_vop_mode_do_set_base(crtc, old_fb, x, y, 0);
 	/* Commit settings */
 	WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN);
 	return 0;
+}
 static int
 rk_vop_mode_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
     int x, int y, enum mode_set_atomic state)
+{
 	struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
 	struct rk_vop_softc * const sc = mixer_crtc->sc;
 	rk_vop_mode_do_set_base(crtc, fb, x, y, 1);
 	/* Commit settings */
 	WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN);
 	return 0;
+}
 static void
 rk_vop_disable(struct drm_crtc *crtc)
+{
+}
 static void
 rk_vop_prepare(struct drm_crtc *crtc)
+{
+}
 static void
 rk_vop_commit(struct drm_crtc *crtc)
+{
 	struct rk_vop_crtc *mixer_crtc = to_rk_vop_crtc(crtc);
 	struct rk_vop_softc * const sc = mixer_crtc->sc;
 	/* Commit settings */
 	WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN);
+}
 static const struct drm_crtc_helper_funcs rk_vop_crtc_helper_funcs = {
 	.dpms = rk_vop_dpms,
 	.mode_fixup = rk_vop_mode_fixup,
 	.mode_set = rk_vop_mode_set,
 	.mode_set_base = rk_vop_mode_set_base,
 	.mode_set_base_atomic = rk_vop_mode_set_base_atomic,
 	.disable = rk_vop_disable,
 	.prepare = rk_vop_prepare,
 	.commit = rk_vop_commit,
 };
 static int
 rk_vop_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate)
+{
 	struct rk_vop_softc * const sc = device_private(dev);
 	struct drm_device *ddev;
 	if (!activate)
 		return EINVAL;
 	ddev = rk_drm_port_device(&sc->sc_ports);
 	if (ddev == NULL) {
 		DRM_ERROR("couldn't find DRM device\n");
 		return ENXIO;
+	}
 	if (sc->sc_crtc.sc == NULL) {
 		sc->sc_crtc.sc = sc;
 		drm_crtc_init(ddev, &sc->sc_crtc.base, &rk_vop_crtc_funcs);
 		drm_crtc_helper_add(&sc->sc_crtc.base, &rk_vop_crtc_helper_funcs);
 		aprint_debug_dev(dev, "using CRTC %d for %s\n",
 		    drm_crtc_index(&sc->sc_crtc.base), sc->sc_conf->descr);
+	}
 	const u_int ep_index = fdt_endpoint_index(ep);
 	if (ep_index >= VOP_NEP) {
 		DRM_ERROR("endpoint index %d out of range\n", ep_index);
 		return ENXIO;
+	}
 	return fdt_endpoint_activate(ep, activate);
+}
 static void *
 rk_vop_ep_get_data(device_t dev, struct fdt_endpoint *ep)
+{
 	struct rk_vop_softc * const sc = device_private(dev);
 	return &sc->sc_crtc.base;
+}
 static int
 rk_vop_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 static void
 rk_vop_attach(device_t parent, device_t self, void *aux)
+{
 	struct rk_vop_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	const char * const reset_names[] = { "axi", "ahb", "dclk" };
 	const char * const clock_names[] = { "aclk_vop", "hclk_vop" };
 	struct fdtbus_reset *rst;
 	bus_addr_t addr;
 	bus_size_t size;
 	u_int n;
 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	fdtbus_clock_assign(phandle);
 	for (n = 0; n < __arraycount(reset_names); n++) {
 		rst = fdtbus_reset_get(phandle, reset_names[n]);
 		if (rst == NULL || fdtbus_reset_deassert(rst) != 0) {
 			aprint_error(": couldn't de-assert reset %s\n", reset_names[n]);
 			return;
+		}
+	}
 	for (n = 0; n < __arraycount(clock_names); n++) {
 		if (fdtbus_clock_enable(phandle, clock_names[n], true) != 0) {
 			aprint_error(": couldn't enable clock %s\n", clock_names[n]);
 			return;
+		}
+	}
 	sc->sc_dclk = fdtbus_clock_get(phandle, "dclk_vop");
 	if (sc->sc_dclk == NULL || clk_enable(sc->sc_dclk) != 0) {
 		aprint_error(": couldn't enable clock %s\n", "dclk_vop");
 		return;
+	}
 	sc->sc_dev = self;
 	sc->sc_bst = faa->faa_bst;
 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
 		aprint_error(": couldn't map registers\n");
 		return;
+	}
 	sc->sc_phandle = faa->faa_phandle;
 	sc->sc_conf = of_search_compatible(phandle, compat_data)->data;
 	aprint_naive("\n");
 	aprint_normal(": %s\n", sc->sc_conf->descr);
 	if (sc->sc_conf->init != NULL)
 		sc->sc_conf->init(sc);
 	sc->sc_ports.dp_ep_activate = rk_vop_ep_activate;
 	sc->sc_ports.dp_ep_get_data = rk_vop_ep_get_data;
 	fdt_ports_register(&sc->sc_ports, self, phandle, EP_DRM_CRTC);
 	const int port_phandle = of_find_firstchild_byname(phandle, "port");
 	if (port_phandle > 0)
 		rk_drm_register_port(port_phandle, &sc->sc_ports);
+}
 CFATTACH_DECL_NEW(rk_vop, sizeof(struct rk_vop_softc),
 	rk_vop_match, rk_vop_attach, NULL, NULL);

 @@ -1,249 +1,249 @@
-/* $NetBSD: rk_pwm.c,v 1.5 2021/01/25 14:20:38 thorpej Exp $ */
+/* $NetBSD: rk_pwm.c,v 1.6 2021/01/27 02:00:02 thorpej Exp $ */
 /*-
  * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: rk_pwm.c,v 1.5 2021/01/25 14:20:38 thorpej Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rk_pwm.c,v 1.6 2021/01/27 02:00:02 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/time.h>
 #include <dev/pwm/pwmvar.h>
 #include <dev/fdt/fdtvar.h>
 #define	PWM0_CNT		0x00
 #define	PWM0_PERIOD_HPR		0x04
 #define	PWM0_DUTY_LPR		0x08
 #define	PWM0_CTRL		0x0c
 #define	 CTRL_RPT		__BITS(31,24)
 #define	 CTRL_SCALE		__BITS(23,16)
 #define	 CTRL_PRESCALE		__BITS(14,12)
 #define	 CTRL_CLK_SEL		__BIT(9)
 #define	 CTRL_LP_EN		__BIT(8)
 #define	 CTRL_OUTPUT_MODE	__BIT(5)
 #define	 CTRL_INACTIVE_POL	__BIT(4)
 #define	 CTRL_DUTY_POL		__BIT(3)
 #define	 CTRL_PWM_MODE		__BITS(2,1)
 #define	  CTRL_PWM_MODE_ONESHOT		0
 #define	  CTRL_PWM_MODE_CONTINUOUS	1
 #define	  CTRL_PWM_MODE_CAPTURE		2
 #define	 CTRL_PWM_EN		__BIT(0)
 enum rk_pwm_type {
 	PWM_RK3288 = 1,
 };
 static const struct device_compatible_entry compat_data[] = {
 	{ .compat = "rockchip,rk3288-pwm",	.value = PWM_RK3288 },
-	{ }
+	DEVICE_COMPAT_EOL
 };
 struct rk_pwm_softc {
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	struct pwm_controller	sc_pwm;
 	struct pwm_config	sc_conf;
 	u_int			sc_clkfreq;
 };
 #define	PWM_READ(sc, reg)		\
 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
 #define	PWM_WRITE(sc, reg, val)		\
 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
 static pwm_tag_t
 rk_pwm_get_tag(device_t dev, const void *data, size_t len)
+{
 	struct rk_pwm_softc * const sc = device_private(dev);
 	const u_int *pwm = data;
 	if (len != 16)
 		return NULL;
 	const u_int index = be32toh(pwm[1]);
 	if (index != 0)
 		return NULL;
 	const u_int period = be32toh(pwm[2]);
 	const u_int polarity = be32toh(pwm[3]);
 	sc->sc_conf.period = period;
 	sc->sc_conf.polarity = polarity ? PWM_ACTIVE_LOW : PWM_ACTIVE_HIGH;
 	return &sc->sc_pwm;
+}
 static struct fdtbus_pwm_controller_func rk_pwm_funcs = {
 	.get_tag = rk_pwm_get_tag
 };
 static int
 rk_pwm_enable(pwm_tag_t pwm, bool enable)
+{
 	struct rk_pwm_softc * const sc = device_private(pwm->pwm_dev);
 	uint32_t ctrl, octrl;
 	octrl = ctrl = PWM_READ(sc, PWM0_CTRL);
 	if (enable)
 		ctrl |= CTRL_PWM_EN;
 	else
 		ctrl &= ~CTRL_PWM_EN;
 	if (ctrl != octrl)
 		PWM_WRITE(sc, PWM0_CTRL, ctrl);
 	return 0;
+}
 static int
 rk_pwm_get_config(pwm_tag_t pwm, struct pwm_config *conf)
+{
 	struct rk_pwm_softc * const sc = device_private(pwm->pwm_dev);
 #if 0
 	/* XXX may be useful someday */
 	uint32_t ctrl, period, duty;
 	u_int div;
 	ctrl = PWM_READ(sc, PWM0_CTRL);
 	period = PWM_READ(sc, PWM0_PERIOD_HPR);
 	duty = PWM_READ(sc, PWM0_DUTY_LPR);
 	if (ctrl & CTRL_CLK_SEL) {
 		div = __SHIFTOUT(ctrl, CTRL_SCALE) * 2;
 		if (div == 0)
 			div = 512;
 	} else {
 		div = 1;
+	}
 	div /= (1 << __SHIFTOUT(ctrl, CTRL_PRESCALE));
 	const uint64_t rate = sc->sc_clkfreq / div;
 	conf->polarity = (ctrl & CTRL_DUTY_POL) ? PWM_ACTIVE_HIGH : PWM_ACTIVE_LOW;
         conf->period = (u_int)(((uint64_t)period * 1000000000) / rate);
         conf->duty_cycle = (u_int)(((uint64_t)duty * 1000000000) / rate);
 #else
 	*conf = sc->sc_conf;
 #endif
 	return 0;
+}
 static int
 rk_pwm_set_config(pwm_tag_t pwm, const struct pwm_config *conf)
+{
 	struct rk_pwm_softc * const sc = device_private(pwm->pwm_dev);
 	uint32_t ctrl;
 	const uint64_t rate = sc->sc_clkfreq;
 	const uint32_t period = (u_int)((conf->period * rate) / 1000000000);
 	const uint32_t duty = (u_int)((conf->duty_cycle * rate) / 1000000000);
 	/* Preserve PWM_EN flag */
 	ctrl = PWM_READ(sc, PWM0_CTRL) & CTRL_PWM_EN;
 	ctrl |= __SHIFTIN(CTRL_PWM_MODE_CONTINUOUS, CTRL_PWM_MODE);
 	if (conf->polarity == PWM_ACTIVE_HIGH)
 		ctrl |= CTRL_DUTY_POL;
 	else
 		ctrl |= CTRL_INACTIVE_POL;
 	PWM_WRITE(sc, PWM0_CTRL, 0);
 	PWM_WRITE(sc, PWM0_PERIOD_HPR, period);
 	PWM_WRITE(sc, PWM0_DUTY_LPR, duty);
 	PWM_WRITE(sc, PWM0_CTRL, ctrl);
 	sc->sc_conf = *conf;
 	return 0;
+}
 static int
 rk_pwm_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 static void
 rk_pwm_attach(device_t parent, device_t self, void *aux)
+{
 	struct rk_pwm_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	struct clk *clk;
 	bus_addr_t addr;
 	bus_size_t size;
 	int error;
 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	clk = fdtbus_clock_get_index(phandle, 0);
 	if (clk == NULL) {
 		aprint_error(": couldn't get clock\n");
 		return;
+	}
 	sc->sc_dev = self;
 	sc->sc_clkfreq = clk_get_rate(clk);
 	sc->sc_bst = faa->faa_bst;
 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
 	if (error) {
 		aprint_error(": couldn't map %#" PRIxBUSADDR ": %d",
 		    addr, error);
 		return;
+	}
 	aprint_naive("\n");
 	aprint_normal(": PWM\n");
 	sc->sc_pwm.pwm_enable = rk_pwm_enable;
 	sc->sc_pwm.pwm_get_config = rk_pwm_get_config;
 	sc->sc_pwm.pwm_set_config = rk_pwm_set_config;
 	sc->sc_pwm.pwm_dev = self;
 	fdtbus_register_pwm_controller(self, phandle,
 	    &rk_pwm_funcs);
+}
 CFATTACH_DECL_NEW(rk_pwm, sizeof(struct rk_pwm_softc),
 	rk_pwm_match, rk_pwm_attach, NULL, NULL);

 @@ -1,386 +1,386 @@
-/*	$NetBSD: rk_v1crypto.c,v 1.5 2021/01/25 14:20:38 thorpej Exp $	*/
+/*	$NetBSD: rk_v1crypto.c,v 1.6 2021/01/27 02:00:02 thorpej Exp $	*/
 /*-
  * Copyright (c) 2020 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Taylor R. Campbell.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * rk_v1crypto -- Rockchip crypto v1 driver
+ *
  * This is just the RNG for now.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: rk_v1crypto.c,v 1.5 2021/01/25 14:20:38 thorpej Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rk_v1crypto.c,v 1.6 2021/01/27 02:00:02 thorpej Exp $");
 #include <sys/types.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/errno.h>
 #include <sys/mutex.h>
 #include <sys/rndsource.h>
 #include <sys/sysctl.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/rockchip/rk_v1crypto.h>
 struct rk_v1crypto_softc {
 	device_t			sc_dev;
 	bus_space_tag_t			sc_bst;
 	bus_space_handle_t		sc_bsh;
 	kmutex_t			sc_lock;
 	struct krndsource		sc_rndsource;
 	struct rk_v1crypto_sysctl {
 		struct sysctllog		*cy_log;
 		const struct sysctlnode		*cy_root_node;
 	}				sc_sysctl;
 };
 static int rk_v1crypto_match(device_t, cfdata_t, void *);
 static void rk_v1crypto_attach(device_t, device_t, void *);
 static int rk_v1crypto_selftest(struct rk_v1crypto_softc *);
 static void rk_v1crypto_rndsource_attach(struct rk_v1crypto_softc *);
 static void rk_v1crypto_rng_get(size_t, void *);
 static void rk_v1crypto_sysctl_attach(struct rk_v1crypto_softc *);
 static int rk_v1crypto_sysctl_rng(SYSCTLFN_ARGS);
 static int rk_v1crypto_rng(struct rk_v1crypto_softc *,
     uint32_t[static RK_V1CRYPTO_TRNG_NOUT]);
 static uint32_t
 RKC_READ(struct rk_v1crypto_softc *sc, bus_addr_t reg)
+{
 	return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg);
+}
 static void
 RKC_WRITE(struct rk_v1crypto_softc *sc, bus_addr_t reg, uint32_t v)
+{
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, v);
+}
 static inline void
 RKC_CTRL(struct rk_v1crypto_softc *sc, uint16_t m, uint16_t v)
+{
 	uint32_t c = 0;
 	c |= __SHIFTIN(m, RK_V1CRYPTO_CTRL_MASK);
 	c |= __SHIFTIN(v, m);
 	RKC_WRITE(sc, RK_V1CRYPTO_CTRL, c);
+}
 CFATTACH_DECL_NEW(rk_v1crypto, sizeof(struct rk_v1crypto_softc),
     rk_v1crypto_match, rk_v1crypto_attach, NULL, NULL);
 static const struct device_compatible_entry compat_data[] = {
 	{ .compat = "rockchip,rk3288-crypto" },
-	{ }
+	DEVICE_COMPAT_EOL
 };
 static int
 rk_v1crypto_match(device_t parent, cfdata_t cf, void *aux)
+{
 	const struct fdt_attach_args *const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 static void
 rk_v1crypto_attach(device_t parent, device_t self, void *aux)
+{
 	static const char *const clks[] = {"aclk", "hclk", "sclk", "apb_pclk"};
 	struct rk_v1crypto_softc *const sc = device_private(self);
 	const struct fdt_attach_args *const faa = aux;
 	bus_addr_t addr;
 	bus_size_t size;
 	const int phandle = faa->faa_phandle;
 	struct fdtbus_reset *rst;
 	unsigned i;
 	uint32_t ctrl;
 	fdtbus_clock_assign(phandle);
 	sc->sc_dev = self;
 	sc->sc_bst = faa->faa_bst;
 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
 	/* Get and map device registers.  */
 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
 		aprint_error(": couldn't map registers\n");
 		return;
+	}
 	/* Enable the clocks.  */
 	for (i = 0; i < __arraycount(clks); i++) {
 		if (fdtbus_clock_enable(phandle, clks[i], true) != 0) {
 			aprint_error(": couldn't enable %s clock\n", clks[i]);
 			return;
+		}
+	}
 	/* Get a reset handle if we need and try to deassert it.  */
 	if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) {
 		if (fdtbus_reset_deassert(rst) != 0) {
 			aprint_error(": couldn't de-assert reset\n");
 			return;
+		}
+	}
 	aprint_naive("\n");
 	aprint_normal(": Crypto v1\n");
 	/*
 	 * Enable ring oscillator to start gathering entropy, and set
 	 * up the crypto clock to sample it once every 100 cycles.
+	 *
 	 * The ring oscillator can run even when the clock is gated or
 	 * flush is asserted, and the longer we run it, the less it
 	 * will be synchronized with the main clock owing to jitter
 	 * ideally from unpredictable thermal noise.
 	 */
 	ctrl = RK_V1CRYPTO_TRNG_CTRL_OSC_ENABLE;
 	ctrl |= __SHIFTIN(100, RK_V1CRYPTO_TRNG_CTRL_CYCLES);
 	RKC_WRITE(sc, RK_V1CRYPTO_TRNG_CTRL, ctrl);
 	if (rk_v1crypto_selftest(sc))
 		return;
 	rk_v1crypto_rndsource_attach(sc);
 	rk_v1crypto_sysctl_attach(sc);
+}
 static int
 rk_v1crypto_selftest(struct rk_v1crypto_softc *sc)
+{
 	static const uint32_t key[4] = {0};
 	static const uint32_t input[4] = {0};
 	static const uint32_t expected[4] = {
 x66e94bd4, 0xef8a2c3b, 0x884cfa59, 0xca342b2e,
 	};
 	uint32_t output[4];
 	uint32_t ctrl;
 	unsigned i, timo;
 	/* Program the key and input block.  */
 	for (i = 0; i < 4; i++)
 		RKC_WRITE(sc, RK_V1CRYPTO_AES_DIN(i), key[i]);
 	for (i = 0; i < 4; i++)
 		RKC_WRITE(sc, RK_V1CRYPTO_AES_DIN(i), input[i]);
 	/*
 	 * Set up the AES unit to do AES-128 `ECB' (i.e., just the raw
 	 * AES permutation) in the encryption direction.
 	 */
 	ctrl = 0;
 	ctrl |= RK_V1CRYPTO_AES_CTRL_KEYCHANGE;
 	ctrl |= __SHIFTIN(RK_V1CRYPTO_AES_CTRL_MODE_ECB,
 	    RK_V1CRYPTO_AES_CTRL_MODE);
 	ctrl |= __SHIFTIN(RK_V1CRYPTO_AES_CTRL_KEYSIZE_128,
 	    RK_V1CRYPTO_AES_CTRL_KEYSIZE);
 	ctrl |= __SHIFTIN(RK_V1CRYPTO_AES_CTRL_DIR_ENC,
 	    RK_V1CRYPTO_AES_CTRL_DIR);
 	RKC_WRITE(sc, RK_V1CRYPTO_AES_CTRL, ctrl);
 	/* Kick it off.  */
 	RKC_CTRL(sc, RK_V1CRYPTO_CTRL_AES_START, 1);
 	/* Wait up to 1ms for it to complete.  */
 	timo = 1000;
 	while (RKC_READ(sc, RK_V1CRYPTO_CTRL) & RK_V1CRYPTO_CTRL_AES_START) {
 		if (--timo == 0) {
 			device_printf(sc->sc_dev, "AES self-test timed out\n");
 			return -1;
+		}
 		DELAY(1);
+	}
 	/* Read the output.  */
 	for (i = 0; i < 4; i++)
 		output[i] = RKC_READ(sc, RK_V1CRYPTO_AES_DOUT(i));
 	/* Verify the output.  */
 	for (i = 0; i < 4; i++) {
 		if (output[i] != expected[i]) {
 			device_printf(sc->sc_dev, "AES self-test failed\n");
 			return -1;
+		}
+	}
 	/* Success!  */
 	return 0;
+}
 static void
 rk_v1crypto_rndsource_attach(struct rk_v1crypto_softc *sc)
+{
 	device_t self = sc->sc_dev;
 	rndsource_setcb(&sc->sc_rndsource, rk_v1crypto_rng_get, sc);
 	rnd_attach_source(&sc->sc_rndsource, device_xname(self),
 	    RND_TYPE_RNG, RND_FLAG_DEFAULT|RND_FLAG_HASCB);
+}
 static void
 rk_v1crypto_rng_get(size_t nbytes, void *cookie)
+{
 	struct rk_v1crypto_softc *sc = cookie;
 	device_t self = sc->sc_dev;
 	uint32_t buf[RK_V1CRYPTO_TRNG_NOUT];
 	uint32_t entropybits = NBBY*sizeof(buf)/2; /* be conservative */
 	unsigned n = RK_V1CRYPTO_TRNG_NOUT;
 	int error;
 	size_t nbits = NBBY*nbytes;
 	while (nbits) {
 		CTASSERT((RK_V1CRYPTO_TRNG_NOUT % 2) == 0);
 		error = rk_v1crypto_rng(sc, buf);
 		if (error) {
 			device_printf(self, "timed out\n");
 			break;
+		}
 		if (consttime_memequal(buf, buf + n/2, n/2)) {
 			device_printf(self, "failed repeated output test\n");
 			break;
+		}
 		rnd_add_data_sync(&sc->sc_rndsource, buf, sizeof buf,
 		    entropybits);
 		nbits -= MIN(nbits, MAX(1, entropybits));
+	}
 	explicit_memset(buf, 0, sizeof buf);
+}
 static void
 rk_v1crypto_sysctl_attach(struct rk_v1crypto_softc *sc)
+{
 	device_t self = sc->sc_dev;
 	struct rk_v1crypto_sysctl *cy = &sc->sc_sysctl;
 	int error;
 	/* hw.rkv1cryptoN (node) */
 	error = sysctl_createv(&cy->cy_log, 0, NULL, &cy->cy_root_node,
 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, device_xname(self),
 	    SYSCTL_DESCR("rk crypto v1 engine knobs"),
 	    NULL, 0, NULL, 0,
 	    CTL_HW, CTL_CREATE, CTL_EOL);
 	if (error) {
 		aprint_error_dev(self,
 		    "failed to set up sysctl hw.%s: %d\n",
 		    device_xname(self), error);
 		return;
+	}
 	/* hw.rkv1cryptoN.rng (`struct', 32-byte array) */
 	sysctl_createv(&cy->cy_log, 0, &cy->cy_root_node, NULL,
 	    CTLFLAG_PERMANENT|CTLFLAG_READONLY|CTLFLAG_PRIVATE, CTLTYPE_STRUCT,
 	    "rng", SYSCTL_DESCR("Read up to 32 bytes out of the TRNG"),
 	    &rk_v1crypto_sysctl_rng, 0, sc, 0, CTL_CREATE, CTL_EOL);
 	if (error) {
 		aprint_error_dev(self,
 		    "failed to set up sysctl hw.%s.rng: %d\n",
 		    device_xname(self), error);
 		return;
+	}
+}
 static int
 rk_v1crypto_sysctl_rng(SYSCTLFN_ARGS)
+{
 	uint32_t buf[RK_V1CRYPTO_TRNG_NOUT];
 	struct sysctlnode node = *rnode;
 	struct rk_v1crypto_softc *sc = node.sysctl_data;
 	size_t size;
 	int error;
 	/* If oldp == NULL, the caller wants to learn the size.  */
 	if (oldp == NULL) {
 		*oldlenp = sizeof buf;
 		return 0;
+	}
 	/* Verify the output buffer size is reasonable.  */
 	size = *oldlenp;
 	if (size > sizeof buf)	/* size_t, so never negative */
 		return E2BIG;
 	if (size == 0)
 		return 0;	/* nothing to do */
 	/* Generate data.  */
 	error = rk_v1crypto_rng(sc, buf);
 	if (error)
 		return error;
 	/* Copy out the data.  */
 	node.sysctl_data = buf;
 	node.sysctl_size = size;
 	error = sysctl_lookup(SYSCTLFN_CALL(&node));
 	/* Clear the buffer.  */
 	explicit_memset(buf, 0, sizeof buf);
 	/* Return the sysctl_lookup error, if any.  */
 	return error;
+}
 static int
 rk_v1crypto_rng(struct rk_v1crypto_softc *sc,
     uint32_t buf[static RK_V1CRYPTO_TRNG_NOUT])
+{
 	unsigned i, timo;
 	int error;
 	/* Acquire lock to serialize access to TRNG.  */
 	mutex_enter(&sc->sc_lock);
 	/*
 	 * Query TRNG and wait up to 1ms for it to post.  Empirically,
 	 * this takes around 120us.
 	 */
 	RKC_CTRL(sc, RK_V1CRYPTO_CTRL_TRNG_START, 1);
 	timo = 1000;
 	while (RKC_READ(sc, RK_V1CRYPTO_CTRL) & RK_V1CRYPTO_CTRL_TRNG_START) {
 		if (--timo == 0) {
 			error = ETIMEDOUT;
 			goto out;
+		}
 		DELAY(1);
+	}
 	/* Read out the data.  */
 	for (i = 0; i < RK_V1CRYPTO_TRNG_NOUT; i++)
 		buf[i] = RKC_READ(sc, RK_V1CRYPTO_TRNG_DOUT(i));
 	/* Success!  */
 	error = 0;
 out:	mutex_exit(&sc->sc_lock);
 	return error;
+}

 @@ -1,894 +1,894 @@
-/*	$NetBSD: rk_tsadc.c,v 1.10 2021/01/25 14:20:38 thorpej Exp $	*/
+/*	$NetBSD: rk_tsadc.c,v 1.11 2021/01/27 02:00:02 thorpej Exp $	*/
 /*
  * Copyright (c) 2019 Matthew R. Green
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rk_tsadc.c,v 1.10 2021/01/25 14:20:38 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rk_tsadc.c,v 1.11 2021/01/27 02:00:02 thorpej Exp $");
 /*
  * Driver for the TSADC temperature sensor monitor in RK3328 and RK3399.
+ *
  * TODO:
  * - handle setting various temp values
  * - handle DT trips/temp value defaults
  * - interrupts aren't triggered (test by lowering warn/crit values), and
  *   once they work, make the interrupt do something
  */
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/time.h>
 #include <sys/kmem.h>
 #include <dev/fdt/fdtvar.h>
 #include <dev/fdt/syscon.h>
 #include <dev/sysmon/sysmonvar.h>
 #ifdef RKTSADC_DEBUG
 #define DPRINTF(fmt, ...) \
 	printf("%s:%d: " fmt "\n", __func__, __LINE__, ## __VA_ARGS__)
 #else
 #define DPRINTF(fmt, ...)
 #endif
 /* Register definitions */
 #define TSADC_USER_CON                          0x00
 #define  TSADC_USER_CON_ADC_STATUS              __BIT(12)
 #define  TSADC_USER_CON_INTER_PD_SOC            __BITS(11,6)
 #define  TSADC_USER_CON_START                   __BIT(5)
 #define  TSADC_USER_CON_START_MODE              __BIT(4)
 #define  TSADC_USER_CON_ADC_POWER_CTRL          __BIT(3)
 #define  TSADC_USER_CON_ADC_INPUT_SRC_SEL       __BITS(2,0)
 #define TSADC_AUTO_CON                          0x04
 #define  TSADC_AUTO_CON_LAST_TSHUT_2CRU         __BIT(25)
 #define  TSADC_AUTO_CON_LAST_TSHUT_2GPIO        __BIT(24)
 #define  TSADC_AUTO_CON_SAMPLE_DLY_SEL          __BIT(17)
 #define  TSADC_AUTO_CON_AUTO_STATUS             __BIT(16)
 #define  TSADC_AUTO_CON_SRC1_LT_EN              __BIT(13)
 #define  TSADC_AUTO_CON_SRC0_LT_EN              __BIT(12)
 #define  TSADC_AUTO_CON_TSHUT_POLARITY          __BIT(8)
 #define  TSADC_AUTO_CON_SRC1_EN                 __BIT(5)
 #define  TSADC_AUTO_CON_SRC0_EN                 __BIT(4)
 #define  TSADC_AUTO_CON_Q_SEL                   __BIT(1)
 #define  TSADC_AUTO_CON_AUTO_EN                 __BIT(0)
 #define TSADC_INT_EN                            0x08
 #define  TSADC_INT_EN_EOC_INT_EN                __BIT(16)
 #define  TSADC_INT_EN_LT_INTEN_SRC1             __BIT(13)
 #define  TSADC_INT_EN_LT_INTEN_SRC0             __BIT(12)
 #define  TSADC_INT_EN_TSHUT_2CRU_EN_SRC1        __BIT(9)
 #define  TSADC_INT_EN_TSHUT_2CRU_EN_SRC0        __BIT(8)
 #define  TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1       __BIT(5)
 #define  TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0       __BIT(4)
 #define  TSADC_INT_EN_HT_INTEN_SRC1             __BIT(1)
 #define  TSADC_INT_EN_HT_INTEN_SRC0             __BIT(0)
 #define TSADC_INT_PD                            0x0c
 #define  TSADC_INT_PD_EOC_INT_PD                __BIT(16)
 #define  TSADC_INT_PD_LT_IRQ_SRC1               __BIT(13)
 #define  TSADC_INT_PD_LT_IRQ_SRC0               __BIT(12)
 #define  TSADC_INT_PD_TSHUT_O_SRC1              __BIT(5)
 #define  TSADC_INT_PD_TSHUT_O_SRC0              __BIT(4)
 #define  TSADC_INT_PD_HT_IRQ_SRC1               __BIT(1)
 #define  TSADC_INT_PD_HT_IRQ_SRC0               __BIT(0)
 #define TSADC_DATA0                             0x20
 #define  TSADC_DATA0_ADC_DATA                   __BITS(11,0)
 #define TSADC_DATA1                             0x24
 #define  TSADC_DATA1_ADC_DATA                   __BITS(11,0)
 #define TSADC_COMP0_INT                         0x30
 #define  TSADC_COMP0_INT_COMP_SRC0              __BITS(11,0)
 #define TSADC_COMP1_INT                         0x34
 #define  TSADC_COMP1_INT_COMP_SRC1              __BITS(11,0)
 #define TSADC_COMP0_SHUT                        0x40
 #define  TSADC_COMP0_SHUT_COMP_SRC0             __BITS(11,0)
 #define TSADC_COMP1_SHUT                        0x44
 #define  TSADC_COMP1_SHUT_COMP_SRC1             __BITS(11,0)
 #define TSADC_HIGH_INT_DEBOUNCE                 0x60
 #define  TSADC_HIGH_INT_DEBOUNCE_TEMP           __BITS(7,0)
 #define TSADC_HIGH_TSHUT_DEBOUNCE               0x64
 #define  TSADC_HIGH_TSHUT_DEBOUNCE_TEMP         __BITS(7,0)
 #define TSADC_AUTO_PERIOD                       0x68
 #define  TSADC_AUTO_PERIOD_TEMP                 __BITS(31,0)
 #define TSADC_AUTO_PERIOD_HT                    0x6c
 #define  TSADC_AUTO_PERIOD_HT_TEMP              __BITS(31,0)
 #define TSADC_COMP0_LOW_INT                     0x80
 #define  TSADC_COMP0_LOW_INT_COMP_SRC0          __BITS(11,0)
 #define TSADC_COMP1_LOW_INT                     0x84
 #define  TSADC_COMP1_LOW_INT_COMP_SRC1          __BITS(11,0)
 #define RK3328_TSADC_AUTO_PERIOD_TIME           250 /* 250ms */
 #define RK3399_TSADC_AUTO_PERIOD_TIME           1875 /* 2.5ms */
 #define TSADC_HT_DEBOUNCE_COUNT                 4
 /*
  * All this magic is taking from the Linux rockchip_thermal driver.
+ *
  * VCM means "voltage common mode", but the documentation for RK3399
  * does not mention this and I don't know what any of this really
  * is for.
  */
 #define RK3399_GRF_SARADC_TESTBIT               0xe644
 #define  RK3399_GRF_SARADC_TESTBIT_ON           (0x10001 << 2)
 #define RK3399_GRF_TSADC_TESTBIT_L              0xe648
 #define  RK3399_GRF_TSADC_TESTBIT_VCM_EN_L      (0x10001 << 7)
 #define RK3399_GRF_TSADC_TESTBIT_H              0xe64c
 #define  RK3399_GRF_TSADC_TESTBIT_VCM_EN_H      (0x10001 << 7)
 #define  RK3399_GRF_TSADC_TESTBIT_H_ON          (0x10001 << 2)
 #define TEMP_uC_TO_uK             273150000
 #define TSHUT_MODE_CPU    0
 #define TSHUT_MODE_GPIO   1
 #define TSHUT_LOW_ACTIVE  0
 #define TSHUT_HIGH_ACTIVE 1
 #define TSHUT_DEF_TEMP    95000
 #define TSADC_DATA_MAX    0xfff
 #define MAX_SENSORS       2
 typedef struct rk_data_array {
 	uint32_t data;  /* register value */
 	int temp;       /* micro-degC */
 } rk_data_array;
 struct rk_tsadc_softc;
 typedef struct rk_data {
 	const rk_data_array	*rd_array;
 	size_t			 rd_size;
 	void			(*rd_init)(struct rk_tsadc_softc *, int, int);
 	bool			 rd_decr;  /* lower values -> higher temp */
 	unsigned		 rd_min, rd_max;
 	unsigned		 rd_auto_period;
 	unsigned		 rd_num_sensors;
 } rk_data;
 /* Per-sensor data */
 struct rk_tsadc_sensor {
 	envsys_data_t	s_data;
 	bool		s_attached;
 	/* TSADC register offsets for this sensor */
 	unsigned	s_data_reg;
 	unsigned	s_comp_tshut;
 	unsigned	s_comp_int;
 	/* enable bit in AUTO_CON register */
 	unsigned	s_comp_int_en;
 	/* warn/crit values in micro Kelvin */
 	int		s_warn;
 	int		s_tshut;
 };
 struct rk_tsadc_softc {
 	device_t		sc_dev;
 	int			sc_phandle;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	size_t			sc_size;
 	uint32_t		sc_data_mask;
 	void			*sc_ih;
 	struct sysmon_envsys	*sc_sme;
 	struct rk_tsadc_sensor	sc_sensors[MAX_SENSORS];
 	struct clk		*sc_clock;
 	struct clk		*sc_clockapb;
 	struct fdtbus_reset	*sc_reset;
 	struct syscon		*sc_syscon;
 	const rk_data		*sc_rd;
 };
 static int rk_tsadc_match(device_t, cfdata_t, void *);
 static void rk_tsadc_attach(device_t, device_t, void *);
 static int rk_tsadc_detach(device_t, int);
 static int rk_tsadc_init_clocks(struct rk_tsadc_softc *);
 static void rk_tsadc_init_counts(struct rk_tsadc_softc *);
 static void rk_tsadc_tshut_set(struct rk_tsadc_softc *s);
 static void rk_tsadc_init_tshut(struct rk_tsadc_softc *, int, int);
 static void rk_tsadc_init_rk3328(struct rk_tsadc_softc *, int, int);
 static void rk_tsadc_init_rk3399(struct rk_tsadc_softc *, int, int);
 static void rk_tsadc_init_enable(struct rk_tsadc_softc *);
 static void rk_tsadc_init(struct rk_tsadc_softc *, int, int);
 static void rk_tsadc_refresh(struct sysmon_envsys *, envsys_data_t *);
 static void rk_tsadc_get_limits(struct sysmon_envsys *, envsys_data_t *,
                                 sysmon_envsys_lim_t *, uint32_t *);
 static int rk_tsadc_intr(void *);
 static int rk_tsadc_data_to_temp(struct rk_tsadc_softc *, uint32_t);
 static uint32_t rk_tsadc_temp_to_data(struct rk_tsadc_softc *, int);
 /* RK3328/RK3399 compatible sensors */
 static const struct rk_tsadc_sensor rk_tsadc_sensors[] = {
+	{
 	  .s_data = { .desc = "CPU" },
 	  .s_data_reg = TSADC_DATA0,
 	  .s_comp_tshut = TSADC_COMP0_SHUT,
 	  .s_comp_int = TSADC_COMP0_INT,
 	  .s_comp_int_en = TSADC_AUTO_CON_SRC0_EN,
 	  /*
 	   * XXX DT has:
 	   * cpu_alert1: cpu_alert1 {
 	   *	temperature = <75000>;
 	   *	hysteresis = <2000>;
 	   * cpu_crit: cpu_crit {
 	   *    temperature = <95000>;
 	   *    hysteresis = <2000>;
 	   * pull out of here?
 	   * do something with hysteresis?  put in debounce?
+	   *
 	   * Note that tshut may be overriden by the board specific DT.
 	   */
 	  .s_warn = 75000000,
 	  .s_tshut = 95000000,
 	}, {
 	  .s_data = { .desc = "GPU" },
 	  .s_data_reg = TSADC_DATA1,
 	  .s_comp_tshut = TSADC_COMP1_SHUT,
 	  .s_comp_int = TSADC_COMP1_INT,
 	  .s_comp_int_en = TSADC_AUTO_CON_SRC1_EN,
 	  .s_warn = 75000000,
 	  .s_tshut = 95000000,
 	},
 };
 /*
  * Table from RK3328 manual.  Note that the manual lists valid numbers as
  * 4096 - number.  This also means it is increasing not decreasing for
  * higher temps, and the min and max are also offset from 4096.
  */
 #define RK3328_DATA_OFFSET (4096)
 static const rk_data_array rk3328_data_array[] = {
 #define ENTRY(d,C) \
 	{ .data = RK3328_DATA_OFFSET - (d), .temp = (C) * 1000 * 1000, }
 	ENTRY(TSADC_DATA_MAX,    -40),
 	ENTRY(3800, -40),
 	ENTRY(3792, -35),
 	ENTRY(3783, -30),
 	ENTRY(3774, -25),
 	ENTRY(3765, -20),
 	ENTRY(3756, -15),
 	ENTRY(3747, -10),
 	ENTRY(3737,  -5),
 	ENTRY(3728,   0),
 	ENTRY(3718,   5),
 	ENTRY(3708,  10),
 	ENTRY(3698,  15),
 	ENTRY(3688,  20),
 	ENTRY(3678,  25),
 	ENTRY(3667,  30),
 	ENTRY(3656,  35),
 	ENTRY(3645,  40),
 	ENTRY(3634,  45),
 	ENTRY(3623,  50),
 	ENTRY(3611,  55),
 	ENTRY(3600,  60),
 	ENTRY(3588,  65),
 	ENTRY(3575,  70),
 	ENTRY(3563,  75),
 	ENTRY(3550,  80),
 	ENTRY(3537,  85),
 	ENTRY(3524,  90),
 	ENTRY(3510,  95),
 	ENTRY(3496, 100),
 	ENTRY(3482, 105),
 	ENTRY(3467, 110),
 	ENTRY(3452, 115),
 	ENTRY(3437, 120),
 	ENTRY(3421, 125),
 	ENTRY(0,    125),
 #undef ENTRY
 };
 /* Table from RK3399 manual */
 static const rk_data_array rk3399_data_array[] = {
 #define ENTRY(d,C)	{ .data = (d), .temp = (C) * 1000 * 1000, }
 	ENTRY(0,   -40),
 	ENTRY(402, -40),
 	ENTRY(410, -35),
 	ENTRY(419, -30),
 	ENTRY(427, -25),
 	ENTRY(436, -20),
 	ENTRY(444, -15),
 	ENTRY(453, -10),
 	ENTRY(461,  -5),
 	ENTRY(470,   0),
 	ENTRY(478,   5),
 	ENTRY(487,  10),
 	ENTRY(496,  15),
 	ENTRY(504,  20),
 	ENTRY(513,  25),
 	ENTRY(521,  30),
 	ENTRY(530,  35),
 	ENTRY(538,  40),
 	ENTRY(547,  45),
 	ENTRY(555,  50),
 	ENTRY(564,  55),
 	ENTRY(573,  60),
 	ENTRY(581,  65),
 	ENTRY(590,  70),
 	ENTRY(599,  75),
 	ENTRY(607,  80),
 	ENTRY(616,  85),
 	ENTRY(624,  90),
 	ENTRY(633,  95),
 	ENTRY(642, 100),
 	ENTRY(650, 105),
 	ENTRY(659, 110),
 	ENTRY(668, 115),
 	ENTRY(677, 120),
 	ENTRY(685, 125),
 	ENTRY(TSADC_DATA_MAX, 125),
 #undef ENTRY
 };
 static const rk_data rk3328_data_table = {
 	.rd_array = rk3328_data_array,
 	.rd_size = __arraycount(rk3328_data_array),
 	.rd_init = rk_tsadc_init_rk3328,
 	.rd_decr = false,
 	.rd_max = RK3328_DATA_OFFSET - 3420,
 	.rd_min = RK3328_DATA_OFFSET - 3801,
 	.rd_auto_period = RK3328_TSADC_AUTO_PERIOD_TIME,
 	.rd_num_sensors = 1,
 };
 static const rk_data rk3399_data_table = {
 	.rd_array = rk3399_data_array,
 	.rd_size = __arraycount(rk3399_data_array),
 	.rd_init = rk_tsadc_init_rk3399,
 	.rd_decr = false,
 	.rd_max = 686,
 	.rd_min = 401,
 	.rd_auto_period = RK3399_TSADC_AUTO_PERIOD_TIME,
 	.rd_num_sensors = 2,
 };
 static const struct device_compatible_entry compat_data[] = {
 	{ .compat = "rockchip,rk3328-tsadc",	.data = &rk3328_data_table },
 	{ .compat = "rockchip,rk3399-tsadc",	.data = &rk3399_data_table },
-	{ }
+	DEVICE_COMPAT_EOL
 };
 #define	TSADC_READ(sc, reg)		\
 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
 #define	TSADC_WRITE(sc, reg, val)	\
 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
 CFATTACH_DECL3_NEW(rk_tsadc, sizeof(struct rk_tsadc_softc),
 	rk_tsadc_match, rk_tsadc_attach, rk_tsadc_detach, NULL, NULL, NULL,
 	DVF_DETACH_SHUTDOWN);
 /* init/teardown support */
 static int
 rk_tsadc_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 static void
 rk_tsadc_attach(device_t parent, device_t self, void *aux)
+{
 	struct rk_tsadc_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	char intrstr[128];
 	const int phandle = faa->faa_phandle;
 	bus_addr_t addr;
 	int mode, polarity, tshut_temp;
 	sc->sc_dev = self;
 	sc->sc_phandle = phandle;
 	sc->sc_bst = faa->faa_bst;
 	aprint_naive("\n");
 	aprint_normal(": RK3328/3399 Temperature Sensor ADC\n");
 	sc->sc_sme = sysmon_envsys_create();
 	sc->sc_sme->sme_name = device_xname(self);
 	sc->sc_sme->sme_cookie = sc;
 	sc->sc_sme->sme_refresh = rk_tsadc_refresh;
 	sc->sc_sme->sme_get_limits = rk_tsadc_get_limits;
 	sc->sc_data_mask = TSADC_DATA_MAX;
 	pmf_device_register(self, NULL, NULL);
 	sc->sc_rd = of_search_compatible(faa->faa_phandle, compat_data)->data;
 	/* Default to tshut via gpio and tshut low is active */
 	if (of_getprop_uint32(phandle, "rockchip,hw-tshut-mode",
 			      &mode) != 0) {
 		aprint_error(": could not get TSHUT mode, default to GPIO");
 		mode = TSHUT_MODE_GPIO;
+	}
 	if (mode != TSHUT_MODE_CPU && mode != TSHUT_MODE_GPIO) {
 		aprint_error(": TSHUT mode should be 0 or 1\n");
 		goto fail;
+	}
 	if (of_getprop_uint32(phandle, "rockchip,hw-tshut-polarity",
 			      &polarity) != 0) {
 		aprint_error(": could not get TSHUT polarity, default to low");
 		polarity = TSHUT_LOW_ACTIVE;
+	}
 	if (of_getprop_uint32(phandle,
 			      "rockchip,hw-tshut-temp", &tshut_temp) != 0) {
 		aprint_error(": could not get TSHUT temperature, default to %u",
 			     TSHUT_DEF_TEMP);
 		tshut_temp = TSHUT_DEF_TEMP;
+	}
 	tshut_temp *= 1000;	/* convert fdt ms -> us */
 	memcpy(sc->sc_sensors, rk_tsadc_sensors, sizeof(sc->sc_sensors));
 	for (unsigned n = 0; n < sc->sc_rd->rd_num_sensors; n++) {
 		struct rk_tsadc_sensor *rks = &sc->sc_sensors[n];
 		rks->s_data.flags = ENVSYS_FMONLIMITS;
 		rks->s_data.units = ENVSYS_STEMP;
 		rks->s_data.state = ENVSYS_SINVALID;
 		if (sysmon_envsys_sensor_attach(sc->sc_sme, &rks->s_data))
 			goto fail;
 		rks->s_attached = true;
 		rks->s_tshut = tshut_temp;
 #if 0
 		// testing
 		rks->s_tshut = 68000000;
 		rks->s_warn = 61000000;
 #endif
+	}
 	sc->sc_syscon = fdtbus_syscon_acquire(phandle, "rockchip,grf");
 	if (sc->sc_syscon == NULL) {
 		aprint_error(": couldn't get grf syscon\n");
 		goto fail;
+	}
 	if (fdtbus_get_reg(phandle, 0, &addr, &sc->sc_size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		sc->sc_size = 0;
 		goto fail;
+	}
 	if (bus_space_map(sc->sc_bst, addr, sc->sc_size, 0, &sc->sc_bsh) != 0) {
 		aprint_error(": couldn't map registers\n");
 		sc->sc_size = 0;
 		goto fail;
+	}
 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error(": failed to decode interrupt\n");
 		goto fail;
+	}
 	sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, FDT_INTR_MPSAFE,
 	    rk_tsadc_intr, sc, device_xname(self));
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(self, "couldn't establish interrupt on %s\n",
 		    intrstr);
 		goto fail;
+	}
 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
 	if (rk_tsadc_init_clocks(sc)) {
 		aprint_error(": couldn't enable clocks\n");
 		return;
+	}
 	/*
 	 * Manual says to setup auto period (both), high temp (interrupt),
 	 * high temp (shutdown), enable high temp resets (TSHUT to GPIO
 	 * or reset chip), set the debounce times, and, finally, enable the
 	 * controller iself.
 	 */
 	rk_tsadc_init(sc, mode, polarity);
 	return;
 fail:
 	rk_tsadc_detach(self, 0);
+}
 static int
 rk_tsadc_detach(device_t self, int flags)
+{
 	struct rk_tsadc_softc *sc = device_private(self);
 	pmf_device_deregister(self);
 	for (unsigned n = 0; n < sc->sc_rd->rd_num_sensors; n++) {
 		struct rk_tsadc_sensor *rks = &sc->sc_sensors[n];
 		if (rks->s_attached) {
 			sysmon_envsys_sensor_detach(sc->sc_sme, &rks->s_data);
 			rks->s_attached = false;
+		}
+	}
 	sysmon_envsys_unregister(sc->sc_sme);
 	if (sc->sc_clockapb)
 		clk_disable(sc->sc_clockapb);
 	if (sc->sc_clock)
 		clk_disable(sc->sc_clock);
 	if (sc->sc_ih)
 		fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih);
 	if (sc->sc_size)
 		bus_space_unmap(sc->sc_bst, sc->sc_bsh, sc->sc_size);
 	sysmon_envsys_destroy(sc->sc_sme);
 	return 0;
+}
 static int
 rk_tsadc_init_clocks(struct rk_tsadc_softc *sc)
+{
 	int error;
 	fdtbus_clock_assign(sc->sc_phandle);
 	sc->sc_reset = fdtbus_reset_get(sc->sc_phandle, "tsadc-apb");
 	sc->sc_clock = fdtbus_clock_get(sc->sc_phandle, "tsadc");
 	sc->sc_clockapb = fdtbus_clock_get(sc->sc_phandle, "apb_pclk");
 	if (sc->sc_reset == NULL ||
 	    sc->sc_clock == NULL ||
 	    sc->sc_clockapb == NULL)
 		return EINVAL;
 	fdtbus_reset_assert(sc->sc_reset);
 	error = clk_enable(sc->sc_clock);
 	if (error) {
 		fdtbus_reset_deassert(sc->sc_reset);
 		return error;
+	}
 	error = clk_enable(sc->sc_clockapb);
 	DELAY(20);
 	fdtbus_reset_deassert(sc->sc_reset);
 	return error;
+}
 static void
 rk_tsadc_init_counts(struct rk_tsadc_softc *sc)
+{
 	TSADC_WRITE(sc, TSADC_AUTO_PERIOD, sc->sc_rd->rd_auto_period);
 	TSADC_WRITE(sc, TSADC_AUTO_PERIOD_HT, sc->sc_rd->rd_auto_period);
 	TSADC_WRITE(sc, TSADC_HIGH_INT_DEBOUNCE, TSADC_HT_DEBOUNCE_COUNT);
 	TSADC_WRITE(sc, TSADC_HIGH_TSHUT_DEBOUNCE, TSADC_HT_DEBOUNCE_COUNT);
+}
 /* Configure the hardware with the tshut setup. */
 static void
 rk_tsadc_tshut_set(struct rk_tsadc_softc *sc)
+{
 	uint32_t val = TSADC_READ(sc, TSADC_AUTO_CON);
 	for (unsigned n = 0; n < sc->sc_rd->rd_num_sensors; n++) {
 		struct rk_tsadc_sensor *rks = &sc->sc_sensors[n];
 		uint32_t data, warndata;
 		if (!rks->s_attached)
 			continue;
 		data = rk_tsadc_temp_to_data(sc, rks->s_tshut);
 		warndata = rk_tsadc_temp_to_data(sc, rks->s_warn);
 		DPRINTF("(%s:%s): tshut/data %d/%u warn/data %d/%u",
 			sc->sc_sme->sme_name, rks->s_data.desc,
 			rks->s_tshut, data,
 			rks->s_warn, warndata);
 		if (data == sc->sc_data_mask) {
 			aprint_error_dev(sc->sc_dev,
 			    "Failed converting critical temp %u.%06u to code",
 			    rks->s_tshut / 1000000, rks->s_tshut % 1000000);
 			continue;
+		}
 		if (warndata == sc->sc_data_mask) {
 			aprint_error_dev(sc->sc_dev,
 			    "Failed converting warn temp %u.%06u to code",
 			    rks->s_warn / 1000000, rks->s_warn % 1000000);
 			continue;
+		}
 		TSADC_WRITE(sc, rks->s_comp_tshut, data);
 		TSADC_WRITE(sc, rks->s_comp_int, warndata);
 		val |= rks->s_comp_int_en;
+	}
 	TSADC_WRITE(sc, TSADC_AUTO_CON, val);
+}
 static void
 rk_tsadc_init_tshut(struct rk_tsadc_softc *sc, int mode, int polarity)
+{
 	uint32_t val;
 	/* Handle TSHUT temp setting. */
 	rk_tsadc_tshut_set(sc);
 	/* Handle TSHUT mode setting. */
 	val = TSADC_READ(sc, TSADC_INT_EN);
 	if (mode == TSHUT_MODE_CPU) {
 		val |= TSADC_INT_EN_TSHUT_2CRU_EN_SRC1 |
 		       TSADC_INT_EN_TSHUT_2CRU_EN_SRC0;
 		val &= ~(TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1 |
 			 TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0);
 	} else {
 		KASSERT(mode == TSHUT_MODE_GPIO);
 		val &= ~(TSADC_INT_EN_TSHUT_2CRU_EN_SRC1 |
 			 TSADC_INT_EN_TSHUT_2CRU_EN_SRC0);
 		val |= TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1 |
 		       TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0;
+	}
 	TSADC_WRITE(sc, TSADC_INT_EN, val);
 	/* Handle TSHUT polarity setting. */
 	val = TSADC_READ(sc, TSADC_AUTO_CON);
 	if (polarity == TSHUT_HIGH_ACTIVE)
 		val |= TSADC_AUTO_CON_TSHUT_POLARITY;
 	else
 		val &= ~TSADC_AUTO_CON_TSHUT_POLARITY;
 	TSADC_WRITE(sc, TSADC_AUTO_CON, val);
+}
 static void
 rk_tsadc_init_rk3328(struct rk_tsadc_softc *sc, int mode, int polarity)
+{
 	rk_tsadc_init_tshut(sc, mode, polarity);
 	rk_tsadc_init_counts(sc);
+}
 static void
 rk_tsadc_init_rk3399(struct rk_tsadc_softc *sc, int mode, int polarity)
+{
 	syscon_lock(sc->sc_syscon);
 	syscon_write_4(sc->sc_syscon, RK3399_GRF_TSADC_TESTBIT_L,
 				      RK3399_GRF_TSADC_TESTBIT_VCM_EN_L);
 	syscon_write_4(sc->sc_syscon, RK3399_GRF_TSADC_TESTBIT_H,
 				      RK3399_GRF_TSADC_TESTBIT_VCM_EN_H);
 	DELAY(20);
 	syscon_write_4(sc->sc_syscon, RK3399_GRF_SARADC_TESTBIT,
 				      RK3399_GRF_SARADC_TESTBIT_ON);
 	syscon_write_4(sc->sc_syscon, RK3399_GRF_TSADC_TESTBIT_H,
 				      RK3399_GRF_TSADC_TESTBIT_H_ON);
 	DELAY(100);
 	syscon_unlock(sc->sc_syscon);
 	rk_tsadc_init_counts(sc);
 	rk_tsadc_init_tshut(sc, mode, polarity);
+}
 static void
 rk_tsadc_init_enable(struct rk_tsadc_softc *sc)
+{
 	uint32_t val;
 	val = TSADC_READ(sc, TSADC_AUTO_CON);
 	val |= TSADC_AUTO_CON_AUTO_STATUS |
 	       TSADC_AUTO_CON_SRC1_LT_EN | TSADC_AUTO_CON_SRC0_LT_EN;
 	TSADC_WRITE(sc, TSADC_AUTO_CON, val);
 	/* Finally, register & enable the controller */
 	sysmon_envsys_register(sc->sc_sme);
 	val = TSADC_READ(sc, TSADC_AUTO_CON);
 	val |= TSADC_AUTO_CON_AUTO_EN | TSADC_AUTO_CON_Q_SEL;
 	TSADC_WRITE(sc, TSADC_AUTO_CON, val);
+}
 static void
 rk_tsadc_init(struct rk_tsadc_softc *sc, int mode, int polarity)
+{
 	(*sc->sc_rd->rd_init)(sc, mode, polarity);
 	rk_tsadc_init_enable(sc);
+}
 /* run time support */
 /* given edata, find the matching rk sensor structure */
 static struct rk_tsadc_sensor *
 rk_tsadc_edata_to_sensor(struct rk_tsadc_softc * const sc, envsys_data_t *edata)
+{
 	for (unsigned n = 0; n < sc->sc_rd->rd_num_sensors; n++) {
 		struct rk_tsadc_sensor *rks = &sc->sc_sensors[n];
 		if (&rks->s_data == edata)
 			return rks;
+	}
 	return NULL;
+}
 static void
 rk_tsadc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
+{
 	struct rk_tsadc_softc * const sc = sme->sme_cookie;
 	struct rk_tsadc_sensor *rks = rk_tsadc_edata_to_sensor(sc, edata);
 	unsigned data;
 	int temp;
 	if (rks == NULL)
 		return;
 	data = TSADC_READ(sc, rks->s_data_reg) & sc->sc_data_mask;
 	temp = rk_tsadc_data_to_temp(sc, data);
 	DPRINTF("(%s:%s): temp/data %d/%u",
 		sc->sc_sme->sme_name, rks->s_data.desc,
 		temp, data);
 	if (temp == sc->sc_data_mask) {
 		edata->state = ENVSYS_SINVALID;
 	} else {
 		edata->value_cur = temp + TEMP_uC_TO_uK;
 		edata->state = ENVSYS_SVALID;
+	}
+}
 static void
 rk_tsadc_get_limits(struct sysmon_envsys *sme,
 		    envsys_data_t *edata,
 		    sysmon_envsys_lim_t *lim,
 		    uint32_t *props)
+{
 	struct rk_tsadc_softc *sc = sme->sme_cookie;
 	struct rk_tsadc_sensor *rks = rk_tsadc_edata_to_sensor(sc, edata);
 	if (rks == NULL)
 		return;
 	lim->sel_critmax = rks->s_tshut + TEMP_uC_TO_uK;
 	lim->sel_warnmax = rks->s_warn + TEMP_uC_TO_uK;
 	*props = PROP_CRITMAX | PROP_WARNMAX;
+}
 /* XXX do something with interrupts that don't happen yet.  */
 static int
 rk_tsadc_intr(void *arg)
+{
 	struct rk_tsadc_softc * const sc = arg;
 	uint32_t val;
 	/* XXX */
 	DPRINTF("(%s): interrupted", sc->sc_sme->sme_name);
 	for (unsigned n = 0; n < __arraycount(rk_tsadc_sensors); n++) {
 		struct rk_tsadc_sensor *rks = &sc->sc_sensors[n];
 		rk_tsadc_refresh(sc->sc_sme, (envsys_data_t *)rks);
+	}
 	/* ack interrupt */
 	val = TSADC_READ(sc, TSADC_INT_PD);
 	TSADC_WRITE(sc, TSADC_INT_PD, val & ~TSADC_INT_PD_EOC_INT_PD);
 	return 1;
+}
 /*
  * Convert TDASC data codes to temp and reverse.  The manual only has codes
  * and temperature values in 5 degC intervals, but says that interpolation
  * can be done to achieve better resolution between these values, and that
  * the spacing is linear.
  */
 static int
 rk_tsadc_data_to_temp(struct rk_tsadc_softc *sc, uint32_t data)
+{
 	unsigned i;
 	const rk_data *rd = sc->sc_rd;
 	if (data > rd->rd_max || data < rd->rd_min) {
 		DPRINTF("data out of range (%u > %u || %u < %u)",
 			data, rd->rd_max, data, rd->rd_min);
 		return sc->sc_data_mask;
+	}
 	for (i = 1; i < rd->rd_size; i++) {
 		if (rd->rd_array[i].data >= data) {
 			int temprange, offset;
 			uint32_t datarange, datadiff;
 			unsigned first, secnd;
 			if (rd->rd_array[i].data == data)
 				return rd->rd_array[i].temp;
 			/* must interpolate */
 			if (rd->rd_decr) {
 				first = i;
 				secnd = i+1;
 			} else {
 				first = i;
 				secnd = i-1;
+			}
 			temprange = rd->rd_array[first].temp -
 				    rd->rd_array[secnd].temp;
 			datarange = rd->rd_array[first].data -
 				    rd->rd_array[secnd].data;
 			datadiff = data - rd->rd_array[secnd].data;
 			offset = (temprange * datadiff) / datarange;
 			return rd->rd_array[secnd].temp + offset;
+		}
+	}
 	panic("didn't find range");
+}
 static uint32_t
 rk_tsadc_temp_to_data(struct rk_tsadc_softc *sc, int temp)
+{
 	unsigned i;
 	const rk_data *rd = sc->sc_rd;
 	for (i = 1; i < rd->rd_size; i++) {
 		if (rd->rd_array[i].temp >= temp) {
 			int temprange, tempdiff;
 			uint32_t datarange, offset;
 			unsigned first, secnd;
 			if (rd->rd_array[i].temp == temp)
 				return rd->rd_array[i].data;
 			/* must interpolate */
 			if (rd->rd_decr) {
 				first = i;
 				secnd = i+1;
 			} else {
 				first = i;
 				secnd = i-1;
+			}
 			datarange = rd->rd_array[first].data -
 				    rd->rd_array[secnd].data;
 			temprange = rd->rd_array[first].temp -
 				    rd->rd_array[secnd].temp;
 			tempdiff = temp - rd->rd_array[secnd].temp;
 			offset = (datarange * tempdiff) / temprange;
 			return rd->rd_array[secnd].data + offset;
+		}
+	}
 	return sc->sc_data_mask;
+}

 @@ -1,428 +1,428 @@
-/* $NetBSD: rk_usb.c,v 1.9 2021/01/25 14:20:38 thorpej Exp $ */
+/* $NetBSD: rk_usb.c,v 1.10 2021/01/27 02:00:02 thorpej Exp $ */
 /*-
  * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rk_usb.c,v 1.9 2021/01/25 14:20:38 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rk_usb.c,v 1.10 2021/01/27 02:00:02 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/time.h>
 #include <sys/kmem.h>
 #include <dev/clk/clk_backend.h>
 #include <dev/fdt/fdtvar.h>
 #include <dev/fdt/syscon.h>
 static int rk_usb_match(device_t, cfdata_t, void *);
 static void rk_usb_attach(device_t, device_t, void *);
 #define	RK3328_CON0_REG			0x100
 #define	RK3328_CON1_REG			0x104
 #define	RK3328_CON2_REG			0x108
 #define	 RK3328_USBPHY_COMMONONN	__BIT(4)
 #define	RK3399_GRF_USB20_PHY0_CON0_REG	0x0e450
 #define	RK3399_GRF_USB20_PHY1_CON0_REG	0x0e460
 #define	 RK3399_USBPHY_COMMONONN	__BIT(4)
 #define	RK3399_GRF_USB20_PHY0_CON1_REG	0x0e454
 #define	RK3399_GRF_USB20_PHY1_CON1_REG	0x0e464
 #define	RK3399_GRF_USB20_PHY0_CON2_REG	0x0e458
 #define	RK3399_GRF_USB20_PHY1_CON2_REG	0x0e468
 #define	 RK3399_USBPHY_SUSPEND_N	__BIT(1)
 #define	 RK3399_USBPHY_UTMI_SEL		__BIT(0)
 #define	RK3399_PHY_NO(_sc)	((_sc)->sc_reg == 0xe450 ? 0 : 1)
 enum rk_usb_type {
 	USB_RK3328 = 1,
 	USB_RK3399,
 };
 static const struct device_compatible_entry compat_data[] = {
 	{ .compat = "rockchip,rk3328-usb2phy",	.value = USB_RK3328 },
 	{ .compat = "rockchip,rk3399-usb2phy",	.value = USB_RK3399 },
-	{ }
+	DEVICE_COMPAT_EOL
 };
 struct rk_usb_clk {
 	struct clk		base;
 };
 struct rk_usb_softc {
 	device_t		sc_dev;
 	struct syscon		*sc_syscon;
 	enum rk_usb_type	sc_type;
 	struct clk_domain	sc_clkdom;
 	struct rk_usb_clk	sc_usbclk;
 	bus_addr_t		sc_reg;
 };
 CFATTACH_DECL_NEW(rk_usb, sizeof(struct rk_usb_softc),
 	rk_usb_match, rk_usb_attach, NULL, NULL);
 static struct clk *
 rk_usb_clk_get(void *priv, const char *name)
+{
 	struct rk_usb_softc * const sc = priv;
 	if (strcmp(name, sc->sc_usbclk.base.name) != 0)
 		return NULL;
 	return &sc->sc_usbclk.base;
+}
 static void
 rk_usb_clk_put(void *priv, struct clk *clk)
+{
+}
 static u_int
 rk_usb_clk_get_rate(void *priv, struct clk *clk)
+{
 	return 480000000;
+}
 static int
 rk_usb_clk_enable(void *priv, struct clk *clk)
+{
 	struct rk_usb_softc * const sc = priv;
 	uint32_t reg, write_mask, write_val;
 	switch (sc->sc_type) {
 	case USB_RK3328:
 		reg = RK3328_CON2_REG;
 		write_mask = RK3328_USBPHY_COMMONONN << 16;
 		write_val = 0;
 		break;
 	case USB_RK3399:
 		reg = RK3399_PHY_NO(sc) == 0 ?
 		    RK3399_GRF_USB20_PHY0_CON0_REG :
 		    RK3399_GRF_USB20_PHY1_CON0_REG;
 		write_mask = RK3399_USBPHY_COMMONONN << 16;
 		write_val = 0;
 		break;
 	default:
 		return ENXIO;
+	}
 	syscon_lock(sc->sc_syscon);
 	syscon_write_4(sc->sc_syscon, reg, write_mask | write_val);
 	syscon_unlock(sc->sc_syscon);
 	return 0;
+}
 static int
 rk_usb_clk_disable(void *priv, struct clk *clk)
+{
 	struct rk_usb_softc * const sc = priv;
 	uint32_t reg, write_mask, write_val;
 	switch (sc->sc_type) {
 	case USB_RK3328:
 		reg = RK3328_CON2_REG;
 		write_mask = RK3328_USBPHY_COMMONONN << 16;
 		write_val = RK3328_USBPHY_COMMONONN;
 		break;
 	case USB_RK3399:
 		reg = RK3399_PHY_NO(sc) == 0 ?
 		    RK3399_GRF_USB20_PHY0_CON0_REG :
 		    RK3399_GRF_USB20_PHY1_CON0_REG;
 		write_mask = RK3399_USBPHY_COMMONONN << 16;
 		write_val = RK3399_USBPHY_COMMONONN;
 		break;
 	default:
 		return ENXIO;
+	}
 	syscon_lock(sc->sc_syscon);
 	syscon_write_4(sc->sc_syscon, reg, write_mask | write_val);
 	syscon_unlock(sc->sc_syscon);
 	return 0;
+}
 static const struct clk_funcs rk_usb_clk_funcs = {
 	.get = rk_usb_clk_get,
 	.put = rk_usb_clk_put,
 	.get_rate = rk_usb_clk_get_rate,
 	.enable = rk_usb_clk_enable,
 	.disable = rk_usb_clk_disable,
 };
 static struct clk *
 rk_usb_fdt_decode(device_t dev, int cc_phandle, const void *data, size_t len)
+{
 	struct rk_usb_softc * const sc = device_private(dev);
 	if (len != 0)
 		return NULL;
 	return &sc->sc_usbclk.base;
+}
 static const struct fdtbus_clock_controller_func rk_usb_fdt_funcs = {
 	.decode = rk_usb_fdt_decode
 };
 static int
 rk_usb_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 static void
 rk_usb_attach(device_t parent, device_t self, void *aux)
+{
 	struct rk_usb_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	struct clk *clk;
 	int child;
 	/* Cache the base address of this PHY so we know which instance we are */
 	if (fdtbus_get_reg(phandle, 0, &sc->sc_reg, NULL) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	clk = fdtbus_clock_get(phandle, "phyclk");
 	if (clk && clk_enable(clk) != 0) {
 		aprint_error(": couldn't enable phy clock\n");
 		return;
+	}
 	sc->sc_dev = self;
 	sc->sc_type = of_search_compatible(phandle, compat_data)->value;
 	sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(phandle));
 	if (sc->sc_syscon == NULL) {
 		aprint_error(": couldn't get grf syscon\n");
 		return;
+	}
 	const char *clkname = fdtbus_get_string(phandle, "clock-output-names");
 	if (clkname == NULL)
 		clkname = faa->faa_name;
 	sc->sc_clkdom.name = device_xname(self);
 	sc->sc_clkdom.funcs = &rk_usb_clk_funcs;
 	sc->sc_clkdom.priv = sc;
 	sc->sc_usbclk.base.domain = &sc->sc_clkdom;
 	sc->sc_usbclk.base.name = kmem_asprintf("%s", clkname);
 	clk_attach(&sc->sc_usbclk.base);
 	aprint_naive("\n");
 	aprint_normal(": USB2 PHY\n");
 	fdtbus_register_clock_controller(self, phandle, &rk_usb_fdt_funcs);
 	for (child = OF_child(phandle); child; child = OF_peer(child)) {
 		if (!fdtbus_status_okay(child))
 			continue;
 		struct fdt_attach_args cfaa = *faa;
 		cfaa.faa_phandle = child;
 		cfaa.faa_name = fdtbus_get_string(child, "name");
 		cfaa.faa_quiet = false;
 		config_found(self, &cfaa, NULL);
+	}
+}
 /*
  * USB PHY
  */
 static int rk_usbphy_match(device_t, cfdata_t, void *);
 static void rk_usbphy_attach(device_t, device_t, void *);
 struct rk_usbphy_softc {
 	device_t	sc_dev;
 	int		sc_phandle;
 	struct fdtbus_regulator *sc_supply;
 };
 CFATTACH_DECL_NEW(rk_usbphy, sizeof(struct rk_usbphy_softc),
 	rk_usbphy_match, rk_usbphy_attach, NULL, NULL);
 static void *
 rk_usbphy_acquire(device_t dev, const void *data, size_t len)
+{
 	struct rk_usbphy_softc * const sc = device_private(dev);
 	if (len != 0)
 		return NULL;
 	return sc;
+}
 static void
 rk_usbphy_release(device_t dev, void *priv)
+{
+}
 static int
 rk_usbphy_otg_enable(device_t dev, void *priv, bool enable)
+{
 	struct rk_usbphy_softc * const sc = device_private(dev);
 	struct rk_usb_softc * const usb_sc = device_private(device_parent(dev));
 	uint32_t reg, write_mask, write_val;
 	int error;
 	switch (usb_sc->sc_type) {
 	case USB_RK3328:
 		reg = RK3328_CON0_REG;
 		write_mask = 0x1ffU << 16;
 		write_val = enable ? 0 : 0x1d1;
 		break;
 	case USB_RK3399:
 		reg = RK3399_PHY_NO(usb_sc) == 0 ?
 		    RK3399_GRF_USB20_PHY0_CON1_REG :
 		    RK3399_GRF_USB20_PHY1_CON1_REG;
 		write_mask = (RK3399_USBPHY_SUSPEND_N|RK3399_USBPHY_UTMI_SEL) << 16;
 		write_val = enable ? 0 : RK3399_USBPHY_UTMI_SEL;
 		break;
 	default:
 		return ENXIO;
+	}
 	if (sc->sc_supply) {
 		error = enable ? fdtbus_regulator_enable(sc->sc_supply) :
 				 fdtbus_regulator_disable(sc->sc_supply);
 		if (error != 0)
 			return error;
+	}
 	syscon_lock(usb_sc->sc_syscon);
 	syscon_write_4(usb_sc->sc_syscon, reg, write_mask | write_val);
 	syscon_unlock(usb_sc->sc_syscon);
 	return 0;
+}
 static int
 rk_usbphy_host_enable(device_t dev, void *priv, bool enable)
+{
 	struct rk_usbphy_softc * const sc = device_private(dev);
 	struct rk_usb_softc * const usb_sc = device_private(device_parent(dev));
 	uint32_t reg, write_mask, write_val;
 	int error;
 	switch (usb_sc->sc_type) {
 	case USB_RK3328:
 		reg = RK3328_CON1_REG;
 		write_mask = 0x1ffU << 16;
 		write_val = enable ? 0 : 0x1d1;
 		break;
 	case USB_RK3399:
 		reg = RK3399_PHY_NO(usb_sc) == 0 ?
 		    RK3399_GRF_USB20_PHY0_CON2_REG :
 		    RK3399_GRF_USB20_PHY1_CON2_REG;
 		write_mask = (RK3399_USBPHY_SUSPEND_N|RK3399_USBPHY_UTMI_SEL) << 16;
 		write_val = enable ? 0 : RK3399_USBPHY_UTMI_SEL;
 		break;
 	default:
 		return ENXIO;
+	}
 	if (sc->sc_supply) {
 		error = enable ? fdtbus_regulator_enable(sc->sc_supply) :
 				 fdtbus_regulator_disable(sc->sc_supply);
 		if (error != 0)
 			return error;
+	}
 	syscon_lock(usb_sc->sc_syscon);
 	syscon_write_4(usb_sc->sc_syscon, reg, write_mask | write_val);
 	syscon_unlock(usb_sc->sc_syscon);
 	return 0;
+}
 const struct fdtbus_phy_controller_func rk_usbphy_otg_funcs = {
 	.acquire = rk_usbphy_acquire,
 	.release = rk_usbphy_release,
 	.enable = rk_usbphy_otg_enable,
 };
 const struct fdtbus_phy_controller_func rk_usbphy_host_funcs = {
 	.acquire = rk_usbphy_acquire,
 	.release = rk_usbphy_release,
 	.enable = rk_usbphy_host_enable,
 };
 static int
 rk_usbphy_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	const char *name = fdtbus_get_string(phandle, "name");
 	if (strcmp(name, "otg-port") == 0 || strcmp(name, "host-port") == 0)
 		return 1;
 	return 0;
+}
 static void
 rk_usbphy_attach(device_t parent, device_t self, void *aux)
+{
 	struct rk_usbphy_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	const char *name = fdtbus_get_string(phandle, "name");
 	sc->sc_dev = self;
 	sc->sc_phandle = phandle;
 	if (of_hasprop(phandle, "phy-supply")) {
 		sc->sc_supply = fdtbus_regulator_acquire(phandle, "phy-supply");
 		if (sc->sc_supply == NULL) {
 			aprint_error(": couldn't acquire regulator\n");
 			return;
+		}
+	}
 	aprint_naive("\n");
 	if (strcmp(name, "otg-port") == 0) {
 		aprint_normal(": USB2 OTG port\n");
 		fdtbus_register_phy_controller(self, phandle, &rk_usbphy_otg_funcs);
 	} else if (strcmp(name, "host-port") == 0) {
 		aprint_normal(": USB2 host port\n");
 		fdtbus_register_phy_controller(self, phandle, &rk_usbphy_host_funcs);
+	}
+}