 @@ -1,540 +1,540 @@
-/* $NetBSD: ti_gpio.c,v 1.8 2021/01/25 14:20:39 thorpej Exp $ */
+/* $NetBSD: ti_gpio.c,v 1.9 2021/01/27 02:12:16 thorpej Exp $ */
 /*-
  * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ti_gpio.c,v 1.8 2021/01/25 14:20:39 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ti_gpio.c,v 1.9 2021/01/27 02:12:16 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/mutex.h>
 #include <sys/kmem.h>
 #include <sys/gpio.h>
 #include <sys/bitops.h>
 #include <dev/fdt/fdtvar.h>
 #include <dev/gpio/gpiovar.h>
 #include <arm/ti/ti_prcm.h>
 #define	TI_GPIO_NPINS			32
 enum ti_gpio_type {
 	TI_GPIO_OMAP3,
 	TI_GPIO_OMAP4,
 	TI_NGPIO
 };
 enum {
 	GPIO_IRQSTATUS1,
 	GPIO_IRQENABLE1,	/* OMAP3 */
 	GPIO_IRQENABLE1_SET,	/* OMAP4 */
 	GPIO_IRQENABLE1_CLR,	/* OMAP4 */
 	GPIO_OE,
 	GPIO_DATAIN,
 	GPIO_DATAOUT,
 	GPIO_LEVELDETECT0,
 	GPIO_LEVELDETECT1,
 	GPIO_RISINGDETECT,
 	GPIO_FALLINGDETECT,
 	GPIO_CLEARDATAOUT,
 	GPIO_SETDATAOUT,
 	GPIO_NREG
 };
 static const u_int ti_gpio_regmap[TI_NGPIO][GPIO_NREG] = {
 	[TI_GPIO_OMAP3] = {
 		[GPIO_IRQSTATUS1]	= 0x18,
 		[GPIO_IRQENABLE1]	= 0x1c,
 		[GPIO_OE]		= 0x34,
 		[GPIO_DATAIN]		= 0x38,
 		[GPIO_DATAOUT]		= 0x3c,
 		[GPIO_LEVELDETECT0]	= 0x40,
 		[GPIO_LEVELDETECT1]	= 0x44,
 		[GPIO_RISINGDETECT]	= 0x48,
 		[GPIO_FALLINGDETECT]	= 0x4c,
 		[GPIO_CLEARDATAOUT]	= 0x90,
 		[GPIO_SETDATAOUT]	= 0x94,
 	},
 	[TI_GPIO_OMAP4] = {
 		[GPIO_IRQSTATUS1]	= 0x2c,
 		[GPIO_IRQENABLE1_SET]	= 0x34,
 		[GPIO_IRQENABLE1_CLR]	= 0x38,
 		[GPIO_OE]		= 0x134,
 		[GPIO_DATAIN]		= 0x138,
 		[GPIO_DATAOUT]		= 0x13c,
 		[GPIO_LEVELDETECT0]	= 0x140,
 		[GPIO_LEVELDETECT1]	= 0x144,
 		[GPIO_RISINGDETECT]	= 0x148,
 		[GPIO_FALLINGDETECT]	= 0x14c,
 		[GPIO_CLEARDATAOUT]	= 0x190,
 		[GPIO_SETDATAOUT]	= 0x194,
 	},
 };
 static const struct device_compatible_entry compat_data[] = {
 	{ .compat = "ti,omap3-gpio",	.value = TI_GPIO_OMAP3 },
 	{ .compat = "ti,omap4-gpio",	.value = TI_GPIO_OMAP4 },
-	{ }
+	DEVICE_COMPAT_EOL
 };
 struct ti_gpio_intr {
 	u_int intr_pin;
 	int (*intr_func)(void *);
 	void *intr_arg;
 	bool intr_mpsafe;
 };
 struct ti_gpio_softc {
 	device_t sc_dev;
 	bus_space_tag_t sc_bst;
 	bus_space_handle_t sc_bsh;
 	kmutex_t sc_lock;
 	enum ti_gpio_type sc_type;
 	const char *sc_modname;
 	void *sc_ih;
 	struct gpio_chipset_tag sc_gp;
 	gpio_pin_t sc_pins[TI_GPIO_NPINS];
 	bool sc_pinout[TI_GPIO_NPINS];
 	struct ti_gpio_intr sc_intr[TI_GPIO_NPINS];
 	device_t sc_gpiodev;
 };
 struct ti_gpio_pin {
 	struct ti_gpio_softc *pin_sc;
 	u_int pin_nr;
 	int pin_flags;
 	bool pin_actlo;
 };
 #define RD4(sc, reg) 		\
     bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, ti_gpio_regmap[(sc)->sc_type][(reg)])
 #define WR4(sc, reg, val) 	\
     bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, ti_gpio_regmap[(sc)->sc_type][(reg)], (val))
 static int	ti_gpio_match(device_t, cfdata_t, void *);
 static void	ti_gpio_attach(device_t, device_t, void *);
 CFATTACH_DECL_NEW(ti_gpio, sizeof(struct ti_gpio_softc),
 	ti_gpio_match, ti_gpio_attach, NULL, NULL);
 static int
 ti_gpio_ctl(struct ti_gpio_softc *sc, u_int pin, int flags)
+{
 	uint32_t oe;
 	KASSERT(mutex_owned(&sc->sc_lock));
 	oe = RD4(sc, GPIO_OE);
 	if (flags & GPIO_PIN_INPUT)
 		oe |= __BIT(pin);
 	else if (flags & GPIO_PIN_OUTPUT)
 		oe &= ~__BIT(pin);
 	WR4(sc, GPIO_OE, oe);
 	sc->sc_pinout[pin] = (flags & GPIO_PIN_OUTPUT) != 0;
 	return 0;
+}
 static void *
 ti_gpio_acquire(device_t dev, const void *data, size_t len, int flags)
+{
 	struct ti_gpio_softc * const sc = device_private(dev);
 	struct ti_gpio_pin *gpin;
 	const u_int *gpio = data;
 	int error;
 	if (len != 12)
 		return NULL;
 	const uint8_t pin = be32toh(gpio[1]) & 0xff;
 	const bool actlo = be32toh(gpio[2]) & 1;
 	if (pin >= __arraycount(sc->sc_pins))
 		return NULL;
 	mutex_enter(&sc->sc_lock);
 	error = ti_gpio_ctl(sc, pin, flags);
 	mutex_exit(&sc->sc_lock);
 	if (error != 0)
 		return NULL;
 	gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP);
 	gpin->pin_sc = sc;
 	gpin->pin_nr = pin;
 	gpin->pin_flags = flags;
 	gpin->pin_actlo = actlo;
 	return gpin;
+}
 static void
 ti_gpio_release(device_t dev, void *priv)
+{
 	struct ti_gpio_softc * const sc = device_private(dev);
 	struct ti_gpio_pin *pin = priv;
 	mutex_enter(&sc->sc_lock);
 	ti_gpio_ctl(pin->pin_sc, pin->pin_nr, GPIO_PIN_INPUT);
 	mutex_exit(&sc->sc_lock);
 	kmem_free(pin, sizeof(*pin));
+}
 static int
 ti_gpio_read(device_t dev, void *priv, bool raw)
+{
 	struct ti_gpio_softc * const sc = device_private(dev);
 	struct ti_gpio_pin *pin = priv;
 	uint32_t data;
 	int val;
 	KASSERT(sc == pin->pin_sc);
 	const uint32_t data_mask = __BIT(pin->pin_nr);
 	/* No lock required for reads */
 	if (sc->sc_pinout[pin->pin_nr])
 		data = RD4(sc, GPIO_DATAOUT);
 	else
 		data = RD4(sc, GPIO_DATAIN);
 	val = __SHIFTOUT(data, data_mask);
 	if (!raw && pin->pin_actlo)
 		val = !val;
 	return val;
+}
 static void
 ti_gpio_write(device_t dev, void *priv, int val, bool raw)
+{
 	struct ti_gpio_softc * const sc = device_private(dev);
 	struct ti_gpio_pin *pin = priv;
 	KASSERT(sc == pin->pin_sc);
 	const uint32_t data_mask = __BIT(pin->pin_nr);
 	if (!raw && pin->pin_actlo)
 		val = !val;
 	const u_int data_reg = val ? GPIO_SETDATAOUT : GPIO_CLEARDATAOUT;
 	WR4(sc, data_reg, data_mask);
+}
 static struct fdtbus_gpio_controller_func ti_gpio_funcs = {
 	.acquire = ti_gpio_acquire,
 	.release = ti_gpio_release,
 	.read = ti_gpio_read,
 	.write = ti_gpio_write,
 };
 static void
 ti_gpio_intr_disestablish(device_t dev, void *ih)
+{
 	struct ti_gpio_softc * const sc = device_private(dev);
 	struct ti_gpio_intr *intr = ih;
 	const u_int pin = intr->intr_pin;
 	const uint32_t pin_mask = __BIT(pin);
 	uint32_t val;
 	/* Disable interrupts */
 	if (sc->sc_type == TI_GPIO_OMAP3) {
 		val = RD4(sc, GPIO_IRQENABLE1);
 		WR4(sc, GPIO_IRQENABLE1, val & ~pin_mask);
 	} else {
 		WR4(sc, GPIO_IRQENABLE1_CLR, pin_mask);
+	}
 	intr->intr_func = NULL;
 	intr->intr_arg = NULL;
+}
 static void *
 ti_gpio_intr_establish(device_t dev, u_int *specifier, int ipl, int flags,
     int (*func)(void *), void *arg, const char *xname)
+{
 	struct ti_gpio_softc * const sc = device_private(dev);
 	uint32_t val;
 	/* 1st cell is the pin */
 	/* 2nd cell is flags */
 	const u_int pin = be32toh(specifier[0]);
 	const u_int type = be32toh(specifier[2]) & 0xf;
 	if (ipl != IPL_VM || pin >= __arraycount(sc->sc_pins))
 		return NULL;
 	/*
 	 * Enabling both high and low level triggers will cause the GPIO
 	 * controller to always assert the interrupt.
 	 */
 	if ((type & (FDT_INTR_TYPE_LOW_LEVEL|FDT_INTR_TYPE_HIGH_LEVEL)) ==
 	    (FDT_INTR_TYPE_LOW_LEVEL|FDT_INTR_TYPE_HIGH_LEVEL))
 		return NULL;
 	if (sc->sc_intr[pin].intr_func != NULL)
 		return NULL;
 	/* Set pin as input */
 	if (ti_gpio_ctl(sc, pin, GPIO_PIN_INPUT) != 0)
 		return NULL;
 	sc->sc_intr[pin].intr_pin = pin;
 	sc->sc_intr[pin].intr_func = func;
 	sc->sc_intr[pin].intr_arg = arg;
 	sc->sc_intr[pin].intr_mpsafe = (flags & FDT_INTR_MPSAFE) != 0;
 	const uint32_t pin_mask = __BIT(pin);
 	/* Configure triggers */
 	val = RD4(sc, GPIO_LEVELDETECT0);
 	if ((type & FDT_INTR_TYPE_LOW_LEVEL) != 0)
 		val |= pin_mask;
 	else
 		val &= ~pin_mask;
 	WR4(sc, GPIO_LEVELDETECT0, val);
 	val = RD4(sc, GPIO_LEVELDETECT1);
 	if ((type & FDT_INTR_TYPE_HIGH_LEVEL) != 0)
 		val |= pin_mask;
 	else
 		val &= ~pin_mask;
 	WR4(sc, GPIO_LEVELDETECT1, val);
 	val = RD4(sc, GPIO_RISINGDETECT);
 	if ((type & FDT_INTR_TYPE_POS_EDGE) != 0)
 		val |= pin_mask;
 	else
 		val &= ~pin_mask;
 	WR4(sc, GPIO_RISINGDETECT, val);
 	val = RD4(sc, GPIO_FALLINGDETECT);
 	if ((type & FDT_INTR_TYPE_NEG_EDGE) != 0)
 		val |= pin_mask;
 	else
 		val &= ~pin_mask;
 	WR4(sc, GPIO_FALLINGDETECT, val);
 	/* Enable interrupts */
 	if (sc->sc_type == TI_GPIO_OMAP3) {
 		val = RD4(sc, GPIO_IRQENABLE1);
 		WR4(sc, GPIO_IRQENABLE1, val | pin_mask);
 	} else {
 		WR4(sc, GPIO_IRQENABLE1_SET, pin_mask);
+	}
 	return &sc->sc_intr[pin];
+}
 static bool
 ti_gpio_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen)
+{
 	struct ti_gpio_softc * const sc = device_private(dev);
 	/* 1st cell is the pin */
 	/* 2nd cell is flags */
 	const u_int pin = be32toh(specifier[0]);
 	if (pin >= __arraycount(sc->sc_pins))
 		return false;
 	snprintf(buf, buflen, "%s pin %d", sc->sc_modname, pin);
 	return true;
+}
 static struct fdtbus_interrupt_controller_func ti_gpio_intrfuncs = {
 	.establish = ti_gpio_intr_establish,
 	.disestablish = ti_gpio_intr_disestablish,
 	.intrstr = ti_gpio_intrstr,
 };
 static int
 ti_gpio_pin_read(void *priv, int pin)
+{
 	struct ti_gpio_softc * const sc = priv;
 	uint32_t data;
 	int val;
 	KASSERT(pin < __arraycount(sc->sc_pins));
 	const uint32_t data_mask = __BIT(pin);
 	data = RD4(sc, GPIO_DATAIN);
 	val = __SHIFTOUT(data, data_mask);
 	return val;
+}
 static void
 ti_gpio_pin_write(void *priv, int pin, int val)
+{
 	struct ti_gpio_softc * const sc = priv;
 	KASSERT(pin < __arraycount(sc->sc_pins));
 	const u_int data_reg = val ? GPIO_SETDATAOUT : GPIO_CLEARDATAOUT;
 	const uint32_t data_mask = __BIT(pin);
 	WR4(sc, data_reg, data_mask);
+}
 static void
 ti_gpio_pin_ctl(void *priv, int pin, int flags)
+{
 	struct ti_gpio_softc * const sc = priv;
 	KASSERT(pin < __arraycount(sc->sc_pins));
 	mutex_enter(&sc->sc_lock);
 	ti_gpio_ctl(sc, pin, flags);
 	mutex_exit(&sc->sc_lock);
+}
 static void
 ti_gpio_attach_ports(struct ti_gpio_softc *sc)
+{
 	struct gpio_chipset_tag *gp = &sc->sc_gp;
 	struct gpiobus_attach_args gba;
 	u_int pin;
 	gp->gp_cookie = sc;
 	gp->gp_pin_read = ti_gpio_pin_read;
 	gp->gp_pin_write = ti_gpio_pin_write;
 	gp->gp_pin_ctl = ti_gpio_pin_ctl;
 	for (pin = 0; pin < __arraycount(sc->sc_pins); pin++) {
 		sc->sc_pins[pin].pin_num = pin;
 		sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
 		sc->sc_pins[pin].pin_state = ti_gpio_pin_read(sc, pin);
+	}
 	memset(&gba, 0, sizeof(gba));
 	gba.gba_gc = gp;
 	gba.gba_pins = sc->sc_pins;
 	gba.gba_npins = __arraycount(sc->sc_pins);
 	sc->sc_gpiodev = config_found_ia(sc->sc_dev, "gpiobus", &gba, NULL);
+}
 static int
 ti_gpio_intr(void *priv)
+{
 	struct ti_gpio_softc * const sc = priv;
 	uint32_t status;
 	u_int bit;
 	int rv = 0;
 	status = RD4(sc, GPIO_IRQSTATUS1);
 	WR4(sc, GPIO_IRQSTATUS1, status);
 	while ((bit = ffs32(status)) != 0) {
 		const u_int pin = bit - 1;
 		const uint32_t pin_mask = __BIT(pin);
 		struct ti_gpio_intr *intr = &sc->sc_intr[pin];
 		status &= ~pin_mask;
 		if (intr->intr_func == NULL)
 			continue;
 		if (!intr->intr_mpsafe)
 			KERNEL_LOCK(1, curlwp);
 		rv |= intr->intr_func(intr->intr_arg);
 		if (!intr->intr_mpsafe)
 			KERNEL_UNLOCK_ONE(curlwp);
+	}
 	return rv;
+}
 static int
 ti_gpio_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 static void
 ti_gpio_attach(device_t parent, device_t self, void *aux)
+{
 	struct ti_gpio_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	char intrstr[128];
 	bus_addr_t addr;
 	bus_size_t size;
 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error(": couldn't decode interrupt\n");
 		return;
+	}
 	if (ti_prcm_enable_hwmod(phandle, 0) != 0) {
 		aprint_error(": couldn't enable module\n");
 		return;
+	}
 	sc->sc_dev = self;
 	sc->sc_bst = faa->faa_bst;
 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
 		aprint_error(": couldn't map registers\n");
 		return;
+	}
 	sc->sc_type = of_search_compatible(phandle, compat_data)->value;
 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
 	sc->sc_modname = fdtbus_get_string(phandle, "ti,hwmods");
 	if (sc->sc_modname == NULL)
 		sc->sc_modname = fdtbus_get_string(OF_parent(phandle), "ti,hwmods");
 	if (sc->sc_modname == NULL)
 		sc->sc_modname = kmem_asprintf("gpio@%" PRIxBUSADDR, addr);
 	aprint_naive("\n");
 	aprint_normal(": GPIO (%s)\n", sc->sc_modname);
 	fdtbus_register_gpio_controller(self, phandle, &ti_gpio_funcs);
 	ti_gpio_attach_ports(sc);
 	sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM,
 	    FDT_INTR_MPSAFE, ti_gpio_intr, sc, device_xname(self));
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(self, "failed to establish interrupt on %s\n",
 		    intrstr);
 		return;
+	}
 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
 	fdtbus_register_interrupt_controller(self, phandle, &ti_gpio_intrfuncs);
+}

 @@ -1,687 +1,687 @@
-/*	$NetBSD: ti_sdhc.c,v 1.8 2021/01/25 14:20:39 thorpej Exp $	*/
+/*	$NetBSD: ti_sdhc.c,v 1.9 2021/01/27 02:12:16 thorpej Exp $	*/
 /*-
  * Copyright (c) 2011 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ti_sdhc.c,v 1.8 2021/01/25 14:20:39 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ti_sdhc.c,v 1.9 2021/01/27 02:12:16 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/errno.h>
 #include <sys/kernel.h>
 #include <sys/proc.h>
 #include <sys/queue.h>
 #include <sys/mutex.h>
 #include <sys/condvar.h>
 #include <sys/bus.h>
 #include <arm/ti/ti_prcm.h>
 #include <arm/ti/ti_edma.h>
 #include <arm/ti/ti_sdhcreg.h>
 #include <dev/sdmmc/sdhcreg.h>
 #include <dev/sdmmc/sdhcvar.h>
 #include <dev/sdmmc/sdmmcvar.h>
 #include <dev/fdt/fdtvar.h>
 #define EDMA_MAX_PARAMS		32
 #ifdef TISDHC_DEBUG
 int tisdhcdebug = 1;
 #define DPRINTF(n,s)    do { if ((n) <= tisdhcdebug) device_printf s; } while (0)
 #else
 #define DPRINTF(n,s)    do {} while (0)
 #endif
 #define CLKD(kz)	(sc->sc.sc_clkbase / (kz))
 #define SDHC_READ(sc, reg) \
 	bus_space_read_4((sc)->sc_bst, (sc)->sc_sdhc_bsh, (reg))
 #define SDHC_WRITE(sc, reg, val) \
 	bus_space_write_4((sc)->sc_bst, (sc)->sc_sdhc_bsh, (reg), (val))
 struct ti_sdhc_config {
 	bus_size_t		regoff;
 	uint32_t		flags;
 };
 static const struct ti_sdhc_config omap2_hsmmc_config = {
 };
 static const struct ti_sdhc_config omap3_pre_es3_hsmmc_config = {
 	.flags = SDHC_FLAG_SINGLE_ONLY
 };
 static const struct ti_sdhc_config omap4_hsmmc_config = {
 	.regoff = 0x100
 };
 static const struct device_compatible_entry compat_data[] = {
 	{ .compat = "ti,omap2-hsmmc",
 	  .data = &omap2_hsmmc_config },
 	{ .compat = "ti,omap3-hsmmc",
 	  .data = &omap2_hsmmc_config },
 	{ .compat = "ti,omap3-pre-es3-hsmmc",
 	  .data = &omap3_pre_es3_hsmmc_config },
 	{ .compat = "ti,omap4-hsmmc",
 	  .data = &omap4_hsmmc_config },
-	{ }
+	DEVICE_COMPAT_EOL
 };
 enum {
 	EDMA_CHAN_TX,
 	EDMA_CHAN_RX,
 	EDMA_NCHAN
 };
 struct ti_sdhc_softc {
 	struct sdhc_softc	sc;
 	int			sc_phandle;
 	bus_addr_t		sc_addr;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	bus_space_handle_t	sc_hl_bsh;
 	bus_space_handle_t	sc_sdhc_bsh;
 	struct sdhc_host	*sc_hosts[1];
 	void 			*sc_ih;		/* interrupt vectoring */
 	int			sc_edma_chan[EDMA_NCHAN];
 	struct edma_channel	*sc_edma_tx;
 	struct edma_channel	*sc_edma_rx;
 	uint16_t		sc_edma_param_tx[EDMA_MAX_PARAMS];
 	uint16_t		sc_edma_param_rx[EDMA_MAX_PARAMS];
 	kcondvar_t		sc_edma_cv;
 	bus_addr_t		sc_edma_fifo;
 	bool			sc_edma_pending;
 	bus_dmamap_t		sc_edma_dmamap;
 	bus_dma_segment_t	sc_edma_segs[1];
 	void			*sc_edma_bbuf;
 };
 static int ti_sdhc_match(device_t, cfdata_t, void *);
 static void ti_sdhc_attach(device_t, device_t, void *);
 static void ti_sdhc_init(struct ti_sdhc_softc *, const struct ti_sdhc_config *);
 static int ti_sdhc_bus_width(struct sdhc_softc *, int);
 static int ti_sdhc_rod(struct sdhc_softc *, int);
 static int ti_sdhc_write_protect(struct sdhc_softc *);
 static int ti_sdhc_card_detect(struct sdhc_softc *);
 static int ti_sdhc_edma_init(struct ti_sdhc_softc *, u_int, u_int);
 static int ti_sdhc_edma_xfer_data(struct sdhc_softc *, struct sdmmc_command *);
 static void ti_sdhc_edma_done(void *);
 static int ti_sdhc_edma_transfer(struct sdhc_softc *, struct sdmmc_command *);
 CFATTACH_DECL_NEW(ti_sdhc, sizeof(struct ti_sdhc_softc),
     ti_sdhc_match, ti_sdhc_attach, NULL, NULL);
 static int
 ti_sdhc_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 static void
 ti_sdhc_attach(device_t parent, device_t self, void *aux)
+{
 	struct ti_sdhc_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	const struct ti_sdhc_config *conf;
 	bus_addr_t addr;
 	bus_size_t size;
 	u_int bus_width;
 	conf = of_search_compatible(phandle, compat_data)->data;
 	if (ti_prcm_enable_hwmod(phandle, 0) != 0) {
 		aprint_error(": couldn't enable module\n");
 		return;
+	}
 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 || size <= conf->regoff) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	addr += conf->regoff;
 	size -= conf->regoff;
 	sc->sc.sc_dmat = faa->faa_dmat;
 	sc->sc.sc_dev = self;
 	sc->sc_phandle = phandle;
 	sc->sc_addr = addr;
 	sc->sc_bst = faa->faa_bst;
 	/* XXX use fdtbus_dma API */
 	int len;
 	const u_int *dmas = fdtbus_get_prop(phandle, "dmas", &len);
 	switch (len) {
 	case 24:
 		sc->sc_edma_chan[EDMA_CHAN_TX] = be32toh(dmas[1]);
 		sc->sc_edma_chan[EDMA_CHAN_RX] = be32toh(dmas[4]);
 		break;
 	case 32:
 		sc->sc_edma_chan[EDMA_CHAN_TX] = be32toh(dmas[1]);
 		sc->sc_edma_chan[EDMA_CHAN_RX] = be32toh(dmas[5]);
 		break;
 	default:
 		sc->sc_edma_chan[EDMA_CHAN_TX] = -1;
 		sc->sc_edma_chan[EDMA_CHAN_RX] = -1;
 		break;
+	}
 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
 		aprint_error(": couldn't map registers\n");
 		return;
+	}
 	if (of_getprop_uint32(phandle, "bus-width", &bus_width) != 0)
 		bus_width = 4;
 	sc->sc.sc_flags |= conf->flags;
 	sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS;
 	sc->sc.sc_flags |= SDHC_FLAG_NO_LED_ON;
 	sc->sc.sc_flags |= SDHC_FLAG_RSP136_CRC;
 	if (bus_width == 8)
 		sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE;
 	if (of_hasprop(phandle, "ti,needs-special-reset"))
 		sc->sc.sc_flags |= SDHC_FLAG_WAIT_RESET;
 	if (!of_hasprop(phandle, "ti,needs-special-hs-handling"))
 		sc->sc.sc_flags |= SDHC_FLAG_NO_HS_BIT;
 	if (of_hasprop(phandle, "ti,dual-volt"))
 		sc->sc.sc_caps = SDHC_VOLTAGE_SUPP_3_0V;
 	sc->sc.sc_host = sc->sc_hosts;
 	sc->sc.sc_clkbase = 96000;	/* 96MHZ */
 	sc->sc.sc_clkmsk = 0x0000ffc0;
 	sc->sc.sc_vendor_rod = ti_sdhc_rod;
 	sc->sc.sc_vendor_write_protect = ti_sdhc_write_protect;
 	sc->sc.sc_vendor_card_detect = ti_sdhc_card_detect;
 	sc->sc.sc_vendor_bus_width = ti_sdhc_bus_width;
 	if (bus_space_subregion(sc->sc_bst, sc->sc_bsh, 0x100, 0x100,
 	    &sc->sc_sdhc_bsh) != 0) {
 		aprint_error(": couldn't map subregion\n");
 		return;
+	}
 	aprint_naive("\n");
 	aprint_normal(": MMCHS\n");
 	ti_sdhc_init(sc, conf);
+}
 static void
 ti_sdhc_init(struct ti_sdhc_softc *sc, const struct ti_sdhc_config *conf)
+{
 	device_t dev = sc->sc.sc_dev;
 	uint32_t clkd, stat;
 	int error, timo, clksft, n;
 	char intrstr[128];
 	const int tx_chan = sc->sc_edma_chan[EDMA_CHAN_TX];
 	const int rx_chan = sc->sc_edma_chan[EDMA_CHAN_RX];
 	if (tx_chan != -1 && rx_chan != -1) {
 		aprint_normal_dev(dev,
 		    "EDMA tx channel %d, rx channel %d\n",
 		    tx_chan, rx_chan);
 		if (ti_sdhc_edma_init(sc, tx_chan, rx_chan) != 0) {
 			aprint_error_dev(dev, "EDMA disabled\n");
 			goto no_dma;
+		}
 		cv_init(&sc->sc_edma_cv, "sdhcedma");
 		sc->sc_edma_fifo = sc->sc_addr + 0x100 + SDHC_DATA;
 		sc->sc.sc_flags |= SDHC_FLAG_USE_DMA;
 		sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA;
 		sc->sc.sc_flags |= SDHC_FLAG_EXTDMA_DMAEN;
 		sc->sc.sc_vendor_transfer_data_dma = ti_sdhc_edma_xfer_data;
+	}
 no_dma:
 	/* XXXXXX: Turn-on regulator via I2C. */
 	/* XXXXXX: And enable ICLOCK/FCLOCK. */
 	SDHC_WRITE(sc, SDHC_CAPABILITIES,
 	    SDHC_READ(sc, SDHC_CAPABILITIES) | SDHC_VOLTAGE_SUPP_1_8V);
 	if (sc->sc.sc_caps & SDHC_VOLTAGE_SUPP_3_0V)
 		SDHC_WRITE(sc, SDHC_CAPABILITIES,
 		    SDHC_READ(sc, SDHC_CAPABILITIES) | SDHC_VOLTAGE_SUPP_3_0V);
 	/* MMCHS Soft reset */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG,
 	    SYSCONFIG_SOFTRESET);
 	timo = 3000000;	/* XXXX 3 sec. */
 	while (timo--) {
 		if (bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSSTATUS) &
 		    SYSSTATUS_RESETDONE)
 			break;
 		delay(1);
+	}
 	if (timo == 0)
 		aprint_error_dev(dev, "Soft reset timeout\n");
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG,
 	    SYSCONFIG_ENAWAKEUP |
 #if notyet
 	    SYSCONFIG_AUTOIDLE |
 	    SYSCONFIG_SIDLEMODE_AUTO |
 #else
 	    SYSCONFIG_SIDLEMODE_IGNORE |
 #endif
 	    SYSCONFIG_CLOCKACTIVITY_FCLK |
 	    SYSCONFIG_CLOCKACTIVITY_ICLK);
 	if (!fdtbus_intr_str(sc->sc_phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error_dev(dev, "couldn't decode interrupt\n");
 		return;
+	}
 	sc->sc_ih = fdtbus_intr_establish_xname(sc->sc_phandle, 0, IPL_VM,
 , sdhc_intr, &sc->sc, device_xname(dev));
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(dev, "couldn't establish interrupt\n");
 		return;
+	}
 	aprint_normal_dev(dev, "interrupting on %s\n", intrstr);
 	error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_sdhc_bsh, 0x100);
 	if (error != 0) {
 		aprint_error_dev(dev, "couldn't initialize host, error=%d\n",
 		    error);
 		fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih);
 		return;
+	}
 	clksft = ffs(sc->sc.sc_clkmsk) - 1;
 	/* Set SDVS 1.8v and DTW 1bit mode */
 	SDHC_WRITE(sc, SDHC_HOST_CTL,
 	    SDHC_VOLTAGE_1_8V << (SDHC_VOLTAGE_SHIFT + 8));
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_INTCLK_ENABLE |
 							SDHC_SDCLK_ENABLE);
 	SDHC_WRITE(sc, SDHC_HOST_CTL,
 	    SDHC_READ(sc, SDHC_HOST_CTL) | SDHC_BUS_POWER << 8);
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft);
 	/*
 	 * 22.6.1.3.1.5 MMCHS Controller INIT Procedure Start
 	 * from 'OMAP35x Applications Processor  Technical Reference Manual'.
+	 *
 	 * During the INIT procedure, the MMCHS controller generates 80 clock
 	 * periods. In order to keep the 1ms gap, the MMCHS controller should
 	 * be configured to generate a clock whose frequency is smaller or
 	 * equal to 80 KHz.
 	 */
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE);
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk);
 	clkd = CLKD(80);
 	n = 1;
 	while (clkd & ~(sc->sc.sc_clkmsk >> clksft)) {
 		clkd >>= 1;
 		n <<= 1;
+	}
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) | (clkd << clksft));
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | CON_INIT);
 	SDHC_WRITE(sc, SDHC_TRANSFER_MODE, 0x00000000);
 	delay(1000);
 	stat = SDHC_READ(sc, SDHC_NINTR_STATUS);
 	SDHC_WRITE(sc, SDHC_NINTR_STATUS, stat | SDHC_COMMAND_COMPLETE);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) & ~CON_INIT);
 	SDHC_WRITE(sc, SDHC_NINTR_STATUS, 0xffffffff);
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE);
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk);
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft);
 	timo = 3000000;	/* XXXX 3 sec. */
 	while (--timo) {
 		if (SDHC_READ(sc, SDHC_CLOCK_CTL) & SDHC_INTCLK_STABLE)
 			break;
 		delay(1);
+	}
 	if (timo == 0)
 		aprint_error_dev(dev, "ICS timeout\n");
 	SDHC_WRITE(sc, SDHC_CLOCK_CTL,
 	    SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE);
 	if (sc->sc.sc_flags & SDHC_FLAG_USE_ADMA2)
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
 		    bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) |
 		    CON_MNS);
+}
 static int
 ti_sdhc_rod(struct sdhc_softc *sc, int on)
+{
 	struct ti_sdhc_softc *hmsc = (struct ti_sdhc_softc *)sc;
 	uint32_t con;
 	con = bus_space_read_4(hmsc->sc_bst, hmsc->sc_bsh, MMCHS_CON);
 	if (on)
 		con |= CON_OD;
 	else
 		con &= ~CON_OD;
 	bus_space_write_4(hmsc->sc_bst, hmsc->sc_bsh, MMCHS_CON, con);
 	return 0;
+}
 static int
 ti_sdhc_write_protect(struct sdhc_softc *sc)
+{
 	/* Maybe board dependent, using GPIO. Get GPIO-pin from prop? */
 	return 0;	/* XXXXXXX */
+}
 static int
 ti_sdhc_card_detect(struct sdhc_softc *sc)
+{
 	/* Maybe board dependent, using GPIO. Get GPIO-pin from prop? */
 	return 1;	/* XXXXXXXX */
+}
 static int
 ti_sdhc_bus_width(struct sdhc_softc *sc, int width)
+{
 	struct ti_sdhc_softc *hmsc = (struct ti_sdhc_softc *)sc;
 	uint32_t con, hctl;
 	con = bus_space_read_4(hmsc->sc_bst, hmsc->sc_bsh, MMCHS_CON);
 	hctl = SDHC_READ(hmsc, SDHC_HOST_CTL);
 	if (width == 8) {
 		con |= CON_DW8;
 	} else if (width == 4) {
 		con &= ~CON_DW8;
 		hctl |= SDHC_4BIT_MODE;
 	} else {
 		con &= ~CON_DW8;
 		hctl &= ~SDHC_4BIT_MODE;
+	}
 	bus_space_write_4(hmsc->sc_bst, hmsc->sc_bsh, MMCHS_CON, con);
 	SDHC_WRITE(hmsc, SDHC_HOST_CTL, hctl);
 	return 0;
+}
 static int
 ti_sdhc_edma_init(struct ti_sdhc_softc *sc, u_int tx_chan, u_int rx_chan)
+{
 	int i, error, rseg;
 	/* Request tx and rx DMA channels */
 	sc->sc_edma_tx = edma_channel_alloc(EDMA_TYPE_DMA, tx_chan,
 	    ti_sdhc_edma_done, sc);
 	KASSERT(sc->sc_edma_tx != NULL);
 	sc->sc_edma_rx = edma_channel_alloc(EDMA_TYPE_DMA, rx_chan,
 	    ti_sdhc_edma_done, sc);
 	KASSERT(sc->sc_edma_rx != NULL);
 	/* Allocate some PaRAM pages */
 	for (i = 0; i < __arraycount(sc->sc_edma_param_tx); i++) {
 		sc->sc_edma_param_tx[i] = edma_param_alloc(sc->sc_edma_tx);
 		KASSERT(sc->sc_edma_param_tx[i] != 0xffff);
+	}
 	for (i = 0; i < __arraycount(sc->sc_edma_param_rx); i++) {
 		sc->sc_edma_param_rx[i] = edma_param_alloc(sc->sc_edma_rx);
 		KASSERT(sc->sc_edma_param_rx[i] != 0xffff);
+	}
 	/* Setup bounce buffer */
 	error = bus_dmamem_alloc(sc->sc.sc_dmat, MAXPHYS, 32, MAXPHYS,
 	    sc->sc_edma_segs, 1, &rseg, BUS_DMA_WAITOK);
 	if (error) {
 		aprint_error_dev(sc->sc.sc_dev,
 		    "couldn't allocate dmamem: %d\n", error);
 		return error;
+	}
 	KASSERT(rseg == 1);
 	error = bus_dmamem_map(sc->sc.sc_dmat, sc->sc_edma_segs, rseg, MAXPHYS,
 	    &sc->sc_edma_bbuf, BUS_DMA_WAITOK);
 	if (error) {
 		aprint_error_dev(sc->sc.sc_dev, "couldn't map dmamem: %d\n",
 		    error);
 		return error;
+	}
 	error = bus_dmamap_create(sc->sc.sc_dmat, MAXPHYS, 1, MAXPHYS, 0,
 	    BUS_DMA_WAITOK, &sc->sc_edma_dmamap);
 	if (error) {
 		aprint_error_dev(sc->sc.sc_dev, "couldn't create dmamap: %d\n",
 		    error);
 		return error;
+	}
 	error = bus_dmamap_load(sc->sc.sc_dmat, sc->sc_edma_dmamap,
 	    sc->sc_edma_bbuf, MAXPHYS, NULL, BUS_DMA_WAITOK);
 	if (error) {
 		device_printf(sc->sc.sc_dev, "couldn't load dmamap: %d\n",
 		    error);
 		return error;
+	}
 	return error;
+}
 static int
 ti_sdhc_edma_xfer_data(struct sdhc_softc *sdhc_sc, struct sdmmc_command *cmd)
+{
 	struct ti_sdhc_softc *sc = device_private(sdhc_sc->sc_dev);
 	const bus_dmamap_t map = cmd->c_dmamap;
 	bool bounce;
 	int error;
 #if notyet
 	bounce = false;
 	for (int seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) {
 		if ((cmd->c_dmamap->dm_segs[seg].ds_addr & 0x1f) != 0 ||
 		    (cmd->c_dmamap->dm_segs[seg].ds_len & 3) != 0) {
 			bounce = true;
 			break;
+		}
+	}
 #else
 	bounce = true;
 #endif
 	if (bounce) {
 		if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
 			bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_edma_dmamap, 0,
 			    MAXPHYS, BUS_DMASYNC_PREREAD);
 		} else {
 			memcpy(sc->sc_edma_bbuf, cmd->c_data, cmd->c_datalen);
 			bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_edma_dmamap, 0,
 			    MAXPHYS, BUS_DMASYNC_PREWRITE);
+		}
 		cmd->c_dmamap = sc->sc_edma_dmamap;
+	}
 	error = ti_sdhc_edma_transfer(sdhc_sc, cmd);
 	if (bounce) {
 		if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
 			bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_edma_dmamap, 0,
 			    MAXPHYS, BUS_DMASYNC_POSTREAD);
 		} else {
 			bus_dmamap_sync(sc->sc.sc_dmat, sc->sc_edma_dmamap, 0,
 			    MAXPHYS, BUS_DMASYNC_POSTWRITE);
+		}
 		if (ISSET(cmd->c_flags, SCF_CMD_READ) && error == 0) {
 			memcpy(cmd->c_data, sc->sc_edma_bbuf, cmd->c_datalen);
+		}
 		cmd->c_dmamap = map;
+	}
 	return error;
+}
 static int
 ti_sdhc_edma_transfer(struct sdhc_softc *sdhc_sc, struct sdmmc_command *cmd)
+{
 	struct ti_sdhc_softc *sc = device_private(sdhc_sc->sc_dev);
 	kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]);
 	struct edma_channel *edma;
 	uint16_t *edma_param;
 	struct edma_param ep;
 	size_t seg;
 	int error, resid = cmd->c_datalen;
 	int blksize = MIN(cmd->c_datalen, cmd->c_blklen);
 	KASSERT(mutex_owned(plock));
 	edma = ISSET(cmd->c_flags, SCF_CMD_READ) ?
 	    sc->sc_edma_rx : sc->sc_edma_tx;
 	edma_param = ISSET(cmd->c_flags, SCF_CMD_READ) ?
 	    sc->sc_edma_param_rx : sc->sc_edma_param_tx;
 	DPRINTF(1, (sc->sc.sc_dev, "edma xfer: nsegs=%d ch# %d\n",
 	    cmd->c_dmamap->dm_nsegs, edma_channel_index(edma)));
 	if (cmd->c_dmamap->dm_nsegs > EDMA_MAX_PARAMS) {
 		return ENOMEM;
+	}
 	for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) {
 		KASSERT(resid > 0);
 		const int xferlen = uimin(resid,
 		    cmd->c_dmamap->dm_segs[seg].ds_len);
 		KASSERT(xferlen == cmd->c_dmamap->dm_segs[seg].ds_len ||
 			seg == cmd->c_dmamap->dm_nsegs - 1);
 		resid -= xferlen;
 		KASSERT((xferlen & 0x3) == 0);
 		ep.ep_opt = __SHIFTIN(2, EDMA_PARAM_OPT_FWID) /* 32-bit */;
 		ep.ep_opt |= __SHIFTIN(edma_channel_index(edma),
 				       EDMA_PARAM_OPT_TCC);
 		if (seg == cmd->c_dmamap->dm_nsegs - 1) {
 			ep.ep_opt |= EDMA_PARAM_OPT_TCINTEN;
 			ep.ep_link = 0xffff;
 		} else {
 			ep.ep_link = EDMA_PARAM_BASE(edma_param[seg+1]);
+		}
 		if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
 			ep.ep_opt |= EDMA_PARAM_OPT_SAM;
 			ep.ep_src = sc->sc_edma_fifo;
 			ep.ep_dst = cmd->c_dmamap->dm_segs[seg].ds_addr;
 		} else {
 			ep.ep_opt |= EDMA_PARAM_OPT_DAM;
 			ep.ep_src = cmd->c_dmamap->dm_segs[seg].ds_addr;
 			ep.ep_dst = sc->sc_edma_fifo;
+		}
 		KASSERT(xferlen <= 65536 * 4);
 		/*
 		 * In constant addressing mode, the address must be aligned
 		 * to 256-bits.
 		 */
 		KASSERT((cmd->c_dmamap->dm_segs[seg].ds_addr & 0x1f) == 0);
 		/*
 		 * For unknown reason, the A-DMA transfers never completes for
 		 * transfers larger than 64 butes. So use a AB transfer,
 		 * with a 64 bytes A len
 		 */
 		ep.ep_bcntrld = 0;	/* not used for AB-synchronous mode */
 		ep.ep_opt |= EDMA_PARAM_OPT_SYNCDIM;
 		ep.ep_acnt = uimin(xferlen, 64);
 		ep.ep_bcnt = uimin(xferlen, blksize) / ep.ep_acnt;
 		ep.ep_ccnt = xferlen / (ep.ep_acnt * ep.ep_bcnt);
 		ep.ep_srcbidx = ep.ep_dstbidx = 0;
 		ep.ep_srccidx = ep.ep_dstcidx = 0;
 		if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
 			ep.ep_dstbidx = ep.ep_acnt;
 			ep.ep_dstcidx = ep.ep_acnt * ep.ep_bcnt;
 		} else {
 			ep.ep_srcbidx = ep.ep_acnt;
 			ep.ep_srccidx = ep.ep_acnt * ep.ep_bcnt;
+		}
 		edma_set_param(edma, edma_param[seg], &ep);
 #ifdef TISDHC_DEBUG
 		if (tisdhcdebug >= 1) {
 			printf("target OPT: %08x\n", ep.ep_opt);
 			edma_dump_param(edma, edma_param[seg]);
+		}
 #endif
+	}
 	error = 0;
 	sc->sc_edma_pending = true;
 	edma_transfer_enable(edma, edma_param[0]);
 	while (sc->sc_edma_pending) {
 		error = cv_timedwait(&sc->sc_edma_cv, plock, hz*10);
 		if (error == EWOULDBLOCK) {
 			device_printf(sc->sc.sc_dev, "transfer timeout!\n");
 			edma_dump(edma);
 			edma_dump_param(edma, edma_param[0]);
 			edma_halt(edma);
 			sc->sc_edma_pending = false;
 			error = ETIMEDOUT;
 			break;
+		}
+	}
 	edma_halt(edma);
 	return error;
+}
 static void
 ti_sdhc_edma_done(void *priv)
+{
 	struct ti_sdhc_softc *sc = priv;
 	kmutex_t *plock = sdhc_host_lock(sc->sc_hosts[0]);
 	mutex_enter(plock);
 	KASSERT(sc->sc_edma_pending == true);
 	sc->sc_edma_pending = false;
 	cv_broadcast(&sc->sc_edma_cv);
 	mutex_exit(plock);
+}

 @@ -1,701 +1,701 @@
-/* $NetBSD: ti_iic.c,v 1.11 2021/01/25 14:20:39 thorpej Exp $ */
+/* $NetBSD: ti_iic.c,v 1.12 2021/01/27 02:12:16 thorpej Exp $ */
 /*
  * Copyright (c) 2013 Manuel Bouyer.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /*-
  * Copyright (c) 2012 Jared D. McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ti_iic.c,v 1.11 2021/01/25 14:20:39 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ti_iic.c,v 1.12 2021/01/27 02:12:16 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/conf.h>
 #include <sys/bus.h>
 #include <sys/proc.h>
 #include <sys/kernel.h>
 #include <sys/mutex.h>
 #include <sys/condvar.h>
 #include <dev/i2c/i2cvar.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/ti/ti_prcm.h>
 #include <arm/ti/ti_iicreg.h>
 #ifndef OMAP2_I2C_SLAVE_ADDR
 #define OMAP2_I2C_SLAVE_ADDR	0x01
 #endif
 #define OMAP2_I2C_FIFOBYTES(fd)	(8 << (fd))
 #ifdef I2CDEBUG
 #define DPRINTF(args)	printf args
 #else
 #define DPRINTF(args)
 #endif
 enum ti_iic_type {
 	TI_IIC_OMAP3,
 	TI_IIC_OMAP4,
 	TI_NTYPES
 };
 enum {
 	I2C_SYSC,
 	I2C_IRQSTATUS_RAW,
 	I2C_IRQSTATUS,
 	I2C_IRQENABLE,		/* OMAP3 */
 	I2C_IRQENABLE_SET,	/* OMAP4 */
 	I2C_IRQENABLE_CLR,	/* OMAP4 */
 	I2C_SYSS,
 	I2C_BUF,
 	I2C_CNT,
 	I2C_DATA,
 	I2C_CON,
 	I2C_OA,
 	I2C_SA,
 	I2C_PSC,
 	I2C_SCLL,
 	I2C_SCLH,
 	I2C_BUFSTAT,
 	TI_NREGS
 };
 static const u_int ti_iic_regmap[TI_NTYPES][TI_NREGS] = {
 	[TI_IIC_OMAP3] = {
 		[I2C_SYSC] = 0x20,
 		[I2C_IRQSTATUS_RAW] = 0x08,
 		[I2C_IRQSTATUS] = 0x08,
 		[I2C_IRQENABLE] = 0x04,
 		[I2C_SYSS] = 0x10,
 		[I2C_BUF] = 0x14,
 		[I2C_CNT] = 0x18,
 		[I2C_DATA] = 0x1c,
 		[I2C_CON] = 0x24,
 		[I2C_OA] = 0x28,
 		[I2C_SA] = 0x2c,
 		[I2C_PSC] = 0x30,
 		[I2C_SCLL] = 0x34,
 		[I2C_SCLH] = 0x38,
 		[I2C_BUFSTAT] = 0x40,
 	},
 	[TI_IIC_OMAP4] = {
 		[I2C_SYSC] = 0x10,
 		[I2C_IRQSTATUS_RAW] = 0x24,
 		[I2C_IRQSTATUS] = 0x28,
 		[I2C_IRQENABLE_SET] = 0x2c,
 		[I2C_IRQENABLE_CLR] = 0x30,
 		[I2C_SYSS] = 0x90,
 		[I2C_BUF] = 0x94,
 		[I2C_CNT] = 0x98,
 		[I2C_DATA] = 0x9c,
 		[I2C_CON] = 0xa4,
 		[I2C_OA] = 0xa8,
 		[I2C_SA] = 0xac,
 		[I2C_PSC] = 0xb0,
 		[I2C_SCLL] = 0xb4,
 		[I2C_SCLH] = 0xb8,
 		[I2C_BUFSTAT] = 0xc0,
 	},
 };
 static const struct device_compatible_entry compat_data[] = {
 	/* compatible			type */
 	{ .compat = "ti,omap3-i2c",	.value = TI_IIC_OMAP3 },
 	{ .compat = "ti,omap4-i2c",	.value = TI_IIC_OMAP4 },
-	{ }
+	DEVICE_COMPAT_EOL
 };
 /* operation in progress */
 typedef enum {
 	TI_I2CREAD,
 	TI_I2CWRITE,
 	TI_I2CDONE,
 	TI_I2CERROR
 } ti_i2cop_t;
 struct ti_iic_softc {
 	device_t		sc_dev;
 	struct i2c_controller	sc_ic;
 	kmutex_t		sc_lock;
 	device_t		sc_i2cdev;
 	bus_space_tag_t		sc_iot;
 	bus_space_handle_t	sc_ioh;
 	enum ti_iic_type	sc_type;
 	void			*sc_ih;
 	kmutex_t		sc_mtx;
 	kcondvar_t		sc_cv;
 	ti_i2cop_t		sc_op;
 	int			sc_opflags;
 	int			sc_buflen;
 	int			sc_bufidx;
 	char			*sc_buf;
 	bool			sc_busy;
 	int			sc_rxthres;
 	int			sc_txthres;
 };
 #define I2C_READ_REG(sc, reg)		\
 	bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][(reg)])
 #define I2C_READ_DATA(sc)		\
 	bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][I2C_DATA])
 #define I2C_WRITE_REG(sc, reg, val)	\
 	bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][(reg)], (val))
 #define I2C_WRITE_DATA(sc, val)		\
 	bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][I2C_DATA], (val))
 static int	ti_iic_match(device_t, cfdata_t, void *);
 static void	ti_iic_attach(device_t, device_t, void *);
 static int	ti_iic_intr(void *);
 static int	ti_iic_acquire_bus(void *, int);
 static void	ti_iic_release_bus(void *, int);
 static int	ti_iic_exec(void *, i2c_op_t, i2c_addr_t, const void *,
 			       size_t, void *, size_t, int);
 static int	ti_iic_reset(struct ti_iic_softc *);
 static int	ti_iic_op(struct ti_iic_softc *, i2c_addr_t, ti_i2cop_t,
 			       uint8_t *, size_t, int);
 static void	ti_iic_handle_intr(struct ti_iic_softc *, uint32_t);
 static void	ti_iic_do_read(struct ti_iic_softc *, uint32_t);
 static void	ti_iic_do_write(struct ti_iic_softc *, uint32_t);
 static int	ti_iic_wait(struct ti_iic_softc *, uint16_t, uint16_t, int);
 static uint32_t	ti_iic_stat(struct ti_iic_softc *, uint32_t);
 static int	ti_iic_flush(struct ti_iic_softc *);
 CFATTACH_DECL_NEW(ti_iic, sizeof(struct ti_iic_softc),
     ti_iic_match, ti_iic_attach, NULL, NULL);
 static int
 ti_iic_match(device_t parent, cfdata_t match, void *opaque)
+{
 	struct fdt_attach_args * const faa = opaque;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 static void
 ti_iic_attach(device_t parent, device_t self, void *opaque)
+{
 	struct ti_iic_softc *sc = device_private(self);
 	struct fdt_attach_args * const faa = opaque;
 	const int phandle = faa->faa_phandle;
 	int fifodepth, fifo;
 	const char *modname;
 	char intrstr[128];
 	bus_addr_t addr;
 	bus_size_t size;
 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error(": couldn't decode interrupt\n");
 		return;
+	}
 	if (ti_prcm_enable_hwmod(phandle, 0) != 0) {
 		aprint_error(": couldn't enable module\n");
 		return;
+	}
 	sc->sc_dev = self;
 	sc->sc_iot = faa->faa_bst;
 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
 	mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET);
 	cv_init(&sc->sc_cv, "tiiic");
 	iic_tag_init(&sc->sc_ic);
 	sc->sc_ic.ic_cookie = sc;
 	sc->sc_ic.ic_acquire_bus = ti_iic_acquire_bus;
 	sc->sc_ic.ic_release_bus = ti_iic_release_bus;
 	sc->sc_ic.ic_exec = ti_iic_exec;
 	if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) {
 		aprint_error(": couldn't map registers\n");
 		return;
+	}
 	sc->sc_type = of_search_compatible(phandle, compat_data)->value;
 	sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_NET, 0,
 	    ti_iic_intr, sc, device_xname(self));
 	if (sc->sc_ih == NULL) {
 		aprint_error(": couldn't establish interrupt\n");
 		return;
+	}
 	modname = fdtbus_get_string(phandle, "ti,hwmods");
 	if (modname == NULL)
 		modname = fdtbus_get_string(OF_parent(phandle), "ti,hwmods");
 	fifodepth = I2C_BUFSTAT_FIFODEPTH(I2C_READ_REG(sc, I2C_BUFSTAT));
 	fifo = OMAP2_I2C_FIFOBYTES(fifodepth);
 	sc->sc_rxthres = sc->sc_txthres = fifo >> 1;
 	aprint_naive("\n");
 	if (modname != NULL)
 		aprint_normal(": I2C controller (%s), %d-bytes FIFO\n", modname, fifo);
 	else
 		aprint_normal(": I2C controller (i2c@%" PRIxBUSADDR "), %d-bytes FIFO\n",
 		    addr, fifo);
 	ti_iic_reset(sc);
 	ti_iic_flush(sc);
 	fdtbus_register_i2c_controller(&sc->sc_ic, phandle);
 	fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print);
+}
 static int
 ti_iic_intr(void *arg)
+{
 	struct ti_iic_softc *sc = arg;
 	uint32_t stat;
 	mutex_enter(&sc->sc_mtx);
 	DPRINTF(("ti_iic_intr opflags=%#x\n", sc->sc_opflags));
 	if ((sc->sc_opflags & I2C_F_POLL) == 0) {
 		stat = I2C_READ_REG(sc, I2C_IRQSTATUS);
 		DPRINTF(("ti_iic_intr pre handle sc->sc_op eq %#x\n", sc->sc_op));
 		ti_iic_handle_intr(sc, stat);
 		I2C_WRITE_REG(sc, I2C_IRQSTATUS, stat);
 		if (sc->sc_op == TI_I2CERROR || sc->sc_op == TI_I2CDONE) {
 			DPRINTF(("ti_iic_intr post handle sc->sc_op %#x\n", sc->sc_op));
 			cv_broadcast(&sc->sc_cv);
+		}
+	}
 	mutex_exit(&sc->sc_mtx);
 	DPRINTF(("ti_iic_intr status 0x%x\n", stat));
 	return 1;
+}
 static int
 ti_iic_acquire_bus(void *opaque, int flags)
+{
 	struct ti_iic_softc *sc = opaque;
 	mutex_enter(&sc->sc_lock);
 	while (sc->sc_busy)
 		cv_wait(&sc->sc_cv, &sc->sc_lock);
 	sc->sc_busy = true;
 	mutex_exit(&sc->sc_lock);
 	return 0;
+}
 static void
 ti_iic_release_bus(void *opaque, int flags)
+{
 	struct ti_iic_softc *sc = opaque;
 	mutex_enter(&sc->sc_lock);
 	sc->sc_busy = false;
 	cv_broadcast(&sc->sc_cv);
 	mutex_exit(&sc->sc_lock);
+}
 static int
 ti_iic_exec(void *opaque, i2c_op_t op, i2c_addr_t addr,
     const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
+{
 	struct ti_iic_softc *sc = opaque;
 	int err;
 	DPRINTF(("ti_iic_exec: op 0x%x cmdlen %zd len %zd flags 0x%x\n",
 	    op, cmdlen, len, flags));
 	if (cmdlen > 0) {
 		err = ti_iic_op(sc, addr, TI_I2CWRITE,
 		    __UNCONST(cmdbuf), cmdlen,
 		    (I2C_OP_READ_P(op) ? 0 : I2C_F_STOP) | flags);
 		if (err)
 			goto done;
+	}
 	if (I2C_OP_STOP_P(op))
 		flags |= I2C_F_STOP;
 	/*
 	 * I2C controller doesn't allow for zero-byte transfers.
 	 */
 	if (len == 0) {
 		err = EINVAL;
 		goto done;
+	}
 	if (I2C_OP_READ_P(op)) {
 		err = ti_iic_op(sc, addr, TI_I2CREAD, buf, len, flags);
 	} else {
 		err = ti_iic_op(sc, addr, TI_I2CWRITE, buf, len, flags);
+	}
 done:
 	if (err)
 		ti_iic_reset(sc);
 	ti_iic_flush(sc);
 	DPRINTF(("ti_iic_exec: done %d\n", err));
 	return err;
+}
 static int
 ti_iic_reset(struct ti_iic_softc *sc)
+{
 	uint32_t psc, scll, sclh;
 	int i;
 	DPRINTF(("ti_iic_reset\n"));
 	/* Disable */
 	I2C_WRITE_REG(sc, I2C_CON, 0);
 	/* Soft reset */
 	I2C_WRITE_REG(sc, I2C_SYSC, I2C_SYSC_SRST);
 	delay(1000);
 	/* enable so that we can check for reset complete */
 	I2C_WRITE_REG(sc, I2C_CON, I2C_CON_EN);
 	delay(1000);
 	for (i = 0; i < 1000; i++) { /* 1s delay for reset */
 		if (I2C_READ_REG(sc, I2C_SYSS) & I2C_SYSS_RDONE)
 			break;
+	}
 	/* Disable again */
 	I2C_WRITE_REG(sc, I2C_CON, 0);
 	delay(50000);
 	if (i >= 1000) {
 		aprint_error_dev(sc->sc_dev, ": couldn't reset module\n");
 		return 1;
+	}
 	/* XXX standard speed only */
 	if (sc->sc_type == TI_IIC_OMAP3) {
 		psc = (96000000 / 19200000) - 1;
 		scll = sclh = (19200000 / (2 * 100000)) - 6;
 	} else {
 		psc = 3;
 		scll = 53;
 		sclh = 55;
+	}
 	/* Clocks */
 	I2C_WRITE_REG(sc, I2C_PSC, psc);
 	I2C_WRITE_REG(sc, I2C_SCLL, scll);
 	I2C_WRITE_REG(sc, I2C_SCLH, sclh);
 	/* Own I2C address */
 	I2C_WRITE_REG(sc, I2C_OA, OMAP2_I2C_SLAVE_ADDR);
 	/* 5 bytes fifo */
 	I2C_WRITE_REG(sc, I2C_BUF,
 	    I2C_BUF_RXTRSH(sc->sc_rxthres) | I2C_BUF_TXTRSH(sc->sc_txthres));
 	/* Enable */
 	I2C_WRITE_REG(sc, I2C_CON, I2C_CON_EN);
 	return 0;
+}
 static int
 ti_iic_op(struct ti_iic_softc *sc, i2c_addr_t addr, ti_i2cop_t op,
     uint8_t *buf, size_t buflen, int flags)
+{
 	uint16_t con, stat, mask;
 	int err, retry;
 	KASSERT(op == TI_I2CREAD || op == TI_I2CWRITE);
 	DPRINTF(("ti_iic_op: addr %#x op %#x buf %p buflen %#x flags %#x\n",
 	    addr, op, buf, (unsigned int) buflen, flags));
 	mask = I2C_IRQSTATUS_ARDY | I2C_IRQSTATUS_NACK | I2C_IRQSTATUS_AL;
 	if (op == TI_I2CREAD) {
 		mask |= I2C_IRQSTATUS_RDR | I2C_IRQSTATUS_RRDY;
 	} else {
 		mask |= I2C_IRQSTATUS_XDR | I2C_IRQSTATUS_XRDY;
+	}
 	err = ti_iic_wait(sc, I2C_IRQSTATUS_BB, 0, flags);
 	if (err) {
 		DPRINTF(("ti_iic_op: wait error %d\n", err));
 		return err;
+	}
 	con = I2C_CON_EN;
 	con |= I2C_CON_MST;
 	con |= I2C_CON_STT;
 	if (flags & I2C_F_STOP)
 		con |= I2C_CON_STP;
 	if (addr & ~0x7f)
 		con |= I2C_CON_XSA;
 	if (op == TI_I2CWRITE)
 		con |= I2C_CON_TRX;
 	mutex_enter(&sc->sc_mtx);
 	sc->sc_op = op;
 	sc->sc_opflags = flags;
 	sc->sc_buf = buf;
 	sc->sc_buflen = buflen;
 	sc->sc_bufidx = 0;
 	I2C_WRITE_REG(sc, I2C_CON, I2C_CON_EN | I2C_CON_MST | I2C_CON_STP);
 	DPRINTF(("ti_iic_op: op %d con 0x%x ", op, con));
 	I2C_WRITE_REG(sc, I2C_CNT, buflen);
 	I2C_WRITE_REG(sc, I2C_SA, (addr & I2C_SA_MASK));
 	DPRINTF(("SA 0x%x len %d\n", I2C_READ_REG(sc, I2C_SA), I2C_READ_REG(sc, I2C_CNT)));
 	if ((flags & I2C_F_POLL) == 0 || sc->sc_type == TI_IIC_OMAP3) {
 		/* clear any pending interrupt */
 		I2C_WRITE_REG(sc, I2C_IRQSTATUS,
 		    I2C_READ_REG(sc, I2C_IRQSTATUS));
 		/* and enable */
 		if (sc->sc_type == TI_IIC_OMAP4) {
 			I2C_WRITE_REG(sc, I2C_IRQENABLE_SET, mask);
 		} else {
 			I2C_WRITE_REG(sc, I2C_IRQENABLE, mask);
+		}
+	}
 	/* start transfer */
 	I2C_WRITE_REG(sc, I2C_CON, con);
 	if ((flags & I2C_F_POLL) == 0) {
 		/* and wait for completion */
 		DPRINTF(("ti_iic_op waiting, op %#x\n", sc->sc_op));
 		while (sc->sc_op == op) {
 			if (cv_timedwait(&sc->sc_cv, &sc->sc_mtx,
 			    mstohz(5000)) == EWOULDBLOCK) {
 				/* timeout */
 				op = TI_I2CERROR;
+			}
+		}
 		DPRINTF(("ti_iic_op waiting done, op %#x\n", sc->sc_op));
 		/* disable interrupts */
 		if (sc->sc_type == TI_IIC_OMAP4) {
 			I2C_WRITE_REG(sc, I2C_IRQENABLE_CLR, 0xffff);
 		} else {
 			I2C_WRITE_REG(sc, I2C_IRQENABLE, 0);
+		}
 	} else {
 		/* poll for completion */
 		DPRINTF(("ti_iic_op polling, op %x\n", sc->sc_op));
 		while (sc->sc_op == op) {
 			stat = ti_iic_stat(sc, mask);
 			DPRINTF(("ti_iic_op stat 0x%x\n", stat));
 			if (stat == 0) {
 				/* timeout */
 				sc->sc_op = TI_I2CERROR;
 			} else {
 				ti_iic_handle_intr(sc, stat);
+			}
 			I2C_WRITE_REG(sc, I2C_IRQSTATUS, stat);
+		}
 		DPRINTF(("ti_iic_op polling done, op now %x\n", sc->sc_op));
+	}
 	mutex_exit(&sc->sc_mtx);
 	retry = 10000;
 	I2C_WRITE_REG(sc, I2C_CON, 0);
 	while (I2C_READ_REG(sc, I2C_CON) & I2C_CON_MST) {
 		delay(100);
 		if (--retry == 0)
 			break;
+	}
 	return (sc->sc_op == TI_I2CDONE) ? 0 : EIO;
+}
 static void
 ti_iic_handle_intr(struct ti_iic_softc *sc, uint32_t stat)
+{
 	KASSERT(mutex_owned(&sc->sc_mtx));
 	KASSERT(stat != 0);
 	DPRINTF(("ti_iic_handle_intr stat %#x\n", stat));
 	if (stat &
 	    (I2C_IRQSTATUS_NACK|I2C_IRQSTATUS_AL)) {
 		sc->sc_op = TI_I2CERROR;
 		return;
+	}
 	if (stat & I2C_IRQSTATUS_ARDY) {
 		sc->sc_op = TI_I2CDONE;
 		return;
+	}
 	if (sc->sc_op == TI_I2CREAD)
 		ti_iic_do_read(sc, stat);
 	else if (sc->sc_op == TI_I2CWRITE)
 		ti_iic_do_write(sc, stat);
 	else
 		return;
+}
 void
 ti_iic_do_read(struct ti_iic_softc *sc, uint32_t stat)
+{
 	int len = 0;
 	KASSERT(mutex_owned(&sc->sc_mtx));
 	DPRINTF(("ti_iic_do_read stat %#x\n", stat));
 	if (stat & I2C_IRQSTATUS_RDR) {
 		len = I2C_READ_REG(sc, I2C_BUFSTAT);
 		len = I2C_BUFSTAT_RXSTAT(len);
 		DPRINTF(("ti_iic_do_read receive drain len %d left %d\n",
 		    len, I2C_READ_REG(sc, I2C_CNT)));
 	} else if (stat & I2C_IRQSTATUS_RRDY) {
 		len = sc->sc_rxthres + 1;
 		DPRINTF(("ti_iic_do_read receive len %d left %d\n",
 		    len, I2C_READ_REG(sc, I2C_CNT)));
+	}
 	for (;
 	    sc->sc_bufidx < sc->sc_buflen && len > 0;
 	    sc->sc_bufidx++, len--) {
 		sc->sc_buf[sc->sc_bufidx] = I2C_READ_DATA(sc);
 		DPRINTF(("ti_iic_do_read got b[%d]=0x%x\n", sc->sc_bufidx,
 		    sc->sc_buf[sc->sc_bufidx]));
+	}
 	DPRINTF(("ti_iic_do_read done\n"));
+}
 void
 ti_iic_do_write(struct ti_iic_softc *sc, uint32_t stat)
+{
 	int len = 0;
 	DPRINTF(("ti_iic_do_write stat %#x\n", stat));
 	KASSERT(mutex_owned(&sc->sc_mtx));
 	if (stat & I2C_IRQSTATUS_XDR) {
 		len = I2C_READ_REG(sc, I2C_BUFSTAT);
 		len = I2C_BUFSTAT_TXSTAT(len);
 		DPRINTF(("ti_iic_do_write xmit drain len %d left %d\n",
 		    len, I2C_READ_REG(sc, I2C_CNT)));
 	} else if (stat & I2C_IRQSTATUS_XRDY) {
 		len = sc->sc_txthres + 1;
 		DPRINTF(("ti_iic_do_write xmit len %d left %d\n",
 		    len, I2C_READ_REG(sc, I2C_CNT)));
+	}
 	for (;
 	    sc->sc_bufidx < sc->sc_buflen && len > 0;
 	    sc->sc_bufidx++, len--) {
 		DPRINTF(("ti_iic_do_write send b[%d]=0x%x\n",
 		    sc->sc_bufidx, sc->sc_buf[sc->sc_bufidx]));
 		I2C_WRITE_DATA(sc, sc->sc_buf[sc->sc_bufidx]);
+	}
 	DPRINTF(("ti_iic_do_write done\n"));
+}
 static int
 ti_iic_wait(struct ti_iic_softc *sc, uint16_t mask, uint16_t val, int flags)
+{
 	int retry = 10;
 	uint16_t v;
 	DPRINTF(("ti_iic_wait mask %#x val %#x flags %#x\n", mask, val, flags));
 	while (((v = I2C_READ_REG(sc, I2C_IRQSTATUS_RAW)) & mask) != val) {
 		--retry;
 		if (retry == 0) {
 			aprint_error_dev(sc->sc_dev, ": wait timeout, "
 			    "mask = %#x val = %#x stat = %#x\n",
 			    mask, val, v);
 			return EBUSY;
+		}
 		if (flags & I2C_F_POLL) {
 			delay(50000);
 		} else {
 			kpause("tiiic", false, mstohz(50), NULL);
+		}
+	}
 	DPRINTF(("ti_iic_wait done retry %#x\n", retry));
 	return 0;
+}
 static uint32_t
 ti_iic_stat(struct ti_iic_softc *sc, uint32_t mask)
+{
 	uint32_t v;
 	int retry = 500;
 	DPRINTF(("ti_iic_wait mask %#x\n", mask));
 	while (--retry > 0) {
 		v = I2C_READ_REG(sc, I2C_IRQSTATUS_RAW) & mask;
 		if (v != 0)
 			break;
 		delay(100);
+	}
 	DPRINTF(("ti_iic_wait done retry %#x\n", retry));
 	return v;
+}
 static int
 ti_iic_flush(struct ti_iic_softc *sc)
+{
 	DPRINTF(("ti_iic_flush\n"));
 #if 0
 	int retry = 1000;
 	uint16_t v;
 	while ((v = I2C_READ_REG(sc, I2C_IRQSTATUS_RAW)) & I2C_IRQSTATUS_RRDY) {
 		if (--retry == 0) {
 			aprint_error_dev(sc->sc_dev,
 			    ": flush timeout, stat = %#x\n", v);
 			return EBUSY;
+		}
 		(void)I2C_READ_DATA(sc);
 		delay(1000);
+	}
 #endif
 	I2C_WRITE_REG(sc, I2C_CNT, 0);
 	return 0;
+}

 @@ -1,285 +1,285 @@
-/*	$NetBSD: ti_omapintc.c,v 1.6 2021/01/25 14:20:39 thorpej Exp $	*/
+/*	$NetBSD: ti_omapintc.c,v 1.7 2021/01/27 02:12:16 thorpej Exp $	*/
 /*
  * Define the SDP2430 specific information and then include the generic OMAP
  * interrupt header.
  */
 /*
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain this list of conditions
  *    and the following disclaimer.
  * 2. Redistributions in binary form must reproduce this list of conditions
  *    and the following disclaimer in the documentation and/or other materials
  *    provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ANY
  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #define _INTR_PRIVATE
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ti_omapintc.c,v 1.6 2021/01/25 14:20:39 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ti_omapintc.c,v 1.7 2021/01/27 02:12:16 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/evcnt.h>
 #include <sys/device.h>
 #include <sys/kmem.h>
 #include <uvm/uvm_extern.h>
 #include <machine/intr.h>
 #include <sys/bus.h>
 #include <arm/cpu.h>
 #include <arm/armreg.h>
 #include <arm/cpufunc.h>
 #include <dev/fdt/fdtvar.h>
 #define INTC_CONTROL		0x048
 #define INTC_CONTROL_NEWIRQAGR	__BIT(0)
 #define INTC_ITR		0x080
 #define INTC_MIR		0x084
 #define INTC_MIR_CLEAR		0x088
 #define INTC_MIR_SET		0x08c
 #define INTC_PENDING_IRQ	0x098
 #define INTC_MAX_SOURCES	128
 static const struct device_compatible_entry compat_data[] = {
 	/* compatible			number of banks */
 	{ .compat = "ti,omap3-intc",	.value = 3 },
 	{ .compat = "ti,am33xx-intc",	.value = 4 },
-	{ }
+	DEVICE_COMPAT_EOL
 };
 #define	INTC_READ(sc, g, o)		\
 	bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (g) * 0x20 + (o))
 #define	INTC_WRITE(sc, g, o, v)	\
 	bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (g) * 0x20 + (o), v)
 static int omap2icu_match(device_t, cfdata_t, void *);
 static void omap2icu_attach(device_t, device_t, void *);
 static void omap2icu_unblock_irqs(struct pic_softc *, size_t, uint32_t);
 static void omap2icu_block_irqs(struct pic_softc *, size_t, uint32_t);
 static void omap2icu_establish_irq(struct pic_softc *, struct intrsource *);
 static void omap2icu_set_priority(struct pic_softc *, int);
 #if 0
 static void omap2icu_source_name(struct pic_softc *, int, char *, size_t);
 #endif
 static const struct pic_ops omap2icu_picops = {
 	.pic_unblock_irqs = omap2icu_unblock_irqs,
 	.pic_block_irqs = omap2icu_block_irqs,
 	.pic_establish_irq = omap2icu_establish_irq,
 	.pic_set_priority = omap2icu_set_priority,
 #if 0
 	.pic_source_name = omap2icu_source_name,
 #endif
 };
 #define	PICTOSOFTC(pic)	\
 	((struct omap2icu_softc *)((uintptr_t)(pic) - offsetof(struct omap2icu_softc, sc_pic)))
 struct omap2icu_softc {
 	device_t sc_dev;
 	bus_space_tag_t sc_memt;
 	bus_space_handle_t sc_memh;
 	struct pic_softc sc_pic;
 	uint32_t *sc_enabled_irqs;
 	u_int sc_nbank;
 };
 static struct omap2icu_softc *intc_softc;
 static void
 omap2icu_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
+{
 	struct omap2icu_softc * const sc = PICTOSOFTC(pic);
 	const size_t group = irqbase / 32;
 	KASSERT((irq_mask & sc->sc_enabled_irqs[group]) == 0);
 	sc->sc_enabled_irqs[group] |= irq_mask;
 	INTC_WRITE(sc, group, INTC_MIR_CLEAR, irq_mask);
 	/* Force INTC to recompute IRQ availability */
 	INTC_WRITE(sc, 0, INTC_CONTROL, INTC_CONTROL_NEWIRQAGR);
+}
 static void
 omap2icu_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
+{
 	struct omap2icu_softc * const sc = PICTOSOFTC(pic);
 	const size_t group = irqbase / 32;
 	INTC_WRITE(sc, group, INTC_MIR_SET, irq_mask);
 	sc->sc_enabled_irqs[group] &= ~irq_mask;
+}
 /*
  * Called with interrupts disabled
  */
 static int
 find_pending_irqs(struct omap2icu_softc *sc, size_t group)
+{
 	uint32_t pending = INTC_READ(sc, group, INTC_PENDING_IRQ);
 	KASSERT((sc->sc_enabled_irqs[group] & pending) == pending);
 	if (pending == 0)
 		return 0;
 	return pic_mark_pending_sources(&sc->sc_pic, group * 32, pending);
+}
 static void
 omap_irq_handler(void *frame)
+{
 	struct cpu_info * const ci = curcpu();
 	struct omap2icu_softc * const sc = intc_softc;
 	const int oldipl = ci->ci_cpl;
 	const uint32_t oldipl_mask = __BIT(oldipl);
 	int ipl_mask = 0, n;
 	ci->ci_data.cpu_nintr++;
 	for (n = 0; n < sc->sc_nbank; n++) {
 		if (sc->sc_enabled_irqs[n])
 			ipl_mask |= find_pending_irqs(sc, n);
+	}
 	/* force INTC to recompute IRQ */
 	INTC_WRITE(sc, 0, INTC_CONTROL, INTC_CONTROL_NEWIRQAGR);
 	/*
 	 * Record the pending_ipls and deliver them if we can.
 	 */
 	if ((ipl_mask & ~oldipl_mask) > oldipl_mask)
 		pic_do_pending_ints(I32_bit, oldipl, frame);
+}
 void
 omap2icu_establish_irq(struct pic_softc *pic, struct intrsource *is)
+{
 	KASSERT(is->is_irq < PICTOSOFTC(pic)->sc_pic.pic_maxsources);
 	KASSERT(is->is_type == IST_LEVEL);
+}
 static void
 omap2icu_set_priority(struct pic_softc *pic, int ipl)
+{
 	curcpu()->ci_cpl = ipl;
+}
 static void *
 omapintc_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags,
     int (*func)(void *), void *arg, const char *xname)
+{
 	const u_int irq = be32toh(specifier[0]);
 	if (irq >= INTC_MAX_SOURCES) {
 		device_printf(dev, "IRQ %u is invalid\n", irq);
 		return NULL;
+	}
 	const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0;
 	return intr_establish_xname(irq, ipl, IST_LEVEL | mpsafe, func, arg,
 	    xname);
+}
 static void
 omapintc_fdt_disestablish(device_t dev, void *ih)
+{
         intr_disestablish(ih);
+}
 static bool
 omapintc_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen)
+{
 	if (!specifier)
 		return false;
 	const u_int irq = be32toh(specifier[0]);
 	snprintf(buf, buflen, "INTC irq %d", irq);
 	return true;
+}
 static const struct fdtbus_interrupt_controller_func omapintc_fdt_funcs = {
 	.establish = omapintc_fdt_establish,
 	.disestablish = omapintc_fdt_disestablish,
 	.intrstr = omapintc_fdt_intrstr,
 };
 int
 omap2icu_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 void
 omap2icu_attach(device_t parent, device_t self, void *aux)
+{
 	struct omap2icu_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	bus_addr_t addr;
 	bus_size_t size;
 	int error, n;
 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	sc->sc_dev = self;
 	sc->sc_memt = faa->faa_bst;
 	if (bus_space_map(sc->sc_memt, addr, size, 0, &sc->sc_memh) != 0) {
 		aprint_error(": couldn't map registers\n");
 		return;
+	}
 	sc->sc_nbank = of_search_compatible(phandle, compat_data)->value;
 	sc->sc_enabled_irqs =
 	    kmem_zalloc(sizeof(*sc->sc_enabled_irqs) * sc->sc_nbank, KM_SLEEP);
 	aprint_naive("\n");
 	aprint_normal("\n");
 	for (n = 0; n < sc->sc_nbank; n++)
 		INTC_WRITE(sc, n, INTC_MIR_SET, 0xffffffff);
 	sc->sc_dev = self;
 	self->dv_private = sc;
 	sc->sc_pic.pic_ops = &omap2icu_picops;
 	sc->sc_pic.pic_maxsources = sc->sc_nbank * 32;
 	snprintf(sc->sc_pic.pic_name, sizeof(sc->sc_pic.pic_name), "intc");
 	pic_add(&sc->sc_pic, 0);
 	error = fdtbus_register_interrupt_controller(self, phandle,
 		&omapintc_fdt_funcs);
 	if (error) {
 		aprint_error_dev(self, "couldn't register with fdtbus: %d\n",
 		    error);
 		return;
+	}
 	KASSERT(intc_softc == NULL);
 	intc_softc = sc;
 	arm_fdt_irq_set_handler(omap_irq_handler);
+}
 CFATTACH_DECL_NEW(omapintc,
     sizeof(struct omap2icu_softc),
     omap2icu_match, omap2icu_attach,
     NULL, NULL);

 @@ -1,215 +1,215 @@
-/*	$NetBSD: ti_omaptimer.c,v 1.7 2021/01/25 14:20:39 thorpej Exp $	*/
+/*	$NetBSD: ti_omaptimer.c,v 1.8 2021/01/27 02:12:16 thorpej Exp $	*/
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ti_omaptimer.c,v 1.7 2021/01/25 14:20:39 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ti_omaptimer.c,v 1.8 2021/01/27 02:12:16 thorpej Exp $");
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/timetc.h>
 #include <sys/kernel.h>
 #include <arm/locore.h>
 #include <arm/fdt/arm_fdtvar.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/ti/ti_prcm.h>
 enum omaptimer_type {
 	DM_TIMER_AM335X,
 	DM_TIMER_OMAP3430,
 	_DM_NTIMER
 };
 enum {
 	TIMER_TISR,
 	TIMER_TIER,
 	TIMER_TCLR,
 	TIMER_TCRR,
 	TIMER_TLDR,
 	_TIMER_NREG
 };
 /* TISR bits */
 #define	 OVF_IT_FLAG		__BIT(1)
 /* TIER bits */
 #define	 MAT_EN_FLAG		__BIT(0)
 #define	 OVF_EN_FLAG		__BIT(1)
 #define	 TCAR_EN_FLAG		__BIT(2)
 /* TCLR bits */
 #define	 TCLR_ST		__BIT(0)
 #define	 TCLR_AR		__BIT(1)
 static uint8_t omaptimer_regmap[_DM_NTIMER][_TIMER_NREG] = {
 	[DM_TIMER_AM335X] = {
 		[TIMER_TISR]	= 0x28,
 		[TIMER_TIER]	= 0x2c,
 		[TIMER_TCLR] 	= 0x38,
 		[TIMER_TCRR]	= 0x3c,
 		[TIMER_TLDR]	= 0x40,
 	},
 	[DM_TIMER_OMAP3430] = {
 		[TIMER_TISR]	= 0x18,
 		[TIMER_TIER]	= 0x1c,
 		[TIMER_TCLR] 	= 0x24,
 		[TIMER_TCRR]	= 0x28,
 		[TIMER_TLDR]	= 0x2c,
 	},
 };
 static const struct device_compatible_entry compat_data[] = {
 	{ .compat = "ti,am335x-timer-1ms",	.value = DM_TIMER_AM335X },
 	{ .compat = "ti,am335x-timer",		.value = DM_TIMER_AM335X },
 	{ .compat = "ti,omap3430-timer",	.value = DM_TIMER_OMAP3430 },
-	{ }
+	DEVICE_COMPAT_EOL
 };
 struct omaptimer_softc {
 	device_t sc_dev;
 	bus_space_tag_t sc_bst;
 	bus_space_handle_t sc_bsh;
 	int sc_phandle;
 	enum omaptimer_type sc_type;
 	struct timecounter sc_tc;
 };
 #define	RD4(sc, reg)			\
 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, omaptimer_regmap[(sc)->sc_type][(reg)])
 #define	WR4(sc, reg, val)		\
 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, omaptimer_regmap[(sc)->sc_type][(reg)], val)
 static struct omaptimer_softc *timer_softc;
 static int
 omaptimer_intr(void *arg)
+{
 	struct omaptimer_softc * const sc = timer_softc;
 	struct clockframe * const frame = arg;
 	WR4(sc, TIMER_TISR, OVF_IT_FLAG);
 	hardclock(frame);
 	return 1;
+}
 static void
 omaptimer_cpu_initclocks(void)
+{
 	struct omaptimer_softc * const sc = timer_softc;
 	char intrstr[128];
 	void *ih;
 	KASSERT(sc != NULL);
 	if (!fdtbus_intr_str(sc->sc_phandle, 0, intrstr, sizeof(intrstr)))
 		panic("%s: failed to decode interrupt", __func__);
 	ih = fdtbus_intr_establish_xname(sc->sc_phandle, 0, IPL_CLOCK,
 	    FDT_INTR_MPSAFE, omaptimer_intr, NULL, device_xname(sc->sc_dev));
 	if (ih == NULL)
 		panic("%s: failed to establish timer interrupt", __func__);
 	aprint_normal_dev(sc->sc_dev, "interrupting on %s\n", intrstr);
 	/* Enable interrupts */
 	WR4(sc, TIMER_TIER, OVF_EN_FLAG);
+}
 static u_int
 omaptimer_get_timecount(struct timecounter *tc)
+{
 	struct omaptimer_softc * const sc = tc->tc_priv;
 	return RD4(sc, TIMER_TCRR);
+}
 static void
 omaptimer_enable(struct omaptimer_softc *sc, uint32_t value)
+{
 	/* Configure the timer */
 	WR4(sc, TIMER_TLDR, value);
 	WR4(sc, TIMER_TCRR, value);
 	WR4(sc, TIMER_TIER, 0);
 	WR4(sc, TIMER_TCLR, TCLR_ST | TCLR_AR);
+}
 static int
 omaptimer_match(device_t parent, cfdata_t match, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compat_data(faa->faa_phandle, compat_data);
+}
 static void
 omaptimer_attach(device_t parent, device_t self, void *aux)
+{
 	struct omaptimer_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	struct timecounter *tc = &sc->sc_tc;
 	const char *modname;
 	struct clk *hwmod;
 	bus_addr_t addr;
 	bus_size_t size;
 	u_int rate;
 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	sc->sc_dev = self;
 	sc->sc_phandle = phandle;
 	sc->sc_bst = faa->faa_bst;
 	sc->sc_type = of_search_compatible(phandle, compat_data)->value;
 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
 		device_printf(self, "unable to map bus space");
 		return;
+	}
 	hwmod = ti_prcm_get_hwmod(phandle, 0);
 	if (hwmod == NULL || clk_enable(hwmod) != 0) {
 		aprint_error(": couldn't enable module\n");
 		return;
+	}
 	modname = fdtbus_get_string(phandle, "ti,hwmods");
 	if (modname == NULL)
 		modname = fdtbus_get_string(OF_parent(phandle), "ti,hwmods");
 	aprint_naive("\n");
 	aprint_normal(": Timer (%s)\n", modname);
 	rate = clk_get_rate(hwmod);
 	if (strcmp(modname, "timer2") == 0) {
 		omaptimer_enable(sc, 0);
 		/* Install timecounter */
 		tc->tc_get_timecount = omaptimer_get_timecount;
 		tc->tc_counter_mask = ~0u;
 		tc->tc_frequency = rate;
 		tc->tc_name = modname;
 		tc->tc_quality = 200;
 		tc->tc_priv = sc;
 		tc_init(tc);
 	} else if (strcmp(modname, "timer3") == 0) {
 		const uint32_t value = (0xffffffff - ((rate / hz) - 1));
 		omaptimer_enable(sc, value);
 		/* Use this as the OS timer in UP configurations */
 		if (!arm_has_mpext_p) {
 			timer_softc = sc;
 			arm_fdt_timer_register(omaptimer_cpu_initclocks);
+		}
+	}
+}
 CFATTACH_DECL_NEW(omaptimer, sizeof(struct omaptimer_softc),
     omaptimer_match, omaptimer_attach, NULL, NULL);