 @@ -1,1085 +1,1129 @@
-/*	$NetBSD: pci_subr.c,v 1.224 2020/05/30 10:43:46 jdolecek Exp $	*/
+/*	$NetBSD: pci_subr.c,v 1.225 2021/01/27 05:00:15 thorpej Exp $	*/
 /*
  * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
  * Copyright (c) 1995, 1996, 1998, 2000
  *	Christopher G. Demetriou.  All rights reserved.
  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Charles M. Hannum.
  * 4. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * PCI autoconfiguration support functions.
+ *
  * Note: This file is also built into a userland library (libpci).
  * Pay attention to this when you make modifications.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.224 2020/05/30 10:43:46 jdolecek Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.225 2021/01/27 05:00:15 thorpej Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_pci.h"
 #endif
 #include <sys/param.h>
 #ifdef _KERNEL
 #include <sys/systm.h>
 #include <sys/intr.h>
 #include <sys/module.h>
 #include <sys/kmem.h>
 #define MALLOC(sz)	kmem_alloc(sz, KM_SLEEP)
 #define FREE(p, sz)	kmem_free(p, sz)
 #else
 #include <pci.h>
 #include <stdarg.h>
 #include <stdbool.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
 #define MALLOC(sz)	malloc(sz)
 #define FREE(p, sz)	free(p)
 #endif
 #include <dev/pci/pcireg.h>
 #ifdef _KERNEL
 #include <dev/pci/pcivar.h>
 #else
 #include <dev/pci/pci_verbose.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/pcidevs_data.h>
 #endif
 static int pci_conf_find_cap(const pcireg_t *, unsigned int, int *);
 static int pci_conf_find_extcap(const pcireg_t *, unsigned int, int *);
 static void pci_conf_print_pcie_power(uint8_t, unsigned int);
 #define PCIREG_SHIFTOUT(a, b) ((pcireg_t)__SHIFTOUT((a), (b)))
 #ifdef _KERNEL
 /*
  * Common routines used to match a compatible device by its PCI ID code.
  */
 const struct device_compatible_entry *
 pci_compatible_lookup_id(pcireg_t const id,
     const struct device_compatible_entry *dce)
+{
 	return device_compatible_lookup_id(id, PCI_COMPAT_EOL_VALUE, dce);
+}
 const struct device_compatible_entry *
 pci_compatible_lookup(const struct pci_attach_args * const pa,
     const struct device_compatible_entry * const dce)
+{
 	return pci_compatible_lookup_id(pa->pa_id, dce);
+}
 const struct device_compatible_entry *
 pci_compatible_lookup_subsys(const struct pci_attach_args * const pa,
     const struct device_compatible_entry * const dce)
+{
 	const pcireg_t subsysid =
 	    pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
 	return pci_compatible_lookup_id(subsysid, dce);
+}
 int
 pci_compatible_match(const struct pci_attach_args * const pa,
     const struct device_compatible_entry * const dce)
+{
 	return pci_compatible_lookup(pa, dce) != NULL;
+}
 int
 pci_compatible_match_subsys(const struct pci_attach_args * const pa,
     const struct device_compatible_entry * const dce)
+{
 	return pci_compatible_lookup_subsys(pa, dce) != NULL;
+}
 #endif /* _KERNEL */
 /*
  * Descriptions of known PCI classes and subclasses.
+ *
  * Subclasses are described in the same way as classes, but have a
  * NULL subclass pointer.
  */
 struct pci_class {
 	const char	*name;
 	u_int		val;		/* as wide as pci_{,sub}class_t */
 	const struct pci_class *subclasses;
 };
 /*
  * Class 0x00.
  * Before rev. 2.0.
  */
 static const struct pci_class pci_subclass_prehistoric[] = {
 	{ "miscellaneous",	PCI_SUBCLASS_PREHISTORIC_MISC,	NULL,	},
 	{ "VGA",		PCI_SUBCLASS_PREHISTORIC_VGA,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x01.
  * Mass storage controller
  */
 /* ATA programming interface */
 static const struct pci_class pci_interface_ata[] = {
 	{ "with single DMA",	PCI_INTERFACE_ATA_SINGLEDMA,	NULL,	},
 	{ "with chained DMA",	PCI_INTERFACE_ATA_CHAINEDDMA,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /* SATA programming interface */
 static const struct pci_class pci_interface_sata[] = {
 	{ "vendor specific",	PCI_INTERFACE_SATA_VND,		NULL,	},
 	{ "AHCI 1.0",		PCI_INTERFACE_SATA_AHCI10,	NULL,	},
 	{ "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, },
 	{ NULL,			0,				NULL,	},
 };
 /* Flash programming interface */
 static const struct pci_class pci_interface_nvm[] = {
 	{ "vendor specific",	PCI_INTERFACE_NVM_VND,		NULL,	},
 	{ "NVMHCI 1.0",		PCI_INTERFACE_NVM_NVMHCI10,	NULL,	},
 	{ "NVMe",		PCI_INTERFACE_NVM_NVME,		NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /* Subclasses */
 static const struct pci_class pci_subclass_mass_storage[] = {
 	{ "SCSI",		PCI_SUBCLASS_MASS_STORAGE_SCSI,	NULL,	},
 	{ "IDE",		PCI_SUBCLASS_MASS_STORAGE_IDE,	NULL,	},
 	{ "floppy",		PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, },
 	{ "IPI",		PCI_SUBCLASS_MASS_STORAGE_IPI,	NULL,	},
 	{ "RAID",		PCI_SUBCLASS_MASS_STORAGE_RAID,	NULL,	},
 	{ "ATA",		PCI_SUBCLASS_MASS_STORAGE_ATA,
 	  pci_interface_ata, },
 	{ "SATA",		PCI_SUBCLASS_MASS_STORAGE_SATA,
 	  pci_interface_sata, },
 	{ "SAS",		PCI_SUBCLASS_MASS_STORAGE_SAS,	NULL,	},
 	{ "Flash",		PCI_SUBCLASS_MASS_STORAGE_NVM,
 	  pci_interface_nvm,	},
 	{ "miscellaneous",	PCI_SUBCLASS_MASS_STORAGE_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x02.
  * Network controller.
  */
 static const struct pci_class pci_subclass_network[] = {
 	{ "ethernet",		PCI_SUBCLASS_NETWORK_ETHERNET,	NULL,	},
 	{ "token ring",		PCI_SUBCLASS_NETWORK_TOKENRING,	NULL,	},
 	{ "FDDI",		PCI_SUBCLASS_NETWORK_FDDI,	NULL,	},
 	{ "ATM",		PCI_SUBCLASS_NETWORK_ATM,	NULL,	},
 	{ "ISDN",		PCI_SUBCLASS_NETWORK_ISDN,	NULL,	},
 	{ "WorldFip",		PCI_SUBCLASS_NETWORK_WORLDFIP,	NULL,	},
 	{ "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, },
 	{ "miscellaneous",	PCI_SUBCLASS_NETWORK_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x03.
  * Display controller.
  */
 /* VGA programming interface */
 static const struct pci_class pci_interface_vga[] = {
 	{ "",			PCI_INTERFACE_VGA_VGA,		NULL,	},
 	{ "8514-compat",	PCI_INTERFACE_VGA_8514,		NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /* Subclasses */
 static const struct pci_class pci_subclass_display[] = {
 	{ "VGA",		PCI_SUBCLASS_DISPLAY_VGA,  pci_interface_vga,},
 	{ "XGA",		PCI_SUBCLASS_DISPLAY_XGA,	NULL,	},
 	{ "3D",			PCI_SUBCLASS_DISPLAY_3D,	NULL,	},
 	{ "miscellaneous",	PCI_SUBCLASS_DISPLAY_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x04.
  * Multimedia device.
  */
 static const struct pci_class pci_subclass_multimedia[] = {
 	{ "video",		PCI_SUBCLASS_MULTIMEDIA_VIDEO,	NULL,	},
 	{ "audio",		PCI_SUBCLASS_MULTIMEDIA_AUDIO,	NULL,	},
 	{ "telephony",		PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,},
 	{ "mixed mode",		PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, },
 	{ "miscellaneous",	PCI_SUBCLASS_MULTIMEDIA_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x05.
  * Memory controller.
  */
 static const struct pci_class pci_subclass_memory[] = {
 	{ "RAM",		PCI_SUBCLASS_MEMORY_RAM,	NULL,	},
 	{ "flash",		PCI_SUBCLASS_MEMORY_FLASH,	NULL,	},
 	{ "miscellaneous",	PCI_SUBCLASS_MEMORY_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x06.
  * Bridge device.
  */
 /* PCI bridge programming interface */
 static const struct pci_class pci_interface_pcibridge[] = {
 	{ "",			PCI_INTERFACE_BRIDGE_PCI_PCI,	NULL,	},
 	{ "subtractive decode",	PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /* Semi-transparent PCI-to-PCI bridge programming interface */
 static const struct pci_class pci_interface_stpci[] = {
 	{ "primary side facing host",	PCI_INTERFACE_STPCI_PRIMARY, NULL, },
 	{ "secondary side facing host",	PCI_INTERFACE_STPCI_SECONDARY, NULL, },
 	{ NULL,			0,				NULL,	},
 };
 /* Advanced Switching programming interface */
 static const struct pci_class pci_interface_advsw[] = {
 	{ "custom interface",	PCI_INTERFACE_ADVSW_CUSTOM,	NULL, },
 	{ "ASI-SIG",		PCI_INTERFACE_ADVSW_ASISIG,	NULL, },
 	{ NULL,			0,				NULL,	},
 };
 /* Subclasses */
 static const struct pci_class pci_subclass_bridge[] = {
 	{ "host",		PCI_SUBCLASS_BRIDGE_HOST,	NULL,	},
 	{ "ISA",		PCI_SUBCLASS_BRIDGE_ISA,	NULL,	},
 	{ "EISA",		PCI_SUBCLASS_BRIDGE_EISA,	NULL,	},
 	{ "MicroChannel",	PCI_SUBCLASS_BRIDGE_MC,		NULL,	},
 	{ "PCI",		PCI_SUBCLASS_BRIDGE_PCI,
 	  pci_interface_pcibridge,	},
 	{ "PCMCIA",		PCI_SUBCLASS_BRIDGE_PCMCIA,	NULL,	},
 	{ "NuBus",		PCI_SUBCLASS_BRIDGE_NUBUS,	NULL,	},
 	{ "CardBus",		PCI_SUBCLASS_BRIDGE_CARDBUS,	NULL,	},
 	{ "RACEway",		PCI_SUBCLASS_BRIDGE_RACEWAY,	NULL,	},
 	{ "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI,
 	  pci_interface_stpci,	},
 	{ "InfiniBand",		PCI_SUBCLASS_BRIDGE_INFINIBAND,	NULL,	},
 	{ "advanced switching",	PCI_SUBCLASS_BRIDGE_ADVSW,
 	  pci_interface_advsw,	},
 	{ "miscellaneous",	PCI_SUBCLASS_BRIDGE_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x07.
  * Simple communications controller.
  */
 /* Serial controller programming interface */
 static const struct pci_class pci_interface_serial[] = {
 	{ "generic XT-compat",	PCI_INTERFACE_SERIAL_XT,	NULL,	},
 	{ "16450-compat",	PCI_INTERFACE_SERIAL_16450,	NULL,	},
 	{ "16550-compat",	PCI_INTERFACE_SERIAL_16550,	NULL,	},
 	{ "16650-compat",	PCI_INTERFACE_SERIAL_16650,	NULL,	},
 	{ "16750-compat",	PCI_INTERFACE_SERIAL_16750,	NULL,	},
 	{ "16850-compat",	PCI_INTERFACE_SERIAL_16850,	NULL,	},
 	{ "16950-compat",	PCI_INTERFACE_SERIAL_16950,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /* Parallel controller programming interface */
 static const struct pci_class pci_interface_parallel[] = {
 	{ "",			PCI_INTERFACE_PARALLEL,			NULL,},
 	{ "bi-directional",	PCI_INTERFACE_PARALLEL_BIDIRECTIONAL,	NULL,},
 	{ "ECP 1.X-compat",	PCI_INTERFACE_PARALLEL_ECP1X,		NULL,},
 	{ "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL,	NULL,},
 	{ "IEEE1284 target",	PCI_INTERFACE_PARALLEL_IEEE1284_TGT,	NULL,},
 	{ NULL,			0,					NULL,},
 };
 /* Modem programming interface */
 static const struct pci_class pci_interface_modem[] = {
 	{ "",			PCI_INTERFACE_MODEM,			NULL,},
 	{ "Hayes&16450-compat",	PCI_INTERFACE_MODEM_HAYES16450,		NULL,},
 	{ "Hayes&16550-compat",	PCI_INTERFACE_MODEM_HAYES16550,		NULL,},
 	{ "Hayes&16650-compat",	PCI_INTERFACE_MODEM_HAYES16650,		NULL,},
 	{ "Hayes&16750-compat",	PCI_INTERFACE_MODEM_HAYES16750,		NULL,},
 	{ NULL,			0,					NULL,},
 };
 /* Subclasses */
 static const struct pci_class pci_subclass_communications[] = {
 	{ "serial",		PCI_SUBCLASS_COMMUNICATIONS_SERIAL,
 	  pci_interface_serial, },
 	{ "parallel",		PCI_SUBCLASS_COMMUNICATIONS_PARALLEL,
 	  pci_interface_parallel, },
 	{ "multi-port serial",	PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL,	NULL,},
 	{ "modem",		PCI_SUBCLASS_COMMUNICATIONS_MODEM,
 	  pci_interface_modem, },
 	{ "GPIB",		PCI_SUBCLASS_COMMUNICATIONS_GPIB,	NULL,},
 	{ "smartcard",		PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD,	NULL,},
 	{ "miscellaneous",	PCI_SUBCLASS_COMMUNICATIONS_MISC,	NULL,},
 	{ NULL,			0,					NULL,},
 };
 /*
  * Class 0x08.
  * Base system peripheral.
  */
 /* PIC programming interface */
 static const struct pci_class pci_interface_pic[] = {
 	{ "generic 8259",	PCI_INTERFACE_PIC_8259,		NULL,	},
 	{ "ISA PIC",		PCI_INTERFACE_PIC_ISA,		NULL,	},
 	{ "EISA PIC",		PCI_INTERFACE_PIC_EISA,		NULL,	},
 	{ "IO APIC",		PCI_INTERFACE_PIC_IOAPIC,	NULL,	},
 	{ "IO(x) APIC",		PCI_INTERFACE_PIC_IOXAPIC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /* DMA programming interface */
 static const struct pci_class pci_interface_dma[] = {
 	{ "generic 8237",	PCI_INTERFACE_DMA_8237,		NULL,	},
 	{ "ISA",		PCI_INTERFACE_DMA_ISA,		NULL,	},
 	{ "EISA",		PCI_INTERFACE_DMA_EISA,		NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /* Timer programming interface */
 static const struct pci_class pci_interface_tmr[] = {
 	{ "generic 8254",	PCI_INTERFACE_TIMER_8254,	NULL,	},
 	{ "ISA",		PCI_INTERFACE_TIMER_ISA,	NULL,	},
 	{ "EISA",		PCI_INTERFACE_TIMER_EISA,	NULL,	},
 	{ "HPET",		PCI_INTERFACE_TIMER_HPET,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /* RTC programming interface */
 static const struct pci_class pci_interface_rtc[] = {
 	{ "generic",		PCI_INTERFACE_RTC_GENERIC,	NULL,	},
 	{ "ISA",		PCI_INTERFACE_RTC_ISA,		NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /* Subclasses */
 static const struct pci_class pci_subclass_system[] = {
 	{ "interrupt",		PCI_SUBCLASS_SYSTEM_PIC,   pci_interface_pic,},
 	{ "DMA",		PCI_SUBCLASS_SYSTEM_DMA,   pci_interface_dma,},
 	{ "timer",		PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,},
 	{ "RTC",		PCI_SUBCLASS_SYSTEM_RTC,   pci_interface_rtc,},
 	{ "PCI Hot-Plug",	PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL,	},
 	{ "SD Host Controller",	PCI_SUBCLASS_SYSTEM_SDHC,	NULL,	},
 	{ "IOMMU",		PCI_SUBCLASS_SYSTEM_IOMMU,	NULL,	},
 	{ "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, },
 	{ "miscellaneous",	PCI_SUBCLASS_SYSTEM_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x09.
  * Input device.
  */
 /* Gameport programming interface */
 static const struct pci_class pci_interface_game[] = {
 	{ "generic",		PCI_INTERFACE_GAMEPORT_GENERIC,	NULL,	},
 	{ "legacy",		PCI_INTERFACE_GAMEPORT_LEGACY,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /* Subclasses */
 static const struct pci_class pci_subclass_input[] = {
 	{ "keyboard",		PCI_SUBCLASS_INPUT_KEYBOARD,	NULL,	},
 	{ "digitizer",		PCI_SUBCLASS_INPUT_DIGITIZER,	NULL,	},
 	{ "mouse",		PCI_SUBCLASS_INPUT_MOUSE,	NULL,	},
 	{ "scanner",		PCI_SUBCLASS_INPUT_SCANNER,	NULL,	},
 	{ "game port",		PCI_SUBCLASS_INPUT_GAMEPORT,
 	  pci_interface_game, },
 	{ "miscellaneous",	PCI_SUBCLASS_INPUT_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x0a.
  * Docking station.
  */
 static const struct pci_class pci_subclass_dock[] = {
 	{ "generic",		PCI_SUBCLASS_DOCK_GENERIC,	NULL,	},
 	{ "miscellaneous",	PCI_SUBCLASS_DOCK_MISC,		NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x0b.
  * Processor.
  */
 static const struct pci_class pci_subclass_processor[] = {
 	{ "386",		PCI_SUBCLASS_PROCESSOR_386,	NULL,	},
 	{ "486",		PCI_SUBCLASS_PROCESSOR_486,	NULL,	},
 	{ "Pentium",		PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL,	},
 	{ "Alpha",		PCI_SUBCLASS_PROCESSOR_ALPHA,	NULL,	},
 	{ "PowerPC",		PCI_SUBCLASS_PROCESSOR_POWERPC, NULL,	},
 	{ "MIPS",		PCI_SUBCLASS_PROCESSOR_MIPS,	NULL,	},
 	{ "Co-processor",	PCI_SUBCLASS_PROCESSOR_COPROC,	NULL,	},
 	{ "miscellaneous",	PCI_SUBCLASS_PROCESSOR_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x0c.
  * Serial bus controller.
  */
 /* IEEE1394 programming interface */
 static const struct pci_class pci_interface_ieee1394[] = {
 	{ "Firewire",		PCI_INTERFACE_IEEE1394_FIREWIRE,	NULL,},
 	{ "OpenHCI",		PCI_INTERFACE_IEEE1394_OPENHCI,		NULL,},
 	{ NULL,			0,					NULL,},
 };
 /* USB programming interface */
 static const struct pci_class pci_interface_usb[] = {
 	{ "UHCI",		PCI_INTERFACE_USB_UHCI,		NULL,	},
 	{ "OHCI",		PCI_INTERFACE_USB_OHCI,		NULL,	},
 	{ "EHCI",		PCI_INTERFACE_USB_EHCI,		NULL,	},
 	{ "xHCI",		PCI_INTERFACE_USB_XHCI,		NULL,	},
 	{ "other HC",		PCI_INTERFACE_USB_OTHERHC,	NULL,	},
 	{ "device",		PCI_INTERFACE_USB_DEVICE,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /* IPMI programming interface */
 static const struct pci_class pci_interface_ipmi[] = {
 	{ "SMIC",		PCI_INTERFACE_IPMI_SMIC,	NULL,	},
 	{ "keyboard",		PCI_INTERFACE_IPMI_KBD,		NULL,	},
 	{ "block transfer",	PCI_INTERFACE_IPMI_BLOCKXFER,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /* Subclasses */
 static const struct pci_class pci_subclass_serialbus[] = {
 	{ "IEEE1394",		PCI_SUBCLASS_SERIALBUS_FIREWIRE,
 	  pci_interface_ieee1394, },
 	{ "ACCESS.bus",		PCI_SUBCLASS_SERIALBUS_ACCESS,	NULL,	},
 	{ "SSA",		PCI_SUBCLASS_SERIALBUS_SSA,	NULL,	},
 	{ "USB",		PCI_SUBCLASS_SERIALBUS_USB,
 	  pci_interface_usb, },
 	/* XXX Fiber Channel/_FIBRECHANNEL */
 	{ "Fiber Channel",	PCI_SUBCLASS_SERIALBUS_FIBER,	NULL,	},
 	{ "SMBus",		PCI_SUBCLASS_SERIALBUS_SMBUS,	NULL,	},
 	{ "InfiniBand",		PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,},
 	{ "IPMI",		PCI_SUBCLASS_SERIALBUS_IPMI,
 	  pci_interface_ipmi, },
 	{ "SERCOS",		PCI_SUBCLASS_SERIALBUS_SERCOS,	NULL,	},
 	{ "CANbus",		PCI_SUBCLASS_SERIALBUS_CANBUS,	NULL,	},
 	{ "miscellaneous",	PCI_SUBCLASS_SERIALBUS_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x0d.
  * Wireless Controller.
  */
 static const struct pci_class pci_subclass_wireless[] = {
 	{ "IrDA",		PCI_SUBCLASS_WIRELESS_IRDA,	NULL,	},
 	{ "Consumer IR",/*XXX*/	PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL,	},
 	{ "RF",			PCI_SUBCLASS_WIRELESS_RF,	NULL,	},
 	{ "bluetooth",		PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL,	},
 	{ "broadband",		PCI_SUBCLASS_WIRELESS_BROADBAND, NULL,	},
 	{ "802.11a (5 GHz)",	PCI_SUBCLASS_WIRELESS_802_11A,	NULL,	},
 	{ "802.11b (2.4 GHz)",	PCI_SUBCLASS_WIRELESS_802_11B,	NULL,	},
 	{ "miscellaneous",	PCI_SUBCLASS_WIRELESS_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x0e.
  * Intelligent IO controller.
  */
 /* Intelligent IO programming interface */
 static const struct pci_class pci_interface_i2o[] = {
 	{ "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /* Subclasses */
 static const struct pci_class pci_subclass_i2o[] = {
 	{ "standard",		PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,},
 	{ "miscellaneous",	PCI_SUBCLASS_I2O_MISC,		NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x0f.
  * Satellite communication controller.
  */
 static const struct pci_class pci_subclass_satcom[] = {
 	{ "TV",			PCI_SUBCLASS_SATCOM_TV,		NULL,	},
 	{ "audio",		PCI_SUBCLASS_SATCOM_AUDIO,	NULL,	},
 	{ "voice",		PCI_SUBCLASS_SATCOM_VOICE,	NULL,	},
 	{ "data",		PCI_SUBCLASS_SATCOM_DATA,	NULL,	},
 	{ "miscellaneous",	PCI_SUBCLASS_SATCOM_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x10.
  * Encryption/Decryption controller.
  */
 static const struct pci_class pci_subclass_crypto[] = {
 	{ "network/computing",	PCI_SUBCLASS_CRYPTO_NETCOMP,	NULL,	},
 	{ "entertainment",	PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,},
 	{ "miscellaneous",	PCI_SUBCLASS_CRYPTO_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /*
  * Class 0x11.
  * Data aquuisition and signal processing controller.
  */
 static const struct pci_class pci_subclass_dasp[] = {
 	{ "DPIO",		PCI_SUBCLASS_DASP_DPIO,		NULL,	},
 	{ "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ,	NULL,	},
 	{ "synchronization",	PCI_SUBCLASS_DASP_SYNC,		NULL,	},
 	{ "management",		PCI_SUBCLASS_DASP_MGMT,		NULL,	},
 	{ "miscellaneous",	PCI_SUBCLASS_DASP_MISC,		NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 /* List of classes */
 static const struct pci_class pci_classes[] = {
 	{ "prehistoric",	PCI_CLASS_PREHISTORIC,
 	    pci_subclass_prehistoric,				},
 	{ "mass storage",	PCI_CLASS_MASS_STORAGE,
 	    pci_subclass_mass_storage,				},
 	{ "network",		PCI_CLASS_NETWORK,
 	    pci_subclass_network,				},
 	{ "display",		PCI_CLASS_DISPLAY,
 	    pci_subclass_display,				},
 	{ "multimedia",		PCI_CLASS_MULTIMEDIA,
 	    pci_subclass_multimedia,				},
 	{ "memory",		PCI_CLASS_MEMORY,
 	    pci_subclass_memory,				},
 	{ "bridge",		PCI_CLASS_BRIDGE,
 	    pci_subclass_bridge,				},
 	{ "communications",	PCI_CLASS_COMMUNICATIONS,
 	    pci_subclass_communications,			},
 	{ "system",		PCI_CLASS_SYSTEM,
 	    pci_subclass_system,				},
 	{ "input",		PCI_CLASS_INPUT,
 	    pci_subclass_input,					},
 	{ "dock",		PCI_CLASS_DOCK,
 	    pci_subclass_dock,					},
 	{ "processor",		PCI_CLASS_PROCESSOR,
 	    pci_subclass_processor,				},
 	{ "serial bus",		PCI_CLASS_SERIALBUS,
 	    pci_subclass_serialbus,				},
 	{ "wireless",		PCI_CLASS_WIRELESS,
 	    pci_subclass_wireless,				},
 	{ "I2O",		PCI_CLASS_I2O,
 	    pci_subclass_i2o,					},
 	{ "satellite comm",	PCI_CLASS_SATCOM,
 	    pci_subclass_satcom,				},
 	{ "crypto",		PCI_CLASS_CRYPTO,
 	    pci_subclass_crypto,				},
 	{ "DASP",		PCI_CLASS_DASP,
 	    pci_subclass_dasp,					},
 	{ "processing accelerators", PCI_CLASS_ACCEL,
 	    NULL,						},
 	{ "non-essential instrumentation", PCI_CLASS_INSTRUMENT,
 	    NULL,						},
 	{ "undefined",		PCI_CLASS_UNDEFINED,
 	    NULL,						},
 	{ NULL,			0,
 	    NULL,						},
 };
 DEV_VERBOSE_DEFINE(pci);
 /*
  * Append a formatted string to dest without writing more than len
  * characters (including the trailing NUL character).  dest and len
  * are updated for use in subsequent calls to snappendf().
+ *
  * Returns 0 on success, a negative value if vnsprintf() fails, or
  * a positive value if the dest buffer would have overflowed.
  */
 static int __printflike(3, 4)
 snappendf(char **dest, size_t *len, const char * restrict fmt, ...)
+{
 	va_list	ap;
 	int count;
 	va_start(ap, fmt);
 	count = vsnprintf(*dest, *len, fmt, ap);
 	va_end(ap);
 	/* Let vsnprintf() errors bubble up to caller */
 	if (count < 0 || *len == 0)
 		return count;
 	/* Handle overflow */
 	if ((size_t)count >= *len) {
 		*dest += *len - 1;
 		*len = 1;
 		return 1;
+	}
 	/* Update dest & len to point at trailing NUL */
 	*dest += count;
 	*len -= count;
 	return 0;
+}
 void
 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp,
     size_t l)
+{
 	pci_class_t class;
 	pci_subclass_t subclass;
 	pci_interface_t interface;
 	pci_revision_t revision;
 	char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN];
 	const struct pci_class *classp, *subclassp, *interfacep;
 	class = PCI_CLASS(class_reg);
 	subclass = PCI_SUBCLASS(class_reg);
 	interface = PCI_INTERFACE(class_reg);
 	revision = PCI_REVISION(class_reg);
 	pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg));
 	pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg),
 	    PCI_PRODUCT(id_reg));
 	classp = pci_classes;
 	while (classp->name != NULL) {
 		if (class == classp->val)
 			break;
 		classp++;
+	}
 	subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
 	while (subclassp && subclassp->name != NULL) {
 		if (subclass == subclassp->val)
 			break;
 		subclassp++;
+	}
 	interfacep = (subclassp && subclassp->name != NULL) ?
 	    subclassp->subclasses : NULL;
 	while (interfacep && interfacep->name != NULL) {
 		if (interface == interfacep->val)
 			break;
 		interfacep++;
+	}
 	(void)snappendf(&cp, &l, "%s %s", vendor, product);
 	if (showclass) {
 		(void)snappendf(&cp, &l, " (");
 		if (classp->name == NULL)
 			(void)snappendf(&cp, &l,
 			    "class 0x%02x, subclass 0x%02x",
 			    class, subclass);
 		else {
 			if (subclassp == NULL || subclassp->name == NULL)
 				(void)snappendf(&cp, &l,
 				    "%s, subclass 0x%02x",
 				    classp->name, subclass);
 			else
 				(void)snappendf(&cp, &l, "%s %s",
 				    subclassp->name, classp->name);
+		}
 		if ((interfacep == NULL) || (interfacep->name == NULL)) {
 			if (interface != 0)
 				(void)snappendf(&cp, &l, ", interface 0x%02x",
 				    interface);
 		} else if (strncmp(interfacep->name, "", 1) != 0)
 			(void)snappendf(&cp, &l, ", %s", interfacep->name);
 		if (revision != 0)
 			(void)snappendf(&cp, &l, ", revision 0x%02x", revision);
 		(void)snappendf(&cp, &l, ")");
+	}
+}
 #ifdef _KERNEL
 void
 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive,
 			 const char *known, int addrev)
+{
 	char devinfo[256];
 	if (known) {
 		aprint_normal(": %s", known);
 		if (addrev)
 			aprint_normal(" (rev. 0x%02x)",
 				      PCI_REVISION(pa->pa_class));
 		aprint_normal("\n");
 	} else {
 		pci_devinfo(pa->pa_id, pa->pa_class, 0,
 			    devinfo, sizeof(devinfo));
 		aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
 			      PCI_REVISION(pa->pa_class));
+	}
 	if (naive)
 		aprint_naive(": %s\n", naive);
 	else
 		aprint_naive("\n");
+}
 #endif
 /*
  * Print out most of the PCI configuration registers.  Typically used
  * in a device attach routine like this:
+ *
  *	#ifdef MYDEV_DEBUG
  *		printf("%s: ", device_xname(sc->sc_dev));
  *		pci_conf_print(pa->pa_pc, pa->pa_tag, NULL);
  *	#endif
  */
 #define	i2o(i)	((i) * 4)
 #define	o2i(o)	((o) / 4)
 #define	onoff2(str, rval, bit, onstr, offstr)				\
 	/*CONSTCOND*/							\
 	printf("      %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr);
 #define	onoff(str, rval, bit)	onoff2(str, rval, bit, "on", "off")
 static void
 pci_conf_print_common(
 #ifdef _KERNEL
     pci_chipset_tag_t pc, pcitag_t tag,
 #endif
     const pcireg_t *regs)
+{
 	pci_class_t class;
 	pci_subclass_t subclass;
 	pci_interface_t interface;
 	pci_revision_t revision;
 	char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN];
 	const struct pci_class *classp, *subclassp, *interfacep;
 	const char *name;
 	pcireg_t rval;
 	unsigned int num;
 	rval = regs[o2i(PCI_CLASS_REG)];
 	class = PCI_CLASS(rval);
 	subclass = PCI_SUBCLASS(rval);
 	interface = PCI_INTERFACE(rval);
 	revision = PCI_REVISION(rval);
 	rval = regs[o2i(PCI_ID_REG)];
 	name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval));
 	if (name)
 		printf("    Vendor Name: %s (0x%04x)\n", name,
 		    PCI_VENDOR(rval));
 	else
 		printf("    Vendor ID: 0x%04x\n", PCI_VENDOR(rval));
 	name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval),
 	    PCI_PRODUCT(rval));
 	if (name)
 		printf("    Device Name: %s (0x%04x)\n", name,
 		    PCI_PRODUCT(rval));
 	else
 		printf("    Device ID: 0x%04x\n", PCI_PRODUCT(rval));
 	rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
 	printf("    Command register: 0x%04x\n", rval & 0xffff);
 	onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE);
 	onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE);
 	onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE);
 	onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE);
 	onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE);
 	onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE);
 	onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE);
 	onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE);
 	onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE);
 	onoff("Fast back-to-back transactions", rval,
 	    PCI_COMMAND_BACKTOBACK_ENABLE);
 	onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE);
 	printf("    Status register: 0x%04x\n", (rval >> 16) & 0xffff);
 	onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS);
 	onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active",
 	    "inactive");
 	onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT);
 	onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT);
 	onoff("User Definable Features (UDF) support", rval,
 	    PCI_STATUS_UDF_SUPPORT);
 	onoff("Fast back-to-back capable", rval,
 	    PCI_STATUS_BACKTOBACK_SUPPORT);
 	onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR);
 	printf("      DEVSEL timing: ");
 	switch (rval & PCI_STATUS_DEVSEL_MASK) {
 	case PCI_STATUS_DEVSEL_FAST:
 		printf("fast");
 		break;
 	case PCI_STATUS_DEVSEL_MEDIUM:
 		printf("medium");
 		break;
 	case PCI_STATUS_DEVSEL_SLOW:
 		printf("slow");
 		break;
 	default:
 		printf("unknown/reserved");	/* XXX */
 		break;
+	}
 	printf(" (0x%x)\n", PCIREG_SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK));
 	onoff("Slave signaled Target Abort", rval,
 	    PCI_STATUS_TARGET_TARGET_ABORT);
 	onoff("Master received Target Abort", rval,
 	    PCI_STATUS_MASTER_TARGET_ABORT);
 	onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT);
 	onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR);
 	onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT);
 	rval = regs[o2i(PCI_CLASS_REG)];
 	for (classp = pci_classes; classp->name != NULL; classp++) {
 		if (class == classp->val)
 			break;
+	}
 	/*
 	 * ECN: Change Root Complex Event Collector Class Code
 	 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type
 	 * in PCIe extend capability to know whether it's RCEC or IOMMU.
 	 */
 	if ((class == PCI_CLASS_SYSTEM)
 	    && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) {
 		int pcie_capoff;
 		pcireg_t reg;
 		if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
 			reg = regs[o2i(pcie_capoff + PCIE_XCAP)];
 			if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC)
 				subclass = PCI_SUBCLASS_SYSTEM_RCEC;
+		}
+	}
 	subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
 	while (subclassp && subclassp->name != NULL) {
 		if (subclass == subclassp->val)
 			break;
 		subclassp++;
+	}
 	interfacep = (subclassp && subclassp->name != NULL) ?
 	    subclassp->subclasses : NULL;
 	while (interfacep && interfacep->name != NULL) {
 		if (interface == interfacep->val)
 			break;
 		interfacep++;
+	}
 	if (classp->name != NULL)
 		printf("    Class Name: %s (0x%02x)\n", classp->name, class);
 	else
 		printf("    Class ID: 0x%02x\n", class);
 	if (subclassp != NULL && subclassp->name != NULL)
 		printf("    Subclass Name: %s (0x%02x)\n",
 		    subclassp->name, PCI_SUBCLASS(rval));
 	else
 		printf("    Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
 	if ((interfacep != NULL) && (interfacep->name != NULL)
 	    && (strncmp(interfacep->name, "", 1) != 0))
 		printf("    Interface Name: %s (0x%02x)\n",
 		    interfacep->name, interface);
 	else
 		printf("    Interface: 0x%02x\n", interface);
 	printf("    Revision ID: 0x%02x\n", revision);
 	rval = regs[o2i(PCI_BHLC_REG)];
 	printf("    BIST: 0x%02x\n", PCI_BIST(rval));
 	printf("    Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval),
 	    PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "",
 	    PCI_HDRTYPE(rval));
 	printf("    Latency Timer: 0x%02x\n", PCI_LATTIMER(rval));
 	num = PCI_CACHELINE(rval);
 	printf("    Cache Line Size: %ubytes (0x%02x)\n", num * 4, num);
+}
 static int
 pci_conf_print_bar(
 #ifdef _KERNEL
     pci_chipset_tag_t pc, pcitag_t tag,
 #endif
     const pcireg_t *regs, int reg, const char *name)
+{
 	int width;
 	pcireg_t rval, rval64h;
 	bool ioen, memen;
 #ifdef _KERNEL
 	pcireg_t mask, mask64h = 0;
 #endif
 	rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
 	ioen = rval & PCI_COMMAND_IO_ENABLE;
 	memen = rval & PCI_COMMAND_MEM_ENABLE;
 	width = 4;
 	/*
 	 * Section 6.2.5.1, `Address Maps', tells us that:
+	 *
 	 * 1) The builtin software should have already mapped the
 	 * device in a reasonable way.
+	 *
 	 * 2) A device which wants 2^n bytes of memory will hardwire
 	 * the bottom n bits of the address to 0.  As recommended,
 	 * we write all 1s and see what we get back.
 	 */
 	rval = regs[o2i(reg)];
 	if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
 	    PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
 		rval64h = regs[o2i(reg + 4)];
 		width = 8;
 	} else
 		rval64h = 0;
 #ifdef _KERNEL
 	if (rval != 0 && memen) {
 		int s;
 		/*
 		 * The following sequence seems to make some devices
 		 * (e.g. host bus bridges, which don't normally
 		 * have their space mapped) very unhappy, to
 		 * the point of crashing the system.
+		 *
 		 * Therefore, if the mapping register is zero to
 		 * start out with, don't bother trying.
 		 */
 		s = splhigh();
 		pci_conf_write(pc, tag, reg, 0xffffffff);
 		mask = pci_conf_read(pc, tag, reg);
 		pci_conf_write(pc, tag, reg, rval);
 		if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
 		    PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
 			pci_conf_write(pc, tag, reg + 4, 0xffffffff);
 			mask64h = pci_conf_read(pc, tag, reg + 4);
 			pci_conf_write(pc, tag, reg + 4, rval64h);
+		}
 		splx(s);
 	} else
 		mask = mask64h = 0;
 #endif /* _KERNEL */
 	printf("    Base address register at 0x%02x", reg);
 	if (name)
 		printf(" (%s)", name);
 	printf("\n      ");
 	if (rval == 0) {
 		printf("not implemented\n");
 		return width;
+	}
 	printf("type: ");
 	if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) {
 		const char *type, *prefetch;
 		switch (PCI_MAPREG_MEM_TYPE(rval)) {
 		case PCI_MAPREG_MEM_TYPE_32BIT:
 			type = "32-bit";
 			break;
 		case PCI_MAPREG_MEM_TYPE_32BIT_1M:
 			type = "32-bit-1M";
 			break;
 		case PCI_MAPREG_MEM_TYPE_64BIT:
 			type = "64-bit";
 			break;
 		default:
 			type = "unknown (XXX)";
 			break;
+		}
 		if (PCI_MAPREG_MEM_PREFETCHABLE(rval))
 			prefetch = "";
 		else
 			prefetch = "non";
 		printf("%s %sprefetchable memory\n", type, prefetch);
 		switch (PCI_MAPREG_MEM_TYPE(rval)) {
 		case PCI_MAPREG_MEM_TYPE_64BIT:
 			printf("      base: 0x%016llx",
 			    PCI_MAPREG_MEM64_ADDR(
 				((((long long) rval64h) << 32) | rval)));
 			if (!memen)
 				printf(", disabled");
 			printf("\n");
 #ifdef _KERNEL
 			printf("      size: 0x%016llx\n",
 			    PCI_MAPREG_MEM64_SIZE(
 				    ((((long long) mask64h) << 32) | mask)));
 #endif
 			break;
 		case PCI_MAPREG_MEM_TYPE_32BIT:
 		case PCI_MAPREG_MEM_TYPE_32BIT_1M:
 		default:
 			printf("      base: 0x%08x",
 			    PCI_MAPREG_MEM_ADDR(rval));
 			if (!memen)
 				printf(", disabled");
 			printf("\n");
 #ifdef _KERNEL
 			printf("      size: 0x%08x\n",
 			    PCI_MAPREG_MEM_SIZE(mask));
 #endif
 			break;
+		}
 	} else {
 #ifdef _KERNEL
 		if (ioen)
 			printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16);
 #endif
 		printf("I/O\n");
 		printf("      base: 0x%08x", PCI_MAPREG_IO_ADDR(rval));
 		if (!ioen)
 			printf(", disabled");
 		printf("\n");
 #ifdef _KERNEL
 		printf("      size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask));
 #endif
+	}
 	return width;
+}
 static void
 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast)
+{
 	int off, needaddr, neednl;
 	needaddr = 1;
 	neednl = 0;
 	for (off = first; off < pastlast; off += 4) {
 		if ((off % 16) == 0 || needaddr) {
 			printf("    0x%02x:", off);
 			needaddr = 0;
+		}
 		printf(" 0x%08x", regs[o2i(off)]);
 		neednl = 1;
 		if ((off % 16) == 12) {
 			printf("\n");
 			neednl = 0;
+		}
+	}
 	if (neednl)
 		printf("\n");
+}
 static const char *
 pci_conf_print_agp_calcycle(uint8_t cal)
+{
 	switch (cal) {
 	case 0x0:
 		return "4ms";
 	case 0x1:
 		return "16ms";
 	case 0x2:
 		return "64ms";
 	case 0x3:
 		return "256ms";
 	case 0x7:
 		return "Calibration Cycle Not Needed";
 	default:
 		return "(reserved)";
+	}
+}
 static void
 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3)
+{
 	if (isagp3) {
 		/* AGP 3.0 */
 		if (reg & AGP_MODE_V3_RATE_4x)

 @@ -1,427 +1,443 @@
-/*	$NetBSD: pcivar.h,v 1.113 2018/12/01 01:23:24 msaitoh Exp $	*/
+/*	$NetBSD: pcivar.h,v 1.114 2021/01/27 05:00:16 thorpej Exp $	*/
 /*
  * Copyright (c) 1996, 1997 Christopher G. Demetriou.  All rights reserved.
  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Charles M. Hannum.
  * 4. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #ifndef _DEV_PCI_PCIVAR_H_
 #define	_DEV_PCI_PCIVAR_H_
 /*
  * Definitions for PCI autoconfiguration.
+ *
  * This file describes types and functions which are used for PCI
  * configuration.  Some of this information is machine-specific, and is
  * provided by pci_machdep.h.
  */
 #include <sys/device.h>
 #include <sys/pmf.h>
 #include <sys/bus.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pci_verbose.h>
 /*
  * Structures and definitions needed by the machine-dependent header.
  */
 struct pcibus_attach_args;
 struct pci_attach_args;
 struct pci_softc;
 #ifdef _KERNEL
 /*
  * Machine-dependent definitions.
  */
 #include <machine/pci_machdep.h>
 enum pci_override_idx {
 	  PCI_OVERRIDE_CONF_READ		= __BIT(0)
 	, PCI_OVERRIDE_CONF_WRITE		= __BIT(1)
 	, PCI_OVERRIDE_INTR_MAP			= __BIT(2)
 	, PCI_OVERRIDE_INTR_STRING		= __BIT(3)
 	, PCI_OVERRIDE_INTR_EVCNT		= __BIT(4)
 	, PCI_OVERRIDE_INTR_ESTABLISH		= __BIT(5)
 	, PCI_OVERRIDE_INTR_DISESTABLISH	= __BIT(6)
 	, PCI_OVERRIDE_MAKE_TAG			= __BIT(7)
 	, PCI_OVERRIDE_DECOMPOSE_TAG		= __BIT(8)
 };
 /* Only add new fields to the end of this structure! */
 struct pci_overrides {
 	pcireg_t (*ov_conf_read)(void *, pci_chipset_tag_t, pcitag_t, int);
 	void (*ov_conf_write)(void *, pci_chipset_tag_t, pcitag_t, int,
 	    pcireg_t);
 	int (*ov_intr_map)(void *, const struct pci_attach_args *,
 	   pci_intr_handle_t *);
 	const char *(*ov_intr_string)(void *, pci_chipset_tag_t,
 	    pci_intr_handle_t, char *, size_t);
 	const struct evcnt *(*ov_intr_evcnt)(void *, pci_chipset_tag_t,
 	    pci_intr_handle_t);
 	void *(*ov_intr_establish)(void *, pci_chipset_tag_t, pci_intr_handle_t,
 	    int, int (*)(void *), void *);
 	void (*ov_intr_disestablish)(void *, pci_chipset_tag_t, void *);
 	pcitag_t (*ov_make_tag)(void *, pci_chipset_tag_t, int, int, int);
 	void (*ov_decompose_tag)(void *, pci_chipset_tag_t, pcitag_t,
 	    int *, int *, int *);
 };
 /*
  * PCI bus attach arguments.
  */
 struct pcibus_attach_args {
 	char		*_pba_busname;	/* XXX placeholder */
 	bus_space_tag_t pba_iot;	/* pci i/o space tag */
 	bus_space_tag_t pba_memt;	/* pci mem space tag */
 	bus_dma_tag_t pba_dmat;		/* DMA tag */
 	bus_dma_tag_t pba_dmat64;	/* DMA tag */
 	pci_chipset_tag_t pba_pc;
 	int		pba_flags;	/* flags; see below */
 	int		pba_bus;	/* PCI bus number */
 	int		pba_sub;	/* pba_bus >= pba_sub: no
 					 * buses are subordinate to
 					 * pba_bus.
+					 *
 					 * pba_bus < pba_sub: buses
 					 * [pba_bus + 1, pba_sub] are
 					 * subordinate to pba_bus.
 					 */
 	/*
 	 * Pointer to the pcitag of our parent bridge.  If there is no
 	 * parent bridge, then we assume we are a root bus.
 	 */
 	pcitag_t	*pba_bridgetag;
 	/*
 	 * Interrupt swizzling information.  These fields
 	 * are only used by secondary busses.
 	 */
 	u_int		pba_intrswiz;	/* how to swizzle pins */
 	pcitag_t	pba_intrtag;	/* intr. appears to come from here */
 };
 /*
  * This is used by <machine/pci_machdep.h> to access the pba_pc member.  It
  * can't use it directly since pcibus_attach_args has yet to be defined.
  */
 static __inline pci_chipset_tag_t
 pcibus_attach_args_pc(struct pcibus_attach_args *pba)
+{
 	return pba->pba_pc;
+}
 /*
  * PCI device attach arguments.
  */
 struct pci_attach_args {
 	bus_space_tag_t pa_iot;		/* pci i/o space tag */
 	bus_space_tag_t pa_memt;	/* pci mem space tag */
 	bus_dma_tag_t pa_dmat;		/* DMA tag */
 	bus_dma_tag_t pa_dmat64;	/* DMA tag */
 	pci_chipset_tag_t pa_pc;
 	int		pa_flags;	/* flags; see below */
 	u_int		pa_bus;
 	u_int		pa_device;
 	u_int		pa_function;
 	pcitag_t	pa_tag;
 	pcireg_t	pa_id, pa_class;
 	/*
 	 * Interrupt information.
+	 *
 	 * "Intrline" is used on systems whose firmware puts
 	 * the right routing data into the line register in
 	 * configuration space.  The rest are used on systems
 	 * that do not.
 	 */
 	u_int		pa_intrswiz;	/* how to swizzle pins if ppb */
 	pcitag_t	pa_intrtag;	/* intr. appears to come from here */
 	pci_intr_pin_t	pa_intrpin;	/* intr. appears on this pin */
 	pci_intr_line_t	pa_intrline;	/* intr. routing information */
 	pci_intr_pin_t  pa_rawintrpin; 	/* unswizzled pin */
 };
 /*
  * This is used by <machine/pci_machdep.h> to access the pa_pc member.  It
  * can't use it directly since pci_attach_args has yet to be defined.
  */
 static __inline pci_chipset_tag_t
 pci_attach_args_pc(const struct pci_attach_args *pa)
+{
 	return pa->pa_pc;
+}
 /*
  * Flags given in the bus and device attachment args.
  */
 #define	PCI_FLAGS_IO_OKAY	0x01		/* I/O space is okay */
 #define	PCI_FLAGS_MEM_OKAY	0x02		/* memory space is okay */
 #define	PCI_FLAGS_MRL_OKAY	0x04		/* Memory Read Line okay */
 #define	PCI_FLAGS_MRM_OKAY	0x08		/* Memory Read Multiple okay */
 #define	PCI_FLAGS_MWI_OKAY	0x10		/* Memory Write and Invalidate
 						   okay */
 #define	PCI_FLAGS_MSI_OKAY	0x20		/* Message Signaled Interrupts
 						   okay */
 #define	PCI_FLAGS_MSIX_OKAY	0x40		/* Message Signaled Interrupts
 						   (Extended) okay */
 /*
  * PCI device 'quirks'.
+ *
  * In general strange behaviour which can be handled by a driver (e.g.
  * a bridge's inability to pass a type of access correctly) should be.
  * The quirks table should only contain information which impacts
  * the operation of the MI PCI code and which can't be pushed lower
  * (e.g. because it's unacceptable to require a driver to be present
  * for the information to be known).
  */
 struct pci_quirkdata {
 	pci_vendor_id_t		vendor;		/* Vendor ID */
 	pci_product_id_t	product;	/* Product ID */
 	int			quirks;		/* quirks; see below */
 };
 #define	PCI_QUIRK_MULTIFUNCTION		__BIT(0)
 #define	PCI_QUIRK_MONOFUNCTION		__BIT(1)
 #define	PCI_QUIRK_SKIP_FUNC(n)		(4 << n)
 #define	PCI_QUIRK_SKIP_FUNC0		PCI_QUIRK_SKIP_FUNC(0)
 #define	PCI_QUIRK_SKIP_FUNC1		PCI_QUIRK_SKIP_FUNC(1)
 #define	PCI_QUIRK_SKIP_FUNC2		PCI_QUIRK_SKIP_FUNC(2)
 #define	PCI_QUIRK_SKIP_FUNC3		PCI_QUIRK_SKIP_FUNC(3)
 #define	PCI_QUIRK_SKIP_FUNC4		PCI_QUIRK_SKIP_FUNC(4)
 #define	PCI_QUIRK_SKIP_FUNC5		PCI_QUIRK_SKIP_FUNC(5)
 #define	PCI_QUIRK_SKIP_FUNC6		PCI_QUIRK_SKIP_FUNC(6)
 #define	PCI_QUIRK_SKIP_FUNC7		PCI_QUIRK_SKIP_FUNC(7)
 #define	PCI_QUIRK_HASEXTCNF		__BIT(10)
 #define	PCI_QUIRK_NOEXTCNF		__BIT(11)
 struct pci_conf_state {
 	pcireg_t reg[16];
 	/* For PCI-X */
 	pcireg_t x_csr;		/* Upper 16bits. Lower 16bits are read only */
 	/* For PCIe */
 	uint16_t e_dcr;
 	uint16_t e_lcr;
 	uint16_t e_slcr;
 	uint16_t e_rcr;
 	uint16_t e_dcr2;
 	uint16_t e_lcr2;
 	/* For MSI */
 	pcireg_t msi_ctl;	/* Upper 16bits. Lower 16bits are read only */
 	pcireg_t msi_maddr;
 	pcireg_t msi_maddr64_hi;
 	pcireg_t msi_mdata;
 	pcireg_t msi_mask;
 	/* For MSI-X */
 	pcireg_t msix_ctl;	/* Upper 16bits. Lower 16bits are read only */
 };
 struct pci_range {
 	bus_addr_t		r_offset;
 	bus_size_t		r_size;
 	int			r_flags;
 };
 struct pci_child {
 	device_t		c_dev;
 	bool			c_psok;
 	pcireg_t		c_powerstate;
 	struct pci_conf_state	c_conf;
 	struct pci_range	c_range[8];
 };
 struct pci_softc {
 	device_t sc_dev;
 	bus_space_tag_t sc_iot, sc_memt;
 	bus_dma_tag_t sc_dmat;
 	bus_dma_tag_t sc_dmat64;
 	pci_chipset_tag_t sc_pc;
 	int sc_bus, sc_maxndevs;
 	pcitag_t *sc_bridgetag;
 	u_int sc_intrswiz;
 	pcitag_t sc_intrtag;
 	int sc_flags;
 	/* accounting of child devices */
 	struct pci_child sc_devices[32*8];
 #define PCI_SC_DEVICESC(d, f) sc_devices[(d) * 8 + (f)]
 };
 extern struct cfdriver pci_cd;
 extern bool pci_mapreg_map_enable_decode;
 int pcibusprint(void *, const char *);
 /*
  * Configuration space access and utility functions.  (Note that most,
  * e.g. make_tag, conf_read, conf_write are declared by pci_machdep.h.)
  */
 int	pci_mapreg_probe(pci_chipset_tag_t, pcitag_t, int, pcireg_t *);
 pcireg_t pci_mapreg_type(pci_chipset_tag_t, pcitag_t, int);
 int	pci_mapreg_info(pci_chipset_tag_t, pcitag_t, int, pcireg_t,
 	    bus_addr_t *, bus_size_t *, int *);
 int	pci_mapreg_map(const struct pci_attach_args *, int, pcireg_t, int,
 	    bus_space_tag_t *, bus_space_handle_t *, bus_addr_t *,
 	    bus_size_t *);
 int	pci_mapreg_submap(const struct pci_attach_args *, int, pcireg_t, int,
 	    bus_size_t, bus_size_t, bus_space_tag_t *, bus_space_handle_t *,
 	    bus_addr_t *, bus_size_t *);
 int pci_find_rom(const struct pci_attach_args *, bus_space_tag_t,
 	    bus_space_handle_t, bus_size_t,
 	    int, bus_space_handle_t *, bus_size_t *);
 int	pci_get_capability(pci_chipset_tag_t, pcitag_t, int, int *, pcireg_t *);
 int	pci_get_ht_capability(pci_chipset_tag_t, pcitag_t, int, int *,
 	    pcireg_t *);
 int	pci_get_ext_capability(pci_chipset_tag_t, pcitag_t, int, int *,
 	    pcireg_t *);
 int	pci_msi_count(pci_chipset_tag_t, pcitag_t);
 int	pci_msix_count(pci_chipset_tag_t, pcitag_t);
 /*
  * Helper functions for autoconfiguration.
  */
 #define	PCI_COMPAT_EOL_VALUE	(0xffffffffU)
 #define	PCI_COMPAT_EOL		{ .id = PCI_COMPAT_EOL_VALUE }
 const struct device_compatible_entry *
 	pci_compatible_lookup_id(pcireg_t,
 	    const struct device_compatible_entry *);
 const struct device_compatible_entry *
 	pci_compatible_lookup(const struct pci_attach_args *,
 	    const struct device_compatible_entry *);
 int	pci_compatible_match(const struct pci_attach_args *,
 	    const struct device_compatible_entry *);
 const struct device_compatible_entry *
 	pci_compatible_lookup_subsys(const struct pci_attach_args *,
 	    const struct device_compatible_entry *);
 int	pci_compatible_match_subsys(const struct pci_attach_args *,
 	    const struct device_compatible_entry *);
 #ifndef PCI_MACHDEP_ENUMERATE_BUS
 int	pci_enumerate_bus(struct pci_softc *, const int *,
 	    int (*)(const struct pci_attach_args *), struct pci_attach_args *);
 #endif
 int	pci_probe_device(struct pci_softc *, pcitag_t tag,
 	    int (*)(const struct pci_attach_args *),
 	    struct pci_attach_args *);
 void	pci_devinfo(pcireg_t, pcireg_t, int, char *, size_t);
 void	pci_aprint_devinfo_fancy(const struct pci_attach_args *,
 				 const char *, const char *, int);
 #define pci_aprint_devinfo(pap, naive) \
 	pci_aprint_devinfo_fancy(pap, naive, NULL, 0);
 void	pci_conf_print(pci_chipset_tag_t, pcitag_t,
 	    void (*)(pci_chipset_tag_t, pcitag_t, const pcireg_t *));
 const struct pci_quirkdata *
 	pci_lookup_quirkdata(pci_vendor_id_t, pci_product_id_t);
 /*
  * Helper functions for user access to the PCI bus.
  */
 struct proc;
 int	pci_devioctl(pci_chipset_tag_t, pcitag_t, u_long, void *,
 	    int flag, struct lwp *);
 /*
  * Power Management (PCI 2.2)
  */
 #define PCI_PWR_D0	0
 #define PCI_PWR_D1	1
 #define PCI_PWR_D2	2
 #define PCI_PWR_D3	3
 int	pci_powerstate(pci_chipset_tag_t, pcitag_t, const int *, int *);
 /*
  * Vital Product Data (PCI 2.2)
  */
 int	pci_vpd_read(pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *);
 int	pci_vpd_write(pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *);
 /*
  * Misc.
  */
 int	pci_find_device(struct pci_attach_args *pa,
 			int (*match)(const struct pci_attach_args *));
 int	pci_dma64_available(const struct pci_attach_args *);
 void	pci_conf_capture(pci_chipset_tag_t, pcitag_t, struct pci_conf_state *);
 void	pci_conf_restore(pci_chipset_tag_t, pcitag_t, struct pci_conf_state *);
 int	pci_get_powerstate(pci_chipset_tag_t, pcitag_t, pcireg_t *);
 int	pci_set_powerstate(pci_chipset_tag_t, pcitag_t, pcireg_t);
 int	pci_activate(pci_chipset_tag_t, pcitag_t, device_t,
     int (*)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t));
 int	pci_activate_null(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t);
 int	pci_chipset_tag_create(pci_chipset_tag_t, uint64_t,
 	                       const struct pci_overrides *,
 	                       void *, pci_chipset_tag_t *);
 void	pci_chipset_tag_destroy(pci_chipset_tag_t);
 int	pci_bus_devorder(pci_chipset_tag_t, int, uint8_t *, int);
 void	*pci_intr_establish_xname(pci_chipset_tag_t, pci_intr_handle_t,
 				  int, int (*)(void *), void *, const char *);
 #ifndef __HAVE_PCI_MSI_MSIX
 typedef enum {
 	PCI_INTR_TYPE_INTX = 0,
 	PCI_INTR_TYPE_MSI,
 	PCI_INTR_TYPE_MSIX,
 	PCI_INTR_TYPE_SIZE,
 } pci_intr_type_t;
 pci_intr_type_t
 	pci_intr_type(pci_chipset_tag_t, pci_intr_handle_t);
 int	pci_intr_alloc(const struct pci_attach_args *, pci_intr_handle_t **,
 	    int *, pci_intr_type_t);
 void	pci_intr_release(pci_chipset_tag_t, pci_intr_handle_t *, int);
 int	pci_intx_alloc(const struct pci_attach_args *, pci_intr_handle_t **);
 int	pci_msi_alloc(const struct pci_attach_args *, pci_intr_handle_t **,
 	    int *);
 int	pci_msi_alloc_exact(const struct pci_attach_args *,
 	    pci_intr_handle_t **, int);
 int	pci_msix_alloc(const struct pci_attach_args *, pci_intr_handle_t **,
 	    int *);
 int	pci_msix_alloc_exact(const struct pci_attach_args *,
 	    pci_intr_handle_t **, int);
 int	pci_msix_alloc_map(const struct pci_attach_args *, pci_intr_handle_t **,
 	    u_int *, int);
 #endif
 /*
  * Device abstraction for inheritance by elanpci(4), for example.
  */
 int pcimatch(device_t, cfdata_t, void *);
 void pciattach(device_t, device_t, void *);
 int pcidetach(device_t, int);
 void pcidevdetached(device_t, device_t);
 int pcirescan(device_t, const char *, const int *);
 /*
  * Interrupts.
  */
 #define	PCI_INTR_MPSAFE		1
 int	pci_intr_setattr(pci_chipset_tag_t, pci_intr_handle_t *, int, uint64_t);
 /*
  * Local constants
  */
 #define PCI_INTRSTR_LEN			64
 #endif /* _KERNEL */
 #endif /* _DEV_PCI_PCIVAR_H_ */