 @@ -1,1244 +1,1242 @@
-/*	$NetBSD: pci_machdep.c,v 1.87 2020/05/04 15:55:56 jdolecek Exp $	*/
+/*	$NetBSD: pci_machdep.c,v 1.88 2021/01/28 01:57:31 jmcneill Exp $	*/
 /*-
  * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
  * NASA Ames Research Center.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Charles M. Hannum.
  * 4. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Machine-specific functions for PCI autoconfiguration.
+ *
  * On PCs, there are two methods of generating PCI configuration cycles.
  * We try to detect the appropriate mechanism for this machine and set
  * up a few function pointers to access the correct method directly.
+ *
  * The configuration method can be hard-coded in the config file by
  * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
  * as defined in section 3.6.4.1, `Generating Configuration Cycles'.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.87 2020/05/04 15:55:56 jdolecek Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.88 2021/01/28 01:57:31 jmcneill Exp $");
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/time.h>
 #include <sys/systm.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/kmem.h>
 #include <uvm/uvm_extern.h>
 #include <machine/bus_private.h>
 #include <machine/pio.h>
 #include <machine/lock.h>
 #include <dev/isa/isareg.h>
 #include <dev/isa/isavar.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pccbbreg.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/ppbvar.h>
 #include <dev/pci/genfb_pcivar.h>
 #include <dev/wsfb/genfbvar.h>
 #include <arch/x86/include/genfb_machdep.h>
 #include <dev/ic/vgareg.h>
 #include "acpica.h"
 #include "genfb.h"
 #include "isa.h"
 #include "opt_acpi.h"
 #include "opt_ddb.h"
 #include "opt_mpbios.h"
 #include "opt_puc.h"
 #include "opt_vga.h"
 #include "pci.h"
 #include "wsdisplay.h"
 #include "com.h"
 #ifdef DDB
 #include <machine/db_machdep.h>
 #include <ddb/db_sym.h>
 #include <ddb/db_extern.h>
 #endif
 #ifdef VGA_POST
 #include <x86/vga_post.h>
 #endif
 #include <x86/cpuvar.h>
 #include <machine/autoconf.h>
 #include <machine/bootinfo.h>
 #ifdef MPBIOS
 #include <machine/mpbiosvar.h>
 #endif
 #if NACPICA > 0
 #include <machine/mpacpi.h>
 #if !defined(NO_PCI_EXTENDED_CONFIG)
 #include <dev/acpi/acpivar.h>
 #include <dev/acpi/acpi_mcfg.h>
 #endif
 #endif
 #include <machine/mpconfig.h>
 #if NCOM > 0
 #include <dev/pci/puccn.h>
 #endif
 #ifndef XENPV
 #include <x86/efi.h>
 #endif
 #include "opt_pci_conf_mode.h"
 #ifdef PCI_CONF_MODE
 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2)
 static int pci_mode = PCI_CONF_MODE;
 #else
 #error Invalid PCI configuration mode.
 #endif
 #else
 static int pci_mode = -1;
 #endif
 struct pci_conf_lock {
 	uint32_t cl_cpuno;	/* 0: unlocked
 				 * 1 + n: locked by CPU n (0 <= n)
 				 */
 	uint32_t cl_sel;	/* the address that's being read. */
 };
 static void pci_conf_unlock(struct pci_conf_lock *);
 static uint32_t pci_conf_selector(pcitag_t, int);
 static unsigned int pci_conf_port(pcitag_t, int);
 static void pci_conf_select(uint32_t);
 static void pci_conf_lock(struct pci_conf_lock *, uint32_t);
 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *);
 struct pci_bridge_hook_arg {
 	void (*func)(pci_chipset_tag_t, pcitag_t, void *);
 	void *arg;
 };
 #define	PCI_MODE1_ENABLE	0x80000000UL
 #define	PCI_MODE1_ADDRESS_REG	0x0cf8
 #define	PCI_MODE1_DATA_REG	0x0cfc
 #define	PCI_MODE2_ENABLE_REG	0x0cf8
 #define	PCI_MODE2_FORWARD_REG	0x0cfa
 #define _tag(b, d, f) \
 	{.mode1 = PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)}
 #define _qe(bus, dev, fcn, vend, prod) \
 	{_tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)}
 const struct {
 	pcitag_t tag;
 	pcireg_t id;
 } pcim1_quirk_tbl[] = {
 	_qe(0, 0, 0, PCI_VENDOR_INVALID, 0x0000), /* patchable */
 	_qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1),
 	/* XXX Triflex2 not tested */
 	_qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2),
 	_qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4),
 #if 0
 	/* Triton needed for Connectix Virtual PC */
 	_qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX),
 	/* Connectix Virtual PC 5 has a 440BX */
 	_qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP),
 	/* Parallels Desktop for Mac */
 	_qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO),
 	_qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS),
 	/* SIS 740 */
 	_qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740),
 	/* SIS 741 */
 	_qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741),
 	/* VIA Technologies VX900 */
 	_qe(0, 0, 0, PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VX900_HB)
 #endif
 };
 #undef _tag
 #undef _qe
 /* arch/xen does not support MSI/MSI-X yet. */
 #ifdef __HAVE_PCI_MSI_MSIX
 #define PCI_QUIRK_DISABLE_MSI	1 /* Neigher MSI nor MSI-X work */
 #define PCI_QUIRK_DISABLE_MSIX	2 /* MSI-X does not work */
 #define PCI_QUIRK_ENABLE_MSI_VM	3 /* Older chipset in VM where MSI and MSI-X works */
 #define _dme(vend, prod) \
 	{ PCI_QUIRK_DISABLE_MSI, PCI_ID_CODE(vend, prod) }
 #define _dmxe(vend, prod) \
 	{ PCI_QUIRK_DISABLE_MSIX, PCI_ID_CODE(vend, prod) }
 #define _emve(vend, prod) \
 	{ PCI_QUIRK_ENABLE_MSI_VM, PCI_ID_CODE(vend, prod) }
 const struct {
 	int type;
 	pcireg_t id;
 } pci_msi_quirk_tbl[] = {
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCMC),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437MX),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437VX),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439HX),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82439TX),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_AGP),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_AGP),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443GX_NOAGP),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443LX_AGP),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810_MCH),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82810E_MCH),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82815_FULL_HUB),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82820_MCH),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82830MP_IO_1),
 	_dme(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82840_HB),
 	_dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_PCHB),
 	_dme(PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_PCHB),
 	_dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC751_SC),
 	_dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC761_SC),
 	_dme(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_SC762_NB),
 	_emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82441FX), /* QEMU */
 	_emve(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX), /* VMWare */
 };
 #undef _dme
 #undef _dmxe
 #undef _emve
 #endif /* __HAVE_PCI_MSI_MSIX */
 /*
  * PCI doesn't have any special needs; just use the generic versions
  * of these functions.
  */
 struct x86_bus_dma_tag pci_bus_dma_tag = {
 	._tag_needs_free	= 0,
 #if defined(_LP64) || defined(PAE)
 	._bounce_thresh		= PCI32_DMA_BOUNCE_THRESHOLD,
 	._bounce_alloc_lo	= ISA_DMA_BOUNCE_THRESHOLD,
 	._bounce_alloc_hi	= PCI32_DMA_BOUNCE_THRESHOLD,
 #else
 	._bounce_thresh		= 0,
 	._bounce_alloc_lo	= 0,
 	._bounce_alloc_hi	= 0,
 #endif
 	._may_bounce		= NULL,
 };
 #ifdef _LP64
 struct x86_bus_dma_tag pci_bus_dma64_tag = {
 	._tag_needs_free	= 0,
 	._bounce_thresh		= 0,
 	._bounce_alloc_lo	= 0,
 	._bounce_alloc_hi	= 0,
 	._may_bounce		= NULL,
 };
 #endif
 static struct pci_conf_lock cl0 = {
 	  .cl_cpuno = 0UL
 	, .cl_sel = 0UL
 };
 static struct pci_conf_lock * const cl = &cl0;
 #if NGENFB > 0 && NACPICA > 0 && defined(VGA_POST)
 extern int acpi_md_vbios_reset;
 extern int acpi_md_vesa_modenum;
 #endif
 static struct genfb_colormap_callback gfb_cb;
 static struct genfb_pmf_callback pmf_cb;
 static struct genfb_mode_callback mode_cb;
 #ifdef VGA_POST
 static struct vga_post *vga_posth = NULL;
 #endif
 static void
 pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel)
+{
 	uint32_t cpuno;
 	KASSERT(sel != 0);
 	kpreempt_disable();
 	cpuno = cpu_number() + 1;
 	/* If the kernel enters pci_conf_lock() through an interrupt
 	 * handler, then the CPU may already hold the lock.
+	 *
 	 * If the CPU does not already hold the lock, spin until
 	 * we can acquire it.
 	 */
 	if (cpuno == cl->cl_cpuno) {
 		ocl->cl_cpuno = cpuno;
 	} else {
 #ifdef LOCKDEBUG
 		u_int spins = 0;
 #endif
 		u_int count;
 		count = SPINLOCK_BACKOFF_MIN;
 		ocl->cl_cpuno = 0;
 		while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) {
 			SPINLOCK_BACKOFF(count);
 #ifdef LOCKDEBUG
 			if (SPINLOCK_SPINOUT(spins)) {
 				panic("%s: cpu %" PRId32
 				    " spun out waiting for cpu %" PRId32,
 				    __func__, cpuno, cl->cl_cpuno);
+			}
 #endif
+		}
+	}
 	/* Only one CPU can be here, so an interlocked atomic_swap(3)
 	 * is not necessary.
+	 *
 	 * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel,
 	 * and applying atomic_cas_32_ni() is not an atomic operation,
 	 * however, any interrupt that, in the middle of the
 	 * operation, modifies cl->cl_sel, will also restore
 	 * cl->cl_sel.  So cl->cl_sel will have the same value when
 	 * we apply atomic_cas_32_ni() as when we evaluated it,
 	 * before.
 	 */
 	ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel);
 	pci_conf_select(sel);
+}
 static void
 pci_conf_unlock(struct pci_conf_lock *ocl)
+{
 	atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel);
 	pci_conf_select(ocl->cl_sel);
 	if (ocl->cl_cpuno != cl->cl_cpuno)
 		atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno);
 	kpreempt_enable();
+}
 static uint32_t
 pci_conf_selector(pcitag_t tag, int reg)
+{
 	static const pcitag_t mode2_mask = {
 		.mode2 = {
 			  .enable = 0xff
 			, .forward = 0xff
+		}
 	};
 	switch (pci_mode) {
 	case 1:
 		return tag.mode1 | reg;
 	case 2:
 		return tag.mode1 & mode2_mask.mode1;
 	default:
 		panic("%s: mode %d not configured", __func__, pci_mode);
+	}
+}
 static unsigned int
 pci_conf_port(pcitag_t tag, int reg)
+{
 	switch (pci_mode) {
 	case 1:
 		return PCI_MODE1_DATA_REG;
 	case 2:
 		return tag.mode2.port | reg;
 	default:
 		panic("%s: mode %d not configured", __func__, pci_mode);
+	}
+}
 static void
 pci_conf_select(uint32_t sel)
+{
 	pcitag_t tag;
 	switch (pci_mode) {
 	case 1:
 		outl(PCI_MODE1_ADDRESS_REG, sel);
 		return;
 	case 2:
 		tag.mode1 = sel;
 		outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
 		if (tag.mode2.enable != 0)
 			outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
 		return;
 	default:
 		panic("%s: mode %d not configured", __func__, pci_mode);
+	}
+}
 static int
 pci_mode_check(void)
+{
 	pcireg_t x;
 	pcitag_t t;
 	int device;
 	const int maxdev = pci_bus_maxdevs(NULL, 0);
 	for (device = 0; device < maxdev; device++) {
 		t = pci_make_tag(NULL, 0, device, 0);
 		x = pci_conf_read(NULL, t, PCI_CLASS_REG);
 		if (PCI_CLASS(x) == PCI_CLASS_BRIDGE &&
 		    PCI_SUBCLASS(x) == PCI_SUBCLASS_BRIDGE_HOST)
 			return 0;
 		x = pci_conf_read(NULL, t, PCI_ID_REG);
 		switch (PCI_VENDOR(x)) {
 		case PCI_VENDOR_COMPAQ:
 		case PCI_VENDOR_INTEL:
 		case PCI_VENDOR_VIATECH:
 			return 0;
+		}
+	}
 	return -1;
+}
 #ifdef __HAVE_PCI_MSI_MSIX
 static int
 pci_has_msi_quirk(pcireg_t id, int type)
+{
 	int i;
 	for (i = 0; i < __arraycount(pci_msi_quirk_tbl); i++) {
 		if (id == pci_msi_quirk_tbl[i].id &&
 		    type == pci_msi_quirk_tbl[i].type)
 			return 1;
+	}
 	return 0;
+}
 #endif
 void
 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba)
+{
 #ifdef __HAVE_PCI_MSI_MSIX
 	pci_chipset_tag_t pc = pba->pba_pc;
 	pcitag_t tag;
 	pcireg_t id, class;
 #endif
 	if (pba->pba_bus == 0)
 		aprint_normal(": configuration mode %d", pci_mode);
 #ifdef MPBIOS
 	mpbios_pci_attach_hook(parent, self, pba);
 #endif
 #if NACPICA > 0
 	mpacpi_pci_attach_hook(parent, self, pba);
 #endif
 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG)
 	acpimcfg_map_bus(self, pba->pba_pc, pba->pba_bus);
 #endif
 #ifdef __HAVE_PCI_MSI_MSIX
 	/*
 	 * In order to decide whether the system supports MSI we look
 	 * at the host bridge, which should be device 0 function 0 on
 	 * bus 0.  It is better to not enable MSI on systems that
 	 * support it than the other way around, so be conservative
 	 * here.  So we don't enable MSI if we don't find a host
 	 * bridge there.  We also deliberately don't enable MSI on
 	 * chipsets from low-end manifacturers like VIA and SiS.
 	 */
 	tag = pci_make_tag(pc, 0, 0, 0);
 	id = pci_conf_read(pc, tag, PCI_ID_REG);
 	class = pci_conf_read(pc, tag, PCI_CLASS_REG);
 	if (PCI_CLASS(class) != PCI_CLASS_BRIDGE ||
 	    PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST)
 		return;
 	/* VMware and KVM use old chipset, but they can use MSI/MSI-X */
 	if ((cpu_feature[1] & CPUID2_RAZ)
 	    && (pci_has_msi_quirk(id, PCI_QUIRK_ENABLE_MSI_VM))) {
 			pba->pba_flags |= PCI_FLAGS_MSI_OKAY;
 			pba->pba_flags |= PCI_FLAGS_MSIX_OKAY;
 	} else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSI)) {
 		pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY;
 		pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY;
 		aprint_verbose("\n");
 		aprint_verbose_dev(self,
 		    "This pci host supports neither MSI nor MSI-X.");
 	} else if (pci_has_msi_quirk(id, PCI_QUIRK_DISABLE_MSIX)) {
 		pba->pba_flags |= PCI_FLAGS_MSI_OKAY;
 		pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY;
 		aprint_verbose("\n");
 		aprint_verbose_dev(self,
 		    "This pci host does not support MSI-X.");
 	} else {
 		pba->pba_flags |= PCI_FLAGS_MSI_OKAY;
 		pba->pba_flags |= PCI_FLAGS_MSIX_OKAY;
+	}
 	/*
 	 * Don't enable MSI on a HyperTransport bus.  In order to
 	 * determine that bus 0 is a HyperTransport bus, we look at
 	 * device 24 function 0, which is the HyperTransport
 	 * host/primary interface integrated on most 64-bit AMD CPUs.
 	 * If that device has a HyperTransport capability, bus 0 must
 	 * be a HyperTransport bus and we disable MSI.
 	 */
 	if (24 < pci_bus_maxdevs(pc, 0)) {
 		tag = pci_make_tag(pc, 0, 24, 0);
 		if (pci_get_capability(pc, tag, PCI_CAP_LDT, NULL, NULL)) {
 			pba->pba_flags &= ~PCI_FLAGS_MSI_OKAY;
 			pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY;
+		}
+	}
 #ifdef XENPV
 	/*
 	 * XXX MSI-X doesn't work for XenPV yet - setup seems to be correct,
 	 * XXX but no interrupts are actually delivered.
 	 */
 	pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY;
 #endif
 #endif /* __HAVE_PCI_MSI_MSIX */
+}
 int
 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
+{
 	/*
 	 * Bus number is irrelevant.  If Configuration Mechanism 2 is in
 	 * use, can only have devices 0-15 on any bus.  If Configuration
 	 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal'
 	 * range).
 	 */
 	if (pci_mode == 2)
 		return (16);
 	else
 		return (32);
+}
 pcitag_t
 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
+{
 	pci_chipset_tag_t ipc;
 	pcitag_t tag;
 	for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
 		if ((ipc->pc_present & PCI_OVERRIDE_MAKE_TAG) == 0)
 			continue;
 		return (*ipc->pc_ov->ov_make_tag)(ipc->pc_ctx,
 		    pc, bus, device, function);
+	}
 	switch (pci_mode) {
 	case 1:
 		if (bus >= 256 || device >= 32 || function >= 8)
 			panic("%s: bad request(%d, %d, %d)", __func__,
 			    bus, device, function);
 		tag.mode1 = PCI_MODE1_ENABLE |
 			    (bus << 16) | (device << 11) | (function << 8);
 		return tag;
 	case 2:
 		if (bus >= 256 || device >= 16 || function >= 8)
 			panic("%s: bad request(%d, %d, %d)", __func__,
 			    bus, device, function);
 		tag.mode2.port = 0xc000 | (device << 8);
 		tag.mode2.enable = 0xf0 | (function << 1);
 		tag.mode2.forward = bus;
 		return tag;
 	default:
 		panic("%s: mode %d not configured", __func__, pci_mode);
+	}
+}
 void
 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag,
     int *bp, int *dp, int *fp)
+{
 	pci_chipset_tag_t ipc;
 	for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
 		if ((ipc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) == 0)
 			continue;
 		(*ipc->pc_ov->ov_decompose_tag)(ipc->pc_ctx,
 		    pc, tag, bp, dp, fp);
 		return;
+	}
 	switch (pci_mode) {
 	case 1:
 		if (bp != NULL)
 			*bp = (tag.mode1 >> 16) & 0xff;
 		if (dp != NULL)
 			*dp = (tag.mode1 >> 11) & 0x1f;
 		if (fp != NULL)
 			*fp = (tag.mode1 >> 8) & 0x7;
 		return;
 	case 2:
 		if (bp != NULL)
 			*bp = tag.mode2.forward & 0xff;
 		if (dp != NULL)
 			*dp = (tag.mode2.port >> 8) & 0xf;
 		if (fp != NULL)
 			*fp = (tag.mode2.enable >> 1) & 0x7;
 		return;
 	default:
 		panic("%s: mode %d not configured", __func__, pci_mode);
+	}
+}
 pcireg_t
 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
+{
 	pci_chipset_tag_t ipc;
 	pcireg_t data;
 	struct pci_conf_lock ocl;
 	int dev;
 	KASSERT((reg & 0x3) == 0);
 	for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
 		if ((ipc->pc_present & PCI_OVERRIDE_CONF_READ) == 0)
 			continue;
 		return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg);
+	}
 	pci_decompose_tag(pc, tag, NULL, &dev, NULL);
 	if (__predict_false(pci_mode == 2 && dev >= 16))
 		return (pcireg_t) -1;
 	if (reg < 0)
 		return (pcireg_t) -1;
 	if (reg >= PCI_CONF_SIZE) {
 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG)
 		if (reg >= PCI_EXTCONF_SIZE)
 			return (pcireg_t) -1;
 		acpimcfg_conf_read(pc, tag, reg, &data);
 		return data;
 #else
 		return (pcireg_t) -1;
 #endif
+	}
 	pci_conf_lock(&ocl, pci_conf_selector(tag, reg));
 	data = inl(pci_conf_port(tag, reg));
 	pci_conf_unlock(&ocl);
 	return data;
+}
 void
 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
+{
 	pci_chipset_tag_t ipc;
 	struct pci_conf_lock ocl;
 	int dev;
 	KASSERT((reg & 0x3) == 0);
 	for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
 		if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0)
 			continue;
 		(*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg,
 		    data);
 		return;
+	}
 	pci_decompose_tag(pc, tag, NULL, &dev, NULL);
 	if (__predict_false(pci_mode == 2 && dev >= 16)) {
 		return;
+	}
 	if (reg < 0)
 		return;
 	if (reg >= PCI_CONF_SIZE) {
 #if NACPICA > 0 && !defined(NO_PCI_EXTENDED_CONFIG)
 		if (reg >= PCI_EXTCONF_SIZE)
 			return;
 		acpimcfg_conf_write(pc, tag, reg, data);
 #endif
 		return;
+	}
 	pci_conf_lock(&ocl, pci_conf_selector(tag, reg));
 	outl(pci_conf_port(tag, reg), data);
 	pci_conf_unlock(&ocl);
+}
 void
 pci_mode_set(int mode)
+{
 	KASSERT(pci_mode == -1 || pci_mode == mode);
 	pci_mode = mode;
+}
 int
 pci_mode_detect(void)
+{
 	uint32_t sav, val;
 	int i;
 	pcireg_t idreg;
 	if (pci_mode != -1)
 		return pci_mode;
 	/*
 	 * We try to divine which configuration mode the host bridge wants.
 	 */
 	sav = inl(PCI_MODE1_ADDRESS_REG);
 	pci_mode = 1; /* assume this for now */
 	/*
 	 * catch some known buggy implementations of mode 1
 	 */
 	for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) {
 		pcitag_t t;
 		if (PCI_VENDOR(pcim1_quirk_tbl[i].id) == PCI_VENDOR_INVALID)
 			continue;
 		t.mode1 = pcim1_quirk_tbl[i].tag.mode1;
 		idreg = pci_conf_read(NULL, t, PCI_ID_REG); /* needs "pci_mode" */
 		if (idreg == pcim1_quirk_tbl[i].id) {
 #ifdef DEBUG
 			printf("%s: known mode 1 PCI chipset (%08x)\n",
 			    __func__, idreg);
 #endif
 			return (pci_mode);
+		}
+	}
 #if 0
 	extern char cpu_brand_string[];
 	const char *reason, *system_vendor, *system_product;
 	if (memcmp(cpu_brand_string, "QEMU", 4) == 0)
 		/* PR 45671, https://bugs.launchpad.net/qemu/+bug/897771 */
 		reason = "QEMU";
 	else if ((system_vendor = pmf_get_platform("system-vendor")) != NULL &&
 	    strcmp(system_vendor, "Xen") == 0 &&
 	    (system_product = pmf_get_platform("system-product")) != NULL &&
 	    strcmp(system_product, "HVM domU") == 0)
 		reason = "Xen";
 	else
 		reason = NULL;
 	if (reason) {
 #ifdef DEBUG
 		printf("%s: forcing PCI mode 1 for %s\n", __func__, reason);
 #endif
 		return (pci_mode);
+	}
 #endif
 	/*
 	 * Strong check for standard compliant mode 1:
 	 * 1. bit 31 ("enable") can be set
 	 * 2. byte/word access does not affect register
 	 */
 	outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE);
 	outb(PCI_MODE1_ADDRESS_REG + 3, 0);
 	outw(PCI_MODE1_ADDRESS_REG + 2, 0);
 	val = inl(PCI_MODE1_ADDRESS_REG);
 	if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) {
 #ifdef DEBUG
 		printf("%s: mode 1 enable failed (%x)\n", __func__, val);
 #endif
 		/* Try out mode 1 to see if we can find a host bridge. */
 		if (pci_mode_check() == 0) {
 #ifdef DEBUG
 			printf("%s: mode 1 functional, using\n", __func__);
 #endif
 			return (pci_mode);
+		}
 		goto not1;
+	}
 	outl(PCI_MODE1_ADDRESS_REG, 0);
 	val = inl(PCI_MODE1_ADDRESS_REG);
 	if ((val & 0x80fffffc) != 0)
 		goto not1;
 	return (pci_mode);
 not1:
 	outl(PCI_MODE1_ADDRESS_REG, sav);
 	/*
 	 * This mode 2 check is quite weak (and known to give false
 	 * positives on some Compaq machines).
 	 * However, this doesn't matter, because this is the
 	 * last test, and simply no PCI devices will be found if
 	 * this happens.
 	 */
 	outb(PCI_MODE2_ENABLE_REG, 0);
 	outb(PCI_MODE2_FORWARD_REG, 0);
 	if (inb(PCI_MODE2_ENABLE_REG) != 0 ||
 	    inb(PCI_MODE2_FORWARD_REG) != 0)
 		goto not2;
 	return (pci_mode = 2);
 not2:
 	return (pci_mode = 0);
+}
 void
 pci_device_foreach(pci_chipset_tag_t pc, int maxbus,
 	void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context)
+{
 	pci_device_foreach_min(pc, 0, maxbus, func, context);
+}
 void
 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus,
 	void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context)
+{
 	const struct pci_quirkdata *qd;
 	int bus, device, function, maxdevs, nfuncs;
 	pcireg_t id, bhlcr;
 	pcitag_t tag;
 	for (bus = minbus; bus <= maxbus; bus++) {
 		maxdevs = pci_bus_maxdevs(pc, bus);
 		for (device = 0; device < maxdevs; device++) {
 			tag = pci_make_tag(pc, bus, device, 0);
 			id = pci_conf_read(pc, tag, PCI_ID_REG);
 			/* Invalid vendor ID value? */
 			if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
 				continue;
 			/* XXX Not invalid, but we've done this ~forever. */
 			if (PCI_VENDOR(id) == 0)
 				continue;
 			qd = pci_lookup_quirkdata(PCI_VENDOR(id),
 				PCI_PRODUCT(id));
 			bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG);
 			if (PCI_HDRTYPE_MULTIFN(bhlcr) ||
 			     (qd != NULL &&
 			     (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0))
 				nfuncs = 8;
 			else
 				nfuncs = 1;
 			for (function = 0; function < nfuncs; function++) {
 				tag = pci_make_tag(pc, bus, device, function);
 				id = pci_conf_read(pc, tag, PCI_ID_REG);
 				/* Invalid vendor ID value? */
 				if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
 					continue;
 				/*
 				 * XXX Not invalid, but we've done this
 				 * ~forever.
 				 */
 				if (PCI_VENDOR(id) == 0)
 					continue;
 				(*func)(pc, tag, context);
+			}
+		}
+	}
+}
 void
 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus,
 	void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx)
+{
 	struct pci_bridge_hook_arg bridge_hook;
 	bridge_hook.func = func;
 	bridge_hook.arg = ctx;
 	pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook,
 		&bridge_hook);
+}
 static void
 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx)
+{
 	struct pci_bridge_hook_arg *bridge_hook = (void *)ctx;
 	pcireg_t reg;
 	reg = pci_conf_read(pc, tag, PCI_CLASS_REG);
 	if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&
 	    (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI ||
 		PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) {
 		(*bridge_hook->func)(pc, tag, bridge_hook->arg);
+	}
+}
 static const void *
 bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit)
+{
 	switch (bit) {
 	case PCI_OVERRIDE_CONF_READ:
 		return ov->ov_conf_read;
 	case PCI_OVERRIDE_CONF_WRITE:
 		return ov->ov_conf_write;
 	case PCI_OVERRIDE_INTR_MAP:
 		return ov->ov_intr_map;
 	case PCI_OVERRIDE_INTR_STRING:
 		return ov->ov_intr_string;
 	case PCI_OVERRIDE_INTR_EVCNT:
 		return ov->ov_intr_evcnt;
 	case PCI_OVERRIDE_INTR_ESTABLISH:
 		return ov->ov_intr_establish;
 	case PCI_OVERRIDE_INTR_DISESTABLISH:
 		return ov->ov_intr_disestablish;
 	case PCI_OVERRIDE_MAKE_TAG:
 		return ov->ov_make_tag;
 	case PCI_OVERRIDE_DECOMPOSE_TAG:
 		return ov->ov_decompose_tag;
 	default:
 		return NULL;
+	}
+}
 void
 pci_chipset_tag_destroy(pci_chipset_tag_t pc)
+{
 	kmem_free(pc, sizeof(struct pci_chipset_tag));
+}
 int
 pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present,
     const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp)
+{
 	uint64_t bit, bits, nbits;
 	pci_chipset_tag_t pc;
 	const void *fp;
 	if (ov == NULL || present == 0)
 		return EINVAL;
 	pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP);
 	pc->pc_super = opc;
 	for (bits = present; bits != 0; bits = nbits) {
 		nbits = bits & (bits - 1);
 		bit = nbits ^ bits;
 		if ((fp = bit_to_function_pointer(ov, bit)) == NULL) {
 #ifdef DEBUG
 			printf("%s: missing bit %" PRIx64 "\n", __func__, bit);
 #endif
 			goto einval;
+		}
+	}
 	pc->pc_ov = ov;
 	pc->pc_present = present;
 	pc->pc_ctx = ctx;
 	*pcp = pc;
 	return 0;
 einval:
 	kmem_free(pc, sizeof(struct pci_chipset_tag));
 	return EINVAL;
+}
 static void
 x86_genfb_set_mapreg(void *opaque, int index, int r, int g, int b)
+{
 	outb(IO_VGA + VGA_DAC_ADDRW, index);
 	outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)r >> 2);
 	outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)g >> 2);
 	outb(IO_VGA + VGA_DAC_PALETTE, (uint8_t)b >> 2);
+}
 static bool
 x86_genfb_setmode(struct genfb_softc *sc, int newmode)
+{
 #if NGENFB > 0
 # if NACPICA > 0 && defined(VGA_POST)
 	static int curmode = WSDISPLAYIO_MODE_EMUL;
 # endif
 	switch (newmode) {
 	case WSDISPLAYIO_MODE_EMUL:
 		x86_genfb_mtrr_init(sc->sc_fboffset,
 		    sc->sc_height * sc->sc_stride);
 # if NACPICA > 0 && defined(VGA_POST)
 		if (curmode != newmode) {
 			if (vga_posth != NULL && acpi_md_vesa_modenum != 0) {
 				vga_post_set_vbe(vga_posth,
 				    acpi_md_vesa_modenum);
+			}
+		}
 # endif
 		break;
+	}
 # if NACPICA > 0 && defined(VGA_POST)
 	curmode = newmode;
 # endif
 #endif
 	return true;
+}
 static bool
 x86_genfb_suspend(device_t dev, const pmf_qual_t *qual)
+{
 	return true;
+}
 static bool
 x86_genfb_resume(device_t dev, const pmf_qual_t *qual)
+{
 #if NGENFB > 0
 	struct pci_genfb_softc *psc = device_private(dev);
 #if NACPICA > 0 && defined(VGA_POST)
 	if (vga_posth != NULL && acpi_md_vbios_reset == 2) {
 		vga_post_call(vga_posth);
 		if (acpi_md_vesa_modenum != 0)
 			vga_post_set_vbe(vga_posth, acpi_md_vesa_modenum);
+	}
 #endif
 	genfb_restore_palette(&psc->sc_gen);
 #endif
 	return true;
+}
 static void
 populate_fbinfo(device_t dev, prop_dictionary_t dict)
+{
 #if NWSDISPLAY > 0 && NGENFB > 0
 	extern struct vcons_screen x86_genfb_console_screen;
 	struct rasops_info *ri = &x86_genfb_console_screen.scr_ri;
 #endif
 	const void *fbptr = lookup_bootinfo(BTINFO_FRAMEBUFFER);
 	struct btinfo_framebuffer fbinfo;
 	if (fbptr == NULL)
 		return;
 	memcpy(&fbinfo, fbptr, sizeof(fbinfo));
 	if (fbinfo.physaddr != 0) {
 		prop_dictionary_set_uint32(dict, "width", fbinfo.width);
 		prop_dictionary_set_uint32(dict, "height", fbinfo.height);
 		prop_dictionary_set_uint8(dict, "depth", fbinfo.depth);
 		prop_dictionary_set_uint16(dict, "linebytes", fbinfo.stride);
 		prop_dictionary_set_uint64(dict, "address", fbinfo.physaddr);
 #if NWSDISPLAY > 0 && NGENFB > 0
 		if (ri->ri_bits != NULL) {
 			prop_dictionary_set_uint64(dict, "virtual_address",
 			    ri->ri_hwbits != NULL ?
 			    (vaddr_t)ri->ri_hworigbits :
 			    (vaddr_t)ri->ri_origbits);
+		}
 #endif
+	}
 #if notyet
 	prop_dictionary_set_bool(dict, "splash",
 	    (fbinfo.flags & BI_FB_SPLASH) != 0);
 #endif
 	if (fbinfo.depth == 8) {
 		gfb_cb.gcc_cookie = NULL;
 		gfb_cb.gcc_set_mapreg = x86_genfb_set_mapreg;
 		prop_dictionary_set_uint64(dict, "cmap_callback",
 		    (uint64_t)(uintptr_t)&gfb_cb);
+	}
 	if (fbinfo.physaddr != 0) {
 		mode_cb.gmc_setmode = x86_genfb_setmode;
 		prop_dictionary_set_uint64(dict, "mode_callback",
 		    (uint64_t)(uintptr_t)&mode_cb);
+	}
 #if NWSDISPLAY > 0 && NGENFB > 0
 	if (device_is_a(dev, "genfb")) {
 		prop_dictionary_set_bool(dict, "enable_shadowfb",
 		    ri->ri_hwbits != NULL);
 		x86_genfb_set_console_dev(dev);
 #ifdef DDB
 		db_trap_callback = x86_genfb_ddb_trap_callback;
 #endif
+	}
 #endif
+}
 device_t
 device_pci_register(device_t dev, void *aux)
+{
 	device_t parent = device_parent(dev);
 	device_pci_props_register(dev, aux);
 	/*
 	 * Handle network interfaces here, the attachment information is
 	 * not available driver-independently later.
+	 *
 	 * For disks, there is nothing useful available at attach time.
 	 */
 	if (device_class(dev) == DV_IFNET) {
 		struct btinfo_netif *bin = lookup_bootinfo(BTINFO_NETIF);
 		if (bin == NULL)
 			return NULL;
 		/*
 		 * We don't check the driver name against the device name
 		 * passed by the boot ROM.  The ROM should stay usable if
 		 * the driver becomes obsolete.  The physical attachment
 		 * information (checked below) must be sufficient to
 		 * identify the device.
 		 */
 		if (bin->bus == BI_BUS_PCI && device_is_a(parent, "pci")) {
 			struct pci_attach_args *paa = aux;
 			int b, d, f;
 			/*
 			 * Calculate BIOS representation of:
+			 *
 			 *	<bus,device,function>
+			 *
 			 * and compare.
 			 */
 			pci_decompose_tag(paa->pa_pc, paa->pa_tag, &b, &d, &f);
 			if (bin->addr.tag == ((b << 8) | (d << 3) | f))
 				return dev;
 #ifndef XENPV
 			/*
 			 * efiboot reports parent ppb bus/device/function.
 			 */
 			device_t grand = device_parent(parent);
 			if (efi_probe() && grand && device_is_a(grand, "ppb")) {
 				struct ppb_softc *ppb_sc = device_private(grand);
 				pci_decompose_tag(ppb_sc->sc_pc, ppb_sc->sc_tag,
 				    &b, &d, &f);
 				if (bin->addr.tag == ((b << 8) | (d << 3) | f))
 					return dev;
+			}
 #endif
+		}
+	}
 	if (parent && device_is_a(parent, "pci") &&
 	    x86_found_console == false) {
 		struct pci_attach_args *pa = aux;
 		if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) {
 			prop_dictionary_t dict = device_properties(dev);
 			/*
 			 * framebuffer drivers other than genfb can work
 			 * without the address property
 			 */
 			populate_fbinfo(dev, dict);
 #if 1 && NWSDISPLAY > 0 && NGENFB > 0
 			/* XXX */
 			if (device_is_a(dev, "genfb")) {
 				prop_dictionary_set_bool(dict, "is_console",
 				    genfb_is_console());
 			} else
 #endif
 			prop_dictionary_set_bool(dict, "is_console", true);
 			prop_dictionary_set_bool(dict, "clear-screen", false);
 #if NWSDISPLAY > 0 && NGENFB > 0
 			extern struct vcons_screen x86_genfb_console_screen;
 			prop_dictionary_set_uint16(dict, "cursor-row",
 			    x86_genfb_console_screen.scr_ri.ri_crow);
 #endif
 #if notyet
 			prop_dictionary_set_bool(dict, "splash",
 			    (fbinfo->flags & BI_FB_SPLASH) != 0);
 #endif
 			pmf_cb.gpc_suspend = x86_genfb_suspend;
 			pmf_cb.gpc_resume = x86_genfb_resume;
 			prop_dictionary_set_uint64(dict,
 			    "pmf_callback", (uint64_t)(uintptr_t)&pmf_cb);
 #ifdef VGA_POST
 			vga_posth = vga_post_init(pa->pa_bus, pa->pa_device,
 			    pa->pa_function);
 #endif
 			x86_found_console = true;
 			return NULL;
+		}
+	}
 	return NULL;
+}
 #ifndef PUC_CNBUS
 #define PUC_CNBUS 0
 #endif
 #if NCOM > 0
 int
 cpu_puc_cnprobe(struct consdev *cn, struct pci_attach_args *pa)
+{
 	pci_mode_detect();
 	pa->pa_iot = x86_bus_space_io;
 	pa->pa_memt = x86_bus_space_mem;
 	pa->pa_pc = 0;
 	pa->pa_tag = pci_make_tag(0, PUC_CNBUS, pci_bus_maxdevs(NULL, 0) - 1,
 );
 	return 0;
+}
 #endif

 @@ -1,1197 +1,1189 @@
-/*	$NetBSD: hyperv.c,v 1.12 2020/10/12 12:11:03 ryoon Exp $	*/
+/*	$NetBSD: hyperv.c,v 1.13 2021/01/28 01:57:31 jmcneill Exp $	*/
 /*-
  * Copyright (c) 2009-2012,2016-2017 Microsoft Corp.
  * Copyright (c) 2012 NetApp Inc.
  * Copyright (c) 2012 Citrix Inc.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice unmodified, this list of conditions, and the following
  *    disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /**
  * Implements low-level interactions with Hyper-V/Azure
  */
 #include <sys/cdefs.h>
 #ifdef __KERNEL_RCSID
-__KERNEL_RCSID(0, "$NetBSD: hyperv.c,v 1.12 2020/10/12 12:11:03 ryoon Exp $");
+__KERNEL_RCSID(0, "$NetBSD: hyperv.c,v 1.13 2021/01/28 01:57:31 jmcneill Exp $");
 #endif
 #ifdef __FBSDID
 __FBSDID("$FreeBSD: head/sys/dev/hyperv/vmbus/hyperv.c 331757 2018-03-30 02:25:12Z emaste $");
 #endif
 #ifdef _KERNEL_OPT
 #include "lapic.h"
 #include "genfb.h"
 #include "opt_ddb.h"
 #include "vmbus.h"
 #include "wsdisplay.h"
 #endif
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/kmem.h>
 #include <sys/module.h>
 #include <sys/pmf.h>
 #include <sys/sysctl.h>
 #include <sys/timetc.h>
 #include <uvm/uvm_extern.h>
 #include <machine/autoconf.h>
 #include <machine/bootinfo.h>
 #include <machine/cpufunc.h>
 #include <machine/cputypes.h>
 #include <machine/cpuvar.h>
 #include <machine/cpu_counter.h>
 #include <x86/apicvar.h>
 #include <x86/efi.h>
 #include <dev/wsfb/genfbvar.h>
 #include <x86/genfb_machdep.h>
 #include <x86/x86/hypervreg.h>
 #include <x86/x86/hypervvar.h>
 #include <dev/hyperv/vmbusvar.h>
 #include <dev/hyperv/genfb_vmbusvar.h>
 #ifdef DDB
 #include <machine/db_machdep.h>
 #include <ddb/db_sym.h>
 #include <ddb/db_extern.h>
 #endif
 struct hyperv_softc {
 	device_t		sc_dev;
 	struct sysctllog	*sc_log;
 };
 struct hyperv_hypercall_ctx {
 	void		*hc_addr;
 	paddr_t		hc_paddr;
 };
 struct hyperv_percpu_data {
 	int	pd_idtvec;
 };
 static struct hyperv_hypercall_ctx hyperv_hypercall_ctx;
 static char hyperv_hypercall_page[PAGE_SIZE]
     __section(".text") __aligned(PAGE_SIZE) = { 0xcc };
 static u_int	hyperv_get_timecount(struct timecounter *);
 static u_int hyperv_ver_major;
 static u_int hyperv_features;		/* CPUID_HV_MSR_ */
 static u_int hyperv_recommends;
 static u_int hyperv_pm_features;
 static u_int hyperv_features3;
 static char hyperv_version_str[64];
 static char hyperv_features_str[256];
 static char hyperv_pm_features_str[256];
 static char hyperv_features3_str[256];
 uint32_t hyperv_vcpuid[MAXCPUS];
 static struct timecounter hyperv_timecounter = {
 	.tc_get_timecount = hyperv_get_timecount,
 	.tc_counter_mask = 0xffffffff,
 	.tc_frequency = HYPERV_TIMER_FREQ,
 	.tc_name = "Hyper-V",
 	.tc_quality = 2000,
 };
 static void	hyperv_proc_dummy(void *, struct cpu_info *);
 struct hyperv_proc {
 	hyperv_proc_t	func;
 	void		*arg;
 };
 static struct hyperv_proc hyperv_event_proc = {
 	.func = hyperv_proc_dummy,
 };
 static struct hyperv_proc hyperv_message_proc = {
 	.func = hyperv_proc_dummy,
 };
 static int	hyperv_match(device_t, cfdata_t, void *);
 static void	hyperv_attach(device_t, device_t, void *);
 static int	hyperv_detach(device_t, int);
 CFATTACH_DECL_NEW(hyperv, sizeof(struct hyperv_softc),
     hyperv_match, hyperv_attach, hyperv_detach, NULL);
 static void	hyperv_hypercall_memfree(void);
 static bool	hyperv_init_hypercall(void);
 static int	hyperv_sysctl_setup_root(struct hyperv_softc *);
 static u_int
 hyperv_get_timecount(struct timecounter *tc)
+{
 	return (u_int)rdmsr(MSR_HV_TIME_REF_COUNT);
+}
 static uint64_t
 hyperv_tc64_rdmsr(void)
+{
 	return rdmsr(MSR_HV_TIME_REF_COUNT);
+}
 #ifdef __amd64__
 /*
  * Reference TSC
  */
 struct hyperv_ref_tsc {
 	struct hyperv_reftsc	*tsc_ref;
 	paddr_t			tsc_paddr;
 };
 static struct hyperv_ref_tsc hyperv_ref_tsc;
 static u_int	hyperv_tsc_timecount(struct timecounter *);
 static struct timecounter hyperv_tsc_timecounter = {
 	.tc_get_timecount = hyperv_tsc_timecount,
 	.tc_counter_mask = 0xffffffff,
 	.tc_frequency = HYPERV_TIMER_FREQ,
 	.tc_name = "Hyper-V-TSC",
 	.tc_quality = 3000,
 };
 static __inline u_int
 atomic_load_acq_int(volatile u_int *p)
+{
 	u_int r = *p;
 	__insn_barrier();
 	return r;
+}
 static uint64_t
 hyperv_tc64_tsc(void)
+{
 	struct hyperv_reftsc *tsc_ref = hyperv_ref_tsc.tsc_ref;
 	uint32_t seq;
 	while ((seq = atomic_load_acq_int(&tsc_ref->tsc_seq)) != 0) {
 		uint64_t disc, ret, tsc;
 		uint64_t scale = tsc_ref->tsc_scale;
 		int64_t ofs = tsc_ref->tsc_ofs;
 		tsc = cpu_counter();
 		/* ret = ((tsc * scale) >> 64) + ofs */
 		__asm__ __volatile__ ("mulq %3" :
 		    "=d" (ret), "=a" (disc) :
 		    "a" (tsc), "r" (scale));
 		ret += ofs;
 		__insn_barrier();
 		if (tsc_ref->tsc_seq == seq)
 			return ret;
 		/* Sequence changed; re-sync. */
+	}
 	/* Fallback to the generic timecounter, i.e. rdmsr. */
 	return rdmsr(MSR_HV_TIME_REF_COUNT);
+}
 static u_int
 hyperv_tsc_timecount(struct timecounter *tc __unused)
+{
 	return hyperv_tc64_tsc();
+}
 static bool
 hyperv_tsc_tcinit(void)
+{
 	uint64_t orig_msr, msr;
 	if ((hyperv_features &
 	     (CPUID_HV_MSR_TIME_REFCNT | CPUID_HV_MSR_REFERENCE_TSC)) !=
 	    (CPUID_HV_MSR_TIME_REFCNT | CPUID_HV_MSR_REFERENCE_TSC) ||
 	    (cpu_feature[0] & CPUID_SSE2) == 0)	/* SSE2 for mfence/lfence */
 		return false;
 	hyperv_ref_tsc.tsc_ref = (void *)uvm_km_alloc(kernel_map,
 	    PAGE_SIZE, PAGE_SIZE, UVM_KMF_WIRED | UVM_KMF_ZERO);
 	if (hyperv_ref_tsc.tsc_ref == NULL) {
 		aprint_error("Hyper-V: reference TSC page allocation failed\n");
 		return false;
+	}
 	if (!pmap_extract(pmap_kernel(), (vaddr_t)hyperv_ref_tsc.tsc_ref,
 	    &hyperv_ref_tsc.tsc_paddr)) {
 		aprint_error("Hyper-V: reference TSC page setup failed\n");
 		uvm_km_free(kernel_map, (vaddr_t)hyperv_ref_tsc.tsc_ref,
 		    PAGE_SIZE, UVM_KMF_WIRED);
 		hyperv_ref_tsc.tsc_ref = NULL;
 		return false;
+	}
 	orig_msr = rdmsr(MSR_HV_REFERENCE_TSC);
 	msr = MSR_HV_REFTSC_ENABLE | (orig_msr & MSR_HV_REFTSC_RSVD_MASK) |
 	    (atop(hyperv_ref_tsc.tsc_paddr) << MSR_HV_REFTSC_PGSHIFT);
 	wrmsr(MSR_HV_REFERENCE_TSC, msr);
 	/* Install 64 bits timecounter method for other modules to use. */
 	hyperv_tc64 = hyperv_tc64_tsc;
 	/* Register "enlightened" timecounter. */
 	tc_init(&hyperv_tsc_timecounter);
 	return true;
+}
 #endif /* __amd64__ */
 static void
 delay_tc(unsigned int n)
+{
 	struct timecounter *tc;
 	uint64_t end, now;
 	u_int last, u;
 	tc = timecounter;
 	if (tc->tc_quality <= 0) {
 		x86_delay(n);
 		return;
+	}
 	now = 0;
 	end = tc->tc_frequency * n / 1000000;
 	last = tc->tc_get_timecount(tc) & tc->tc_counter_mask;
 	do {
 		x86_pause();
 		u = tc->tc_get_timecount(tc) & tc->tc_counter_mask;
 		if (u < last)
 			now += tc->tc_counter_mask - last + u + 1;
 		else
 			now += u - last;
 		last = u;
 	} while (now < end);
+}
 static void
 delay_msr(unsigned int n)
+{
 	uint64_t end, now;
 	u_int last, u;
 	now = 0;
 	end = HYPERV_TIMER_FREQ * n / 1000000ULL;
 	last = (u_int)rdmsr(MSR_HV_TIME_REF_COUNT);
 	do {
 		x86_pause();
 		u = (u_int)rdmsr(MSR_HV_TIME_REF_COUNT);
 		if (u < last)
 			now += 0xffffffff - last + u + 1;
 		else
 			now += u - last;
 		last = u;
 	} while (now < end);
+}
 static __inline uint64_t
 hyperv_hypercall_md(volatile void *hc_addr, uint64_t in_val, uint64_t in_paddr,
     uint64_t out_paddr)
+{
 	uint64_t status;
 #ifdef __amd64__
 	__asm__ __volatile__ ("mov %0, %%r8" : : "r" (out_paddr): "r8");
 	__asm__ __volatile__ ("call *%3" : "=a" (status) : "c" (in_val),
 	    "d" (in_paddr), "m" (hc_addr));
 #else
 	uint32_t in_val_hi = in_val >> 32;
 	uint32_t in_val_lo = in_val & 0xFFFFFFFF;
 	uint32_t status_hi, status_lo;
 	uint32_t in_paddr_hi = in_paddr >> 32;
 	uint32_t in_paddr_lo = in_paddr & 0xFFFFFFFF;
 	uint32_t out_paddr_hi = out_paddr >> 32;
 	uint32_t out_paddr_lo = out_paddr & 0xFFFFFFFF;
 	__asm__ __volatile__ ("call *%8" : "=d" (status_hi), "=a" (status_lo) :
 	    "d" (in_val_hi), "a" (in_val_lo),
 	    "b" (in_paddr_hi), "c" (in_paddr_lo),
 	    "D" (out_paddr_hi), "S" (out_paddr_lo),
 	    "m" (hc_addr));
 	status = status_lo | ((uint64_t)status_hi << 32);
 #endif
 	return status;
+}
 uint64_t
 hyperv_hypercall(uint64_t control, paddr_t in_paddr, paddr_t out_paddr)
+{
 	if (hyperv_hypercall_ctx.hc_addr == NULL)
 		return ~HYPERCALL_STATUS_SUCCESS;
 	return hyperv_hypercall_md(hyperv_hypercall_ctx.hc_addr, control,
 	    in_paddr, out_paddr);
+}
 static bool
 hyperv_probe(u_int *maxleaf, u_int *features, u_int *pm_features,
     u_int *features3)
+{
 	u_int regs[4];
 	if (vm_guest != VM_GUEST_HV)
 		return false;
 	x86_cpuid(CPUID_LEAF_HV_MAXLEAF, regs);
 	*maxleaf = regs[0];
 	if (*maxleaf < CPUID_LEAF_HV_LIMITS)
 		return false;
 	x86_cpuid(CPUID_LEAF_HV_INTERFACE, regs);
 	if (regs[0] != CPUID_HV_IFACE_HYPERV)
 		return false;
 	x86_cpuid(CPUID_LEAF_HV_FEATURES, regs);
 	if (!(regs[0] & CPUID_HV_MSR_HYPERCALL)) {
 		/*
 		 * Hyper-V w/o Hypercall is impossible; someone
 		 * is faking Hyper-V.
 		 */
 		return false;
+	}
 	*features = regs[0];
 	*pm_features = regs[2];
 	*features3 = regs[3];
 	return true;
+}
 static bool
 hyperv_identify(void)
+{
 	char buf[256];
 	u_int regs[4];
 	u_int maxleaf;
 	if (!hyperv_probe(&maxleaf, &hyperv_features, &hyperv_pm_features,
 	    &hyperv_features3))
 		return false;
 	x86_cpuid(CPUID_LEAF_HV_IDENTITY, regs);
 	hyperv_ver_major = regs[1] >> 16;
 	snprintf(hyperv_version_str, sizeof(hyperv_version_str),
 	    "%d.%d.%d [SP%d]",
 	    hyperv_ver_major, regs[1] & 0xffff, regs[0], regs[2]);
 	aprint_verbose("Hyper-V Version: %s\n", hyperv_version_str);
 	snprintb(hyperv_features_str, sizeof(hyperv_features_str),
 	    "\020"
 	    "\001VPRUNTIME"	/* MSR_HV_VP_RUNTIME */
 	    "\002TMREFCNT"	/* MSR_HV_TIME_REF_COUNT */
 	    "\003SYNIC"		/* MSRs for SynIC */
 	    "\004SYNTM"		/* MSRs for SynTimer */
 	    "\005APIC"		/* MSR_HV_{EOI,ICR,TPR} */
 	    "\006HYPERCALL"	/* MSR_HV_{GUEST_OS_ID,HYPERCALL} */
 	    "\007VPINDEX"	/* MSR_HV_VP_INDEX */
 	    "\010RESET"		/* MSR_HV_RESET */
 	    "\011STATS"		/* MSR_HV_STATS_ */
 	    "\012REFTSC"	/* MSR_HV_REFERENCE_TSC */
 	    "\013IDLE"		/* MSR_HV_GUEST_IDLE */
 	    "\014TMFREQ"	/* MSR_HV_{TSC,APIC}_FREQUENCY */
 	    "\015DEBUG",	/* MSR_HV_SYNTH_DEBUG_ */
 	    hyperv_features);
 	aprint_verbose("  Features=%s\n", hyperv_features_str);
 	snprintb(buf, sizeof(buf),
 	    "\020"
 	    "\005C3HPET",	/* HPET is required for C3 state */
 	    (hyperv_pm_features & ~CPUPM_HV_CSTATE_MASK));
 	snprintf(hyperv_pm_features_str, sizeof(hyperv_pm_features_str),
 	    "%s [C%u]", buf, CPUPM_HV_CSTATE(hyperv_pm_features));
 	aprint_verbose("  PM Features=%s\n", hyperv_pm_features_str);
 	snprintb(hyperv_features3_str, sizeof(hyperv_features3_str),
 	    "\020"
 	    "\001MWAIT"		/* MWAIT */
 	    "\002DEBUG"		/* guest debug support */
 	    "\003PERFMON"	/* performance monitor */
 	    "\004PCPUDPE"	/* physical CPU dynamic partition event */
 	    "\005XMMHC"		/* hypercall input through XMM regs */
 	    "\006IDLE"		/* guest idle support */
 	    "\007SLEEP"		/* hypervisor sleep support */
 	    "\010NUMA"		/* NUMA distance query support */
 	    "\011TMFREQ"	/* timer frequency query (TSC, LAPIC) */
 	    "\012SYNCMC"	/* inject synthetic machine checks */
 	    "\013CRASH"		/* MSRs for guest crash */
 	    "\014DEBUGMSR"	/* MSRs for guest debug */
 	    "\015NPIEP"		/* NPIEP */
 	    "\016HVDIS",	/* disabling hypervisor */
 	    hyperv_features3);
 	aprint_verbose("  Features3=%s\n", hyperv_features3_str);
 	x86_cpuid(CPUID_LEAF_HV_RECOMMENDS, regs);
 	hyperv_recommends = regs[0];
 	aprint_verbose("  Recommends: %08x %08x\n", regs[0], regs[1]);
 	x86_cpuid(CPUID_LEAF_HV_LIMITS, regs);
 	aprint_verbose("  Limits: Vcpu:%d Lcpu:%d Int:%d\n",
 	    regs[0], regs[1], regs[2]);
 	if (maxleaf >= CPUID_LEAF_HV_HWFEATURES) {
 		x86_cpuid(CPUID_LEAF_HV_HWFEATURES, regs);
 		aprint_verbose("  HW Features: %08x, AMD: %08x\n",
 		    regs[0], regs[3]);
+	}
 	return true;
+}
 void
 hyperv_early_init(void)
+{
 	u_int features, pm_features, features3;
 	u_int maxleaf;
 	int i;
 	if (!hyperv_probe(&maxleaf, &features, &pm_features, &features3))
 		return;
 	if (features & CPUID_HV_MSR_TIME_REFCNT)
 		x86_delay = delay_func = delay_msr;
 	if (features & CPUID_HV_MSR_VP_INDEX) {
 		/* Save virtual processor id. */
 		hyperv_vcpuid[0] = rdmsr(MSR_HV_VP_INDEX);
 	} else {
 		/* Set virtual processor id to 0 for compatibility. */
 		hyperv_vcpuid[0] = 0;
+	}
 	for (i = 1; i < MAXCPUS; i++)
 		hyperv_vcpuid[i] = hyperv_vcpuid[0];
+}
 void
 hyperv_init_cpu(struct cpu_info *ci)
+{
 	u_int features, pm_features, features3;
 	u_int maxleaf;
 	if (!hyperv_probe(&maxleaf, &features, &pm_features, &features3))
 		return;
 	if (features & CPUID_HV_MSR_VP_INDEX)
 		hyperv_vcpuid[ci->ci_index] = rdmsr(MSR_HV_VP_INDEX);
+}
 uint32_t
 hyperv_get_vcpuid(cpuid_t cpu)
+{
 	if (cpu < MAXCPUS)
 		return hyperv_vcpuid[cpu];
 	return 0;
+}
 static bool
 hyperv_init(void)
+{
 	if (!hyperv_identify()) {
 		/* Not Hyper-V; reset guest id to the generic one. */
 		if (vm_guest == VM_GUEST_HV)
 			vm_guest = VM_GUEST_VM;
 		return false;
+	}
 	/* Set guest id */
 	wrmsr(MSR_HV_GUEST_OS_ID, MSR_HV_GUESTID_OSTYPE_NETBSD |
 	    (uint64_t)__NetBSD_Version__ << MSR_HV_GUESTID_VERSION_SHIFT);
 	if (hyperv_features & CPUID_HV_MSR_TIME_REFCNT) {
 		/* Register Hyper-V timecounter */
 		tc_init(&hyperv_timecounter);
 		/*
 		 * Install 64 bits timecounter method for other modules to use.
 		 */
 		hyperv_tc64 = hyperv_tc64_rdmsr;
 #ifdef __amd64__
 		hyperv_tsc_tcinit();
 #endif
 		/* delay with timecounter */
 		x86_delay = delay_func = delay_tc;
+	}
 #if NLAPIC > 0
 	if ((hyperv_features & CPUID_HV_MSR_TIME_FREQ) &&
 	    (hyperv_features3 & CPUID3_HV_TIME_FREQ))
 		lapic_per_second = rdmsr(MSR_HV_APIC_FREQUENCY);
 #endif
 	return hyperv_init_hypercall();
+}
 static bool
 hyperv_is_initialized(void)
+{
 	uint64_t msr;
 	if (vm_guest != VM_GUEST_HV)
 		return false;
 	if (rdmsr_safe(MSR_HV_HYPERCALL, &msr) == EFAULT)
 		return false;
 	return (msr & MSR_HV_HYPERCALL_ENABLE) ? true : false;
+}
 static int
 hyperv_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct cpufeature_attach_args *cfaa = aux;
 	struct cpu_info *ci = cfaa->ci;
 	if (strcmp(cfaa->name, "vm") != 0)
 		return 0;
 	if ((ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) == 0)
 		return 0;
 	if (vm_guest != VM_GUEST_HV)
 		return 0;
 	return 1;
+}
 static void
 hyperv_attach(device_t parent, device_t self, void *aux)
+{
 	struct hyperv_softc *sc = device_private(self);
 	sc->sc_dev = self;
 	aprint_naive("\n");
 	aprint_normal(": Hyper-V\n");
 	if (!hyperv_is_initialized()) {
 		if (rdmsr(MSR_HV_GUEST_OS_ID) == 0) {
 			if (!hyperv_init()) {
 				aprint_error_dev(self, "initialize failed\n");
 				return;
+			}
+		}
 		hyperv_init_hypercall();
+	}
 	(void) pmf_device_register(self, NULL, NULL);
 	(void) hyperv_sysctl_setup_root(sc);
+}
 static int
 hyperv_detach(device_t self, int flags)
+{
 	struct hyperv_softc *sc = device_private(self);
 	uint64_t hc;
 	/* Disable Hypercall */
 	hc = rdmsr(MSR_HV_HYPERCALL);
 	wrmsr(MSR_HV_HYPERCALL, hc & MSR_HV_HYPERCALL_RSVD_MASK);
 	hyperv_hypercall_memfree();
 	if (hyperv_features & CPUID_HV_MSR_TIME_REFCNT)
 		tc_detach(&hyperv_timecounter);
 	wrmsr(MSR_HV_GUEST_OS_ID, 0);
 	pmf_device_deregister(self);
 	if (sc->sc_log != NULL) {
 		sysctl_teardown(&sc->sc_log);
 		sc->sc_log = NULL;
+	}
 	return 0;
+}
 void
 hyperv_intr(void)
+{
 	struct cpu_info *ci = curcpu();
 	(*hyperv_event_proc.func)(hyperv_event_proc.arg, ci);
 	(*hyperv_message_proc.func)(hyperv_message_proc.arg, ci);
+}
 void hyperv_hypercall_intr(struct trapframe *);
 void
 hyperv_hypercall_intr(struct trapframe *frame __unused)
+{
 	struct cpu_info *ci = curcpu();
 	ci->ci_isources[LIR_HV]->is_evcnt.ev_count++;
 	hyperv_intr();
+}
 static void
 hyperv_proc_dummy(void *arg __unused, struct cpu_info *ci __unused)
+{
+}
 void
 hyperv_set_event_proc(void (*func)(void *, struct cpu_info *), void *arg)
+{
 	hyperv_event_proc.func = func;
 	hyperv_event_proc.arg = arg;
+}
 void
 hyperv_set_message_proc(void (*func)(void *, struct cpu_info *), void *arg)
+{
 	hyperv_message_proc.func = func;
 	hyperv_message_proc.arg = arg;
+}
 static void
 hyperv_hypercall_memfree(void)
+{
 	hyperv_hypercall_ctx.hc_addr = NULL;
+}
 static bool
 hyperv_init_hypercall(void)
+{
 	uint64_t hc, hc_orig;
 	hyperv_hypercall_ctx.hc_addr = hyperv_hypercall_page;
 	hyperv_hypercall_ctx.hc_paddr = vtophys((vaddr_t)hyperv_hypercall_page);
 	KASSERT(hyperv_hypercall_ctx.hc_paddr != 0);
 	/* Get the 'reserved' bits, which requires preservation. */
 	hc_orig = rdmsr(MSR_HV_HYPERCALL);
 	/*
 	 * Setup the Hypercall page.
+	 *
 	 * NOTE: 'reserved' bits MUST be preserved.
 	 */
 	hc = (atop(hyperv_hypercall_ctx.hc_paddr) << MSR_HV_HYPERCALL_PGSHIFT) |
 	    (hc_orig & MSR_HV_HYPERCALL_RSVD_MASK) |
 	    MSR_HV_HYPERCALL_ENABLE;
 	wrmsr(MSR_HV_HYPERCALL, hc);
 	/*
 	 * Confirm that Hypercall page did get setup.
 	 */
 	hc = rdmsr(MSR_HV_HYPERCALL);
 	if (!(hc & MSR_HV_HYPERCALL_ENABLE)) {
 		aprint_error("Hyper-V: Hypercall setup failed\n");
 		hyperv_hypercall_memfree();
 		/* Can't perform any Hyper-V specific actions */
 		vm_guest = VM_GUEST_VM;
 		return false;
+	}
 	return true;
+}
 int
 hyperv_hypercall_enabled(void)
+{
 	return hyperv_is_initialized();
+}
 int
 hyperv_synic_supported(void)
+{
 	return (hyperv_features & CPUID_HV_MSR_SYNIC) ? 1 : 0;
+}
 int
 hyperv_is_gen1(void)
+{
 	return !efi_probe();
+}
 void
 hyperv_send_eom(void)
+{
 	wrmsr(MSR_HV_EOM, 0);
+}
 void
 vmbus_init_interrupts_md(struct vmbus_softc *sc)
+{
 	extern void Xintr_hyperv_hypercall(void);
 	struct vmbus_percpu_data *pd;
 	struct hyperv_percpu_data *hv_pd;
 	struct idt_vec *iv = &(cpu_info_primary.ci_idtvec);
 	cpuid_t cid;
 	if (idt_vec_is_pcpu())
 		return;
 	/*
 	 * All Hyper-V ISR required resources are setup, now let's find a
 	 * free IDT vector for Hyper-V ISR and set it up.
 	 */
 	iv = &(cpu_info_primary.ci_idtvec);
 	cid = cpu_index(&cpu_info_primary);
 	pd = &sc->sc_percpu[cid];
 	hv_pd = kmem_zalloc(sizeof(*hv_pd), KM_SLEEP);
 	mutex_enter(&cpu_lock);
 	hv_pd->pd_idtvec = idt_vec_alloc(iv,
 	    APIC_LEVEL(NIPL), IDT_INTR_HIGH);
 	mutex_exit(&cpu_lock);
 	KASSERT(hv_pd->pd_idtvec > 0);
 	idt_vec_set(iv, hv_pd->pd_idtvec, Xintr_hyperv_hypercall);
 	pd->md_cookie = (void *)hv_pd;
+}
 void
 vmbus_deinit_interrupts_md(struct vmbus_softc *sc)
+{
 	struct vmbus_percpu_data *pd;
 	struct hyperv_percpu_data *hv_pd;
 	struct idt_vec *iv;
 	cpuid_t cid;
 	if (idt_vec_is_pcpu())
 		return;
 	iv = &(cpu_info_primary.ci_idtvec);
 	cid = cpu_index(&cpu_info_primary);
 	pd = &sc->sc_percpu[cid];
 	hv_pd = pd->md_cookie;
 	if (hv_pd->pd_idtvec > 0)
 		idt_vec_free(iv, hv_pd->pd_idtvec);
 	pd->md_cookie = NULL;
 	kmem_free(hv_pd, sizeof(*hv_pd));
+}
 void
 vmbus_init_synic_md(struct vmbus_softc *sc, cpuid_t cpu)
+{
 	extern void Xintr_hyperv_hypercall(void);
 	struct vmbus_percpu_data *pd, *pd0;
 	struct hyperv_percpu_data *hv_pd;
 	struct cpu_info *ci;
 	struct idt_vec *iv;
 	uint64_t val, orig;
 	uint32_t sint;
 	int hyperv_idtvec;
 	pd = &sc->sc_percpu[cpu];
 	hv_pd = kmem_alloc(sizeof(*hv_pd), KM_SLEEP);
 	pd->md_cookie = (void *)hv_pd;
 	/* Allocate IDT vector for ISR and set it up. */
 	if (idt_vec_is_pcpu()) {
 		ci = curcpu();
 		iv = &ci->ci_idtvec;
 		mutex_enter(&cpu_lock);
 		hyperv_idtvec = idt_vec_alloc(iv, APIC_LEVEL(NIPL), IDT_INTR_HIGH);
 		mutex_exit(&cpu_lock);
 		KASSERT(hyperv_idtvec > 0);
 		idt_vec_set(iv, hyperv_idtvec, Xintr_hyperv_hypercall);
 		hv_pd = kmem_alloc(sizeof(*hv_pd), KM_SLEEP);
 		hv_pd->pd_idtvec = hyperv_idtvec;
 		pd->md_cookie = hv_pd;
 	} else {
 		pd0 = &sc->sc_percpu[cpu_index(&cpu_info_primary)];
 		hv_pd = pd0->md_cookie;
 		hyperv_idtvec = hv_pd->pd_idtvec;
+	}
 	/*
 	 * Setup the SynIC message.
 	 */
 	orig = rdmsr(MSR_HV_SIMP);
 	val = MSR_HV_SIMP_ENABLE | (orig & MSR_HV_SIMP_RSVD_MASK) |
 	    (atop(hyperv_dma_get_paddr(&pd->simp_dma)) << MSR_HV_SIMP_PGSHIFT);
 	wrmsr(MSR_HV_SIMP, val);
 	/*
 	 * Setup the SynIC event flags.
 	 */
 	orig = rdmsr(MSR_HV_SIEFP);
 	val = MSR_HV_SIEFP_ENABLE | (orig & MSR_HV_SIEFP_RSVD_MASK) |
 	    (atop(hyperv_dma_get_paddr(&pd->siep_dma)) << MSR_HV_SIEFP_PGSHIFT);
 	wrmsr(MSR_HV_SIEFP, val);
 	/*
 	 * Configure and unmask SINT for message and event flags.
 	 */
 	sint = MSR_HV_SINT0 + VMBUS_SINT_MESSAGE;
 	orig = rdmsr(sint);
 	val = hyperv_idtvec | MSR_HV_SINT_AUTOEOI |
 	    (orig & MSR_HV_SINT_RSVD_MASK);
 	wrmsr(sint, val);
 	/*
 	 * Configure and unmask SINT for timer.
 	 */
 	sint = MSR_HV_SINT0 + VMBUS_SINT_TIMER;
 	orig = rdmsr(sint);
 	val = hyperv_idtvec | MSR_HV_SINT_AUTOEOI |
 	    (orig & MSR_HV_SINT_RSVD_MASK);
 	wrmsr(sint, val);
 	/*
 	 * All done; enable SynIC.
 	 */
 	orig = rdmsr(MSR_HV_SCONTROL);
 	val = MSR_HV_SCTRL_ENABLE | (orig & MSR_HV_SCTRL_RSVD_MASK);
 	wrmsr(MSR_HV_SCONTROL, val);
+}
 void
 vmbus_deinit_synic_md(struct vmbus_softc *sc, cpuid_t cpu)
+{
 	struct vmbus_percpu_data *pd;
 	struct hyperv_percpu_data *hv_pd;
 	struct cpu_info *ci;
 	struct idt_vec *iv;
 	uint64_t orig;
 	uint32_t sint;
 	/*
 	 * Disable SynIC.
 	 */
 	orig = rdmsr(MSR_HV_SCONTROL);
 	wrmsr(MSR_HV_SCONTROL, (orig & MSR_HV_SCTRL_RSVD_MASK));
 	/*
 	 * Mask message and event flags SINT.
 	 */
 	sint = MSR_HV_SINT0 + VMBUS_SINT_MESSAGE;
 	orig = rdmsr(sint);
 	wrmsr(sint, orig | MSR_HV_SINT_MASKED);
 	/*
 	 * Mask timer SINT.
 	 */
 	sint = MSR_HV_SINT0 + VMBUS_SINT_TIMER;
 	orig = rdmsr(sint);
 	wrmsr(sint, orig | MSR_HV_SINT_MASKED);
 	/*
 	 * Teardown SynIC message.
 	 */
 	orig = rdmsr(MSR_HV_SIMP);
 	wrmsr(MSR_HV_SIMP, (orig & MSR_HV_SIMP_RSVD_MASK));
 	/*
 	 * Teardown SynIC event flags.
 	 */
 	orig = rdmsr(MSR_HV_SIEFP);
 	wrmsr(MSR_HV_SIEFP, (orig & MSR_HV_SIEFP_RSVD_MASK));
 	/*
 	 * Free IDT vector
 	 */
 	if (idt_vec_is_pcpu()) {
 		ci = curcpu();
 		iv = &ci->ci_idtvec;
 		pd = &sc->sc_percpu[cpu_index(ci)];
 		hv_pd = pd->md_cookie;
 		if (hv_pd->pd_idtvec > 0)
 			idt_vec_free(iv, hv_pd->pd_idtvec);
 		pd->md_cookie = NULL;
 		kmem_free(hv_pd, sizeof(*hv_pd));
+	}
+}
 static int
 hyperv_sysctl_setup(struct hyperv_softc *sc,
     const struct sysctlnode *hyperv_node)
+{
 	int error;
 	error = sysctl_createv(&sc->sc_log, 0, &hyperv_node, NULL,
 	    CTLFLAG_READONLY, CTLTYPE_STRING, "version", NULL,
 	    NULL, 0, hyperv_version_str,
 , CTL_CREATE, CTL_EOL);
 	if (error)
 		return error;
 	error = sysctl_createv(&sc->sc_log, 0, &hyperv_node, NULL,
 	    CTLFLAG_READONLY, CTLTYPE_STRING, "features", NULL,
 	    NULL, 0, hyperv_features_str,
 , CTL_CREATE, CTL_EOL);
 	if (error)
 		return error;
 	error = sysctl_createv(&sc->sc_log, 0, &hyperv_node, NULL,
 	    CTLFLAG_READONLY, CTLTYPE_STRING, "pm_features", NULL,
 	    NULL, 0, hyperv_pm_features_str,
 , CTL_CREATE, CTL_EOL);
 	if (error)
 		return error;
 	error = sysctl_createv(&sc->sc_log, 0, &hyperv_node, NULL,
 	    CTLFLAG_READONLY, CTLTYPE_STRING, "features3", NULL,
 	    NULL, 0, hyperv_features3_str,
 , CTL_CREATE, CTL_EOL);
 	if (error)
 		return error;
 	return 0;
+}
 static int
 hyperv_sysctl_setup_root(struct hyperv_softc *sc)
+{
 	const struct sysctlnode *machdep_node, *hyperv_node;
 	int error;
 	error = sysctl_createv(&sc->sc_log, 0, NULL, &machdep_node,
 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL,
 	    NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL);
 	if (error)
 		goto fail;
 	error = sysctl_createv(&sc->sc_log, 0, &machdep_node, &hyperv_node,
 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, "hyperv", NULL,
 	    NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL);
 	if (error)
 		goto fail;
 	error = hyperv_sysctl_setup(sc, hyperv_node);
 	if (error)
 		goto fail;
 	return 0;
 fail:
 	sysctl_teardown(&sc->sc_log);
 	sc->sc_log = NULL;
 	return error;
+}
 MODULE(MODULE_CLASS_DRIVER, hyperv, NULL);
 #ifdef _MODULE
 #include "ioconf.c"
 #endif
 static int
 hyperv_modcmd(modcmd_t cmd, void *aux)
+{
 	int rv = 0;
 	switch (cmd) {
 	case MODULE_CMD_INIT:
 #ifdef _MODULE
 		rv = config_init_component(cfdriver_ioconf_hyperv,
 		    cfattach_ioconf_hyperv, cfdata_ioconf_hyperv);
 #endif
 		hyperv_init();
 		break;
 	case MODULE_CMD_FINI:
 #ifdef _MODULE
 		rv = config_fini_component(cfdriver_ioconf_hyperv,
 		    cfattach_ioconf_hyperv, cfdata_ioconf_hyperv);
 #endif
 		break;
 	default:
 		rv = ENOTTY;
 		break;
+	}
 	return rv;
+}
 #if NVMBUS > 0
 /*
  * genfb at vmbus
  */
 static struct genfb_pmf_callback pmf_cb;
 static struct genfb_mode_callback mode_cb;
 static bool
 x86_genfb_setmode(struct genfb_softc *sc, int newmode)
+{
 #if NGENFB > 0
 	switch (newmode) {
 	case WSDISPLAYIO_MODE_EMUL:
 		x86_genfb_mtrr_init(sc->sc_fboffset,
 		    sc->sc_height * sc->sc_stride);
 		break;
 #endif
 	return true;
+}
 static bool
 x86_genfb_suspend(device_t dev, const pmf_qual_t *qual)
+{
 	return true;
+}
 static bool
 x86_genfb_resume(device_t dev, const pmf_qual_t *qual)
+{
 #if NGENFB > 0
 	struct genfb_vmbus_softc *sc = device_private(dev);
 	genfb_restore_palette(&sc->sc_gen);
 #endif
 	return true;
+}
 static void
 populate_fbinfo(device_t dev, prop_dictionary_t dict)
+{
 #if NWSDISPLAY > 0 && NGENFB > 0
 	extern struct vcons_screen x86_genfb_console_screen;
 	struct rasops_info *ri = &x86_genfb_console_screen.scr_ri;
 #endif
 	const void *fbptr = lookup_bootinfo(BTINFO_FRAMEBUFFER);
 	struct btinfo_framebuffer fbinfo;
 	if (fbptr == NULL)
 		return;
 	memcpy(&fbinfo, fbptr, sizeof(fbinfo));
 	if (fbinfo.physaddr != 0) {
 		prop_dictionary_set_uint32(dict, "width", fbinfo.width);
 		prop_dictionary_set_uint32(dict, "height", fbinfo.height);
 		prop_dictionary_set_uint8(dict, "depth", fbinfo.depth);
 		prop_dictionary_set_uint16(dict, "linebytes", fbinfo.stride);
 		prop_dictionary_set_uint64(dict, "address", fbinfo.physaddr);
 #if NWSDISPLAY > 0 && NGENFB > 0
 		if (ri->ri_bits != NULL) {
 			prop_dictionary_set_uint64(dict, "virtual_address",
 			    ri->ri_hwbits != NULL ?
 			    (vaddr_t)ri->ri_hworigbits :
 			    (vaddr_t)ri->ri_origbits);
+		}
 #endif
+	}
 #if notyet
 	prop_dictionary_set_bool(dict, "splash",
 	    (fbinfo.flags & BI_FB_SPLASH) != 0);
 #endif
 #if 0
 	if (fbinfo.depth == 8) {
 		gfb_cb.gcc_cookie = NULL;
 		gfb_cb.gcc_set_mapreg = x86_genfb_set_mapreg;
 		prop_dictionary_set_uint64(dict, "cmap_callback",
 		    (uint64_t)(uintptr_t)&gfb_cb);
+	}
 #endif
 	if (fbinfo.physaddr != 0) {
 		mode_cb.gmc_setmode = x86_genfb_setmode;
 		prop_dictionary_set_uint64(dict, "mode_callback",
 		    (uint64_t)(uintptr_t)&mode_cb);
+	}
 #if NWSDISPLAY > 0 && NGENFB > 0
 	if (device_is_a(dev, "genfb")) {
 		prop_dictionary_set_bool(dict, "enable_shadowfb",
 		    ri->ri_hwbits != NULL);
 		x86_genfb_set_console_dev(dev);
 #ifdef DDB
 		db_trap_callback = x86_genfb_ddb_trap_callback;
 #endif
+	}
 #endif
+}
 #endif
 device_t
 device_hyperv_register(device_t dev, void *aux)
+{
 #if NVMBUS > 0
 	device_t parent = device_parent(dev);
 	if (parent && device_is_a(parent, "vmbus") && !x86_found_console) {
 		struct vmbus_attach_args *aa = aux;
 		if (memcmp(aa->aa_type, &hyperv_guid_video,
 		    sizeof(*aa->aa_type)) == 0) {
 			prop_dictionary_t dict = device_properties(dev);
 			/* Initialize genfb for serial console */
 			x86_genfb_init();
 			/*
 			 * framebuffer drivers other than genfb can work
 			 * without the address property
 			 */
 			populate_fbinfo(dev, dict);
 #if 1 && NWSDISPLAY > 0 && NGENFB > 0
 			/* XXX */
 			if (device_is_a(dev, "genfb")) {
 				prop_dictionary_set_bool(dict, "is_console",
 				    genfb_is_console());
 			} else
 #endif
 			prop_dictionary_set_bool(dict, "is_console", true);
 			prop_dictionary_set_bool(dict, "clear-screen", false);
 #if NWSDISPLAY > 0 && NGENFB > 0
 			extern struct vcons_screen x86_genfb_console_screen;
 			prop_dictionary_set_uint16(dict, "cursor-row",
 			    x86_genfb_console_screen.scr_ri.ri_crow);
 #endif
 			pmf_cb.gpc_suspend = x86_genfb_suspend;
 			pmf_cb.gpc_resume = x86_genfb_resume;
 			prop_dictionary_set_uint64(dict, "pmf_callback",
 			    (uint64_t)(uintptr_t)&pmf_cb);
 			x86_found_console = true;
 			return NULL;
+		}
+	}
 #endif
 	return NULL;
+}