 @@ -1,174 +1,177 @@
-/* $NetBSD: cycv_platform.c,v 1.15 2020/11/27 07:11:49 skrll Exp $ */
+/* $NetBSD: cycv_platform.c,v 1.16 2021/01/29 13:10:07 rin Exp $ */
 /* This file is in the public domain. */
 #include "arml2cc.h"
 #include "opt_console.h"
 #include "opt_multiprocessor.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cycv_platform.c,v 1.15 2020/11/27 07:11:49 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cycv_platform.c,v 1.16 2021/01/29 13:10:07 rin Exp $");
 #define	_ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <uvm/uvm_extern.h>
 #include <arm/arm32/machdep.h>
 #include <arm/altera/cycv_reg.h>
 #include <arm/altera/cycv_var.h>
 #include <arm/cortex/a9tmr_var.h>
 #include <arm/cortex/pl310_var.h>
 #include <arm/cortex/scu_reg.h>
 #include <arm/bootconfig.h>
 #include <arm/cpufunc.h>
 #include <arm/fdt/arm_fdtvar.h>
 #include <dev/fdt/fdtvar.h>
 #include <dev/ic/comreg.h>
 void cycv_platform_early_putchar(char);
 void __noasan
 cycv_platform_early_putchar(char c) {
 #ifdef CONSADDR
 #define CONSADDR_VA (CONSADDR - CYCV_PERIPHERAL_BASE + CYCV_PERIPHERAL_VBASE)
 	volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
 	    (volatile uint32_t *) CONSADDR_VA :
 	    (volatile uint32_t *) CONSADDR;
 	while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0)
+		;
 	uartaddr[com_data] = htole32(c);
 #endif
+}
 static const struct pmap_devmap *
 cycv_platform_devmap(void) {
 	static const struct pmap_devmap devmap[] = {
 		DEVMAP_ENTRY(CYCV_PERIPHERAL_VBASE,
 				CYCV_PERIPHERAL_BASE,
 				CYCV_PERIPHERAL_SIZE),
 		DEVMAP_ENTRY_END
 	};
 	return devmap;
+}
 static void
 cycv_platform_bootstrap(void)
+{
 	bus_space_tag_t bst = &armv7_generic_bs_tag;
 	bus_space_handle_t bsh_l2c;
 	bus_space_map(bst, CYCV_L2CACHE_BASE, CYCV_L2CACHE_SIZE, 0, &bsh_l2c);
 #if NARML2CC > 0
 	arml2cc_init(bst, bsh_l2c, 0);
 #endif
 	arm_fdt_cpu_bootstrap();
+}
 static int
 cycv_mpstart(void)
+{
 	int ret = 0;
 #ifdef MULTIPROCESSOR
 	bus_space_tag_t bst = &armv7_generic_bs_tag;
 	bus_space_handle_t bsh_rst;
 	bus_space_handle_t bsh_scu;
 	int ret = 0;
 	bus_space_map(bst, CYCV_RSTMGR_BASE, CYCV_RSTMGR_SIZE, 0, &bsh_rst);
 	bus_space_map(bst, CYCV_SCU_BASE, CYCV_SCU_SIZE, 0, &bsh_scu);
 	/* Enable Snoop Control Unit */
 	bus_space_write_4(bst, bsh_scu, SCU_INV_ALL_REG, 0xff);
 	bus_space_write_4(bst, bsh_scu, SCU_CTL,
 		bus_space_read_4(bst, bsh_scu, SCU_CTL) | SCU_CTL_SCU_ENA);
 	const uint32_t startfunc =
 		(uint32_t) KERN_VTOPHYS((vaddr_t) cpu_mpstart);
 	/*
 	 * We place a "LDR PC, =cpu_mpstart" at address 0 in order to bootstrap
 	 * CPU 1. We can't use the similar feature of the Boot ROM because
 	 * it was unmapped by u-boot in favor of the SDRAM.
 	 */
 	pmap_map_chunk(kernel_l1pt.pv_va, CYCV_SDRAM_VBASE, CYCV_SDRAM_BASE,
 		L1_S_SIZE, VM_PROT_READ|VM_PROT_WRITE, PMAP_NOCACHE);
 	/* 0: LDR PC, [PC, #0x18] -> loads address at 0x20 into PC */
 	*(volatile uint32_t *) CYCV_SDRAM_VBASE = htole32(0xe59ff018);
 	*(volatile uint32_t *) (CYCV_SDRAM_VBASE + 0x20) = startfunc;
 	pmap_unmap_chunk(kernel_l1pt.pv_va, CYCV_SDRAM_VBASE, L1_S_SIZE);
 	bus_space_write_4(bst, bsh_rst, CYCV_RSTMGR_MPUMODRST,
 		bus_space_read_4(bst, bsh_rst, CYCV_RSTMGR_MPUMODRST) &
 			~CYCV_RSTMGR_MPUMODRST_CPU1);
 	/* Wait for secondary processor to start */
 	int i;
 	for (i = 0x10000000; i > 0; i--) {
 		if (cpu_hatched_p(1))
 			break;
+	}
 	if (i == 0) {
 		aprint_error("cpu%d: WARNING: AP failed to start\n", 1);
 		ret++;
+	}
 #endif
 	return ret;
+}
 static void
 cycv_platform_init_attach_args(struct fdt_attach_args *faa) {
 	faa->faa_bst = &armv7_generic_bs_tag;
 	faa->faa_dmat = &arm_generic_dma_tag;
+}
 static void
 cycv_platform_device_register(device_t dev, void *aux) {
 	prop_dictionary_t dict = device_properties(dev);
 	if (device_is_a(dev, "arma9tmr")) {
 		prop_dictionary_set_uint32(dict, "frequency",
 			cycv_clkmgr_early_get_mpu_clk() / 4);
+	}
+}
 static void
 cycv_platform_reset(void) {
 	bus_space_tag_t bst = &armv7_generic_bs_tag;
 	bus_space_handle_t bsh;
 	uint32_t val;
 	bus_space_map(bst, CYCV_RSTMGR_BASE, CYCV_RSTMGR_SIZE, 0, &bsh);
 	val = bus_space_read_4(bst, bsh, CYCV_RSTMGR_CTRL);
 	bus_space_write_4(bst, bsh, CYCV_RSTMGR_CTRL,
 		val | CYCV_RSTMGR_CTRL_SWCOLDRSTREQ);
+}
 static u_int
 cycv_platform_uart_freq(void) {
 	return cycv_clkmgr_early_get_l4_sp_clk();
+}
 static const struct arm_platform cycv_platform = {
 	.ap_devmap = cycv_platform_devmap,
 	.ap_bootstrap = cycv_platform_bootstrap,
 	.ap_init_attach_args = cycv_platform_init_attach_args,
 	.ap_device_register = cycv_platform_device_register,
 	.ap_reset = cycv_platform_reset,
 	.ap_delay = a9tmr_delay,
 	.ap_uart_freq = cycv_platform_uart_freq,
 	.ap_mpstart = cycv_mpstart,
 };
 ARM_PLATFORM(cycv, "altr,socfpga-cyclone5", &cycv_platform);

 @@ -1,494 +1,498 @@
-/* $NetBSD: meson_platform.c,v 1.16 2020/09/28 11:54:22 jmcneill Exp $ */
+/* $NetBSD: meson_platform.c,v 1.17 2021/01/29 13:10:07 rin Exp $ */
 /*-
  * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "opt_soc.h"
 #include "opt_multiprocessor.h"
 #include "opt_console.h"
 #include "arml2cc.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: meson_platform.c,v 1.16 2020/09/28 11:54:22 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: meson_platform.c,v 1.17 2021/01/29 13:10:07 rin Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/termios.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/fdt/arm_fdtvar.h>
 #include <uvm/uvm_extern.h>
 #include <machine/bootconfig.h>
 #include <arm/cpufunc.h>
 #include <arm/cortex/a9tmr_var.h>
 #include <arm/cortex/gtmr_var.h>
 #include <arm/cortex/pl310_var.h>
 #include <arm/cortex/scu_reg.h>
 #include <arm/amlogic/meson_uart.h>
 #include <evbarm/fdt/platform.h>
 #include <evbarm/fdt/machdep.h>
 #include <net/if_ether.h>
 #include <libfdt.h>
 #define	MESON_CORE_APB3_VBASE	KERNEL_IO_VBASE
 #define	MESON_CORE_APB3_PBASE	0xc0000000
 #define	MESON_CORE_APB3_SIZE	0x01400000
 #define	MESON_CBUS_OFFSET	0x01100000
 #define	MESON8B_WATCHDOG_BASE	0xc1109900
 #define	MESON8B_WATCHDOG_SIZE	0x8
 #define	 MESON8B_WATCHDOG_TC	0x00
 #define	  MESON8B_WATCHDOG_TC_CPUS	__BITS(27,24)
 #define	  MESON8B_WATCHDOG_TC_ENABLE	__BIT(19)
 #define	  MESON8B_WATCHDOG_TC_TCNT	__BITS(15,0)
 #define	 MESON8B_WATCHDOG_RESET	0x04
 #define	  MESON8B_WATCHDOG_RESET_COUNT	__BITS(15,0)
 #define	MESONGX_WATCHDOG_BASE	0xc11098d0
 #define	MESONGX_WATCHDOG_SIZE	0x10
 #define	 MESONGX_WATCHDOG_CNTL	0x00
 #define	  MESONGX_WATCHDOG_CNTL_CLK_EN		__BIT(24)
 #define	  MESONGX_WATCHDOG_CNTL_SYS_RESET_N_EN	__BIT(21)
 #define	  MESONGX_WATCHDOG_CNTL_WDOG_EN		__BIT(18)
 #define	 MESONGX_WATCHDOG_CNTL1	0x04
 #define	 MESONGX_WATCHDOG_TCNT	0x08
 #define	  MESONGX_WATCHDOG_TCNT_COUNT	__BITS(15,0)
 #define	 MESONGX_WATCHDOG_RESET	0x0c
 #define	MESON8B_ARM_VBASE	(MESON_CORE_APB3_VBASE + MESON_CORE_APB3_SIZE)
 #define	MESON8B_ARM_PBASE	0xc4200000
 #define	MESON8B_ARM_SIZE	0x00200000
 #define	MESON8B_ARM_PL310_BASE	0x00000000
 #define	MESON8B_ARM_SCU_BASE	0x00100000
 #define	MESON8B_AOBUS_VBASE	(MESON8B_ARM_VBASE + MESON8B_ARM_SIZE)
 #define	MESON8B_AOBUS_PBASE	0xc8000000
 #define	MESON8B_AOBUS_SIZE	0x00200000
 #define	MESON8B_AOBUS_RTI_OFFSET 0x00100000
 #define	MESON_AOBUS_PWR_CTRL0_REG	0xe0
 #define	MESON_AOBUS_PWR_CTRL1_REG	0xe4
 #define	MESON_AOBUS_PWR_MEM_PD0_REG	0xf4
 #define	MESON_CBUS_CPU_CLK_CNTL_REG	0x419c
 #define	MESON8B_SRAM_VBASE	(MESON8B_AOBUS_VBASE + MESON8B_AOBUS_SIZE)
 #define	MESON8B_SRAM_PBASE	0xd9000000
 #define	MESON8B_SRAM_SIZE	0x00200000	/* 0x10000 rounded up */
 #define	MESON8B_SRAM_CPUCONF_OFFSET		0x1ff80
 #define	MESON8B_SRAM_CPUCONF_CTRL_REG		0x00
 #define	MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(n)	(0x04 * (n))
 extern struct arm32_bus_dma_tag arm_generic_dma_tag;
 extern struct bus_space arm_generic_bs_tag;
 #define	meson_dma_tag		arm_generic_dma_tag
 #define	meson_bs_tag		arm_generic_bs_tag
 static const struct pmap_devmap *
 meson_platform_devmap(void)
+{
 	static const struct pmap_devmap devmap[] = {
 		DEVMAP_ENTRY(MESON_CORE_APB3_VBASE,
 			     MESON_CORE_APB3_PBASE,
 			     MESON_CORE_APB3_SIZE),
 		DEVMAP_ENTRY(MESON8B_ARM_VBASE,
 			     MESON8B_ARM_PBASE,
 			     MESON8B_ARM_SIZE),
 		DEVMAP_ENTRY(MESON8B_AOBUS_VBASE,
 			     MESON8B_AOBUS_PBASE,
 			     MESON8B_AOBUS_SIZE),
 		DEVMAP_ENTRY(MESON8B_SRAM_VBASE,
 			     MESON8B_SRAM_PBASE,
 			     MESON8B_SRAM_SIZE),
 		DEVMAP_ENTRY_END
 	};
 	return devmap;
+}
 static void
 meson_platform_init_attach_args(struct fdt_attach_args *faa)
+{
 	faa->faa_bst = &meson_bs_tag;
 	faa->faa_dmat = &meson_dma_tag;
+}
 void meson_platform_early_putchar(char);
 void __noasan
 meson_platform_early_putchar(char c)
+{
 #ifdef CONSADDR
 #define	CONSADDR_VA	((CONSADDR - MESON8B_AOBUS_PBASE) + MESON8B_AOBUS_VBASE)
 	volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
 	    (volatile uint32_t *)CONSADDR_VA :
 	    (volatile uint32_t *)CONSADDR;
 	int timo = 150000;
 	while ((uartaddr[UART_STATUS_REG/4] & UART_STATUS_TX_EMPTY) == 0) {
 		if (--timo == 0)
 			break;
+	}
 	uartaddr[UART_WFIFO_REG/4] = c;
 	while ((uartaddr[UART_STATUS_REG/4] & UART_STATUS_TX_EMPTY) == 0) {
 		if (--timo == 0)
 			break;
+	}
 #endif
+}
 static void
 meson_platform_device_register(device_t self, void *aux)
+{
 	prop_dictionary_t dict = device_properties(self);
 	if (device_is_a(self, "awge") && device_unit(self) == 0) {
 		uint8_t enaddr[ETHER_ADDR_LEN];
 		if (get_bootconf_option(boot_args, "awge0.mac-address",
 		    BOOTOPT_TYPE_MACADDR, enaddr)) {
 			prop_dictionary_set_data(dict, "mac-address", enaddr,
 			    sizeof(enaddr));
+		}
+	}
 	if (device_is_a(self, "mesonfb")) {
 		int scale, depth;
 		if (get_bootconf_option(boot_args, "fb.scale",
 		    BOOTOPT_TYPE_INT, &scale) && scale > 0) {
 			prop_dictionary_set_uint32(dict, "scale", scale);
+		}
 		if (get_bootconf_option(boot_args, "fb.depth",
 		    BOOTOPT_TYPE_INT, &depth)) {
 			prop_dictionary_set_uint32(dict, "depth", depth);
+		}
+	}
+}
 #if defined(SOC_MESON8B)
 #define	MESON8B_BOOTINFO_REG	0xd901ff04
 static int
 meson8b_get_boot_id(void)
+{
 	static int boot_id = -1;
 	bus_space_tag_t bst = &arm_generic_bs_tag;
 	bus_space_handle_t bsh;
 	if (boot_id == -1) {
 		if (bus_space_map(bst, MESON8B_BOOTINFO_REG, 4, 0, &bsh) != 0)
 			return -1;
 		boot_id = (int)bus_space_read_4(bst, bsh, 0);
 		bus_space_unmap(bst, bsh, 4);
+	}
 	return boot_id;
+}
 static void
 meson8b_platform_device_register(device_t self, void *aux)
+{
 	device_t parent = device_parent(self);
 	char *ptr;
 	if (device_is_a(self, "ld") &&
 	    device_is_a(parent, "sdmmc") &&
 	    (device_is_a(device_parent(parent), "mesonsdhc") ||
 	     device_is_a(device_parent(parent), "mesonsdio"))) {
 		const int boot_id = meson8b_get_boot_id();
 		const bool has_rootdev = get_bootconf_option(boot_args, "root", BOOTOPT_TYPE_STRING, &ptr) != 0;
 		if (!has_rootdev) {
 			char rootarg[64];
 			snprintf(rootarg, sizeof(rootarg), " root=%sa", device_xname(self));
 			/* Assume that SDIO is used for SD cards and SDHC is used for eMMC */
 			if (device_is_a(device_parent(parent), "mesonsdhc") && boot_id == 0)
 				strcat(boot_args, rootarg);
 			else if (device_is_a(device_parent(parent), "mesonsdio") && boot_id != 0)
 				strcat(boot_args, rootarg);
+		}
+	}
 	meson_platform_device_register(self, aux);
+}
 #endif
 static u_int
 meson_platform_uart_freq(void)
+{
 	return 0;
+}
 static void
 meson_platform_bootstrap(void)
+{
 	arm_fdt_cpu_bootstrap();
 	void *fdt_data = __UNCONST(fdtbus_get_data());
 	const int chosen_off = fdt_path_offset(fdt_data, "/chosen");
 	if (chosen_off < 0)
 		return;
 	if (match_bootconf_option(boot_args, "console", "fb")) {
 		const int framebuffer_off =
 		    fdt_path_offset(fdt_data, "/chosen/framebuffer");
 		if (framebuffer_off >= 0) {
 			const char *status = fdt_getprop(fdt_data,
 			    framebuffer_off, "status", NULL);
 			if (status == NULL || strncmp(status, "ok", 2) == 0) {
 				fdt_setprop_string(fdt_data, chosen_off,
 				    "stdout-path", "/chosen/framebuffer");
+			}
+		}
 	} else if (match_bootconf_option(boot_args, "console", "serial")) {
 		fdt_setprop_string(fdt_data, chosen_off,
 		    "stdout-path", "serial0:115200n8");
+	}
+}
 #if defined(SOC_MESON8B)
 static void
 meson8b_platform_bootstrap(void)
+{
 #if NARML2CC > 0
 	const bus_space_handle_t pl310_bh = MESON8B_ARM_VBASE + MESON8B_ARM_PL310_BASE;
 	arml2cc_init(&arm_generic_bs_tag, pl310_bh, 0);
 #endif
 	meson_platform_bootstrap();
+}
 static void
 meson8b_platform_reset(void)
+{
 	bus_space_tag_t bst = &meson_bs_tag;
 	bus_space_handle_t bsh;
 	bus_space_map(bst, MESON8B_WATCHDOG_BASE, MESON8B_WATCHDOG_SIZE, 0, &bsh);
 	bus_space_write_4(bst, bsh, MESON8B_WATCHDOG_TC,
 	    MESON8B_WATCHDOG_TC_CPUS | MESON8B_WATCHDOG_TC_ENABLE | __SHIFTIN(0xfff, MESON8B_WATCHDOG_TC_TCNT));
 	bus_space_write_4(bst, bsh, MESON8B_WATCHDOG_RESET, 0);
 	for (;;) {
 		__asm("wfi");
+	}
+}
 #ifdef MULTIPROCESSOR
 static void
 meson8b_mpinit_delay(u_int n)
+{
 	for (volatile int i = 0; i < n; i++)
+		;
+}
 #endif
 static int
 cpu_enable_meson8b(int phandle)
+{
 #ifdef MULTIPROCESSOR
 	const bus_addr_t cbar = armreg_cbar_read();
 	bus_space_tag_t bst = &arm_generic_bs_tag;
 	const bus_space_handle_t scu_bsh =
 	    cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE;
 	const bus_space_handle_t cpuconf_bsh =
 	    MESON8B_SRAM_VBASE + MESON8B_SRAM_CPUCONF_OFFSET;
 	const bus_space_handle_t ao_bsh =
 	    MESON8B_AOBUS_VBASE + MESON8B_AOBUS_RTI_OFFSET;
 	const bus_space_handle_t cbus_bsh =
 	    MESON_CORE_APB3_VBASE + MESON_CBUS_OFFSET;
 	uint32_t pwr_sts, pwr_cntl0, pwr_cntl1, cpuclk, mempd0;
 	uint64_t mpidr;
 	fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
 	const u_int cpuno = __SHIFTOUT(mpidr, MPIDR_AFF0);
 	bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno),
 	    KERN_VTOPHYS((vaddr_t)cpu_mpstart));
 	pwr_sts = bus_space_read_4(bst, scu_bsh, SCU_CPU_PWR_STS);
 	pwr_sts &= ~(3 << (8 * cpuno));
 	bus_space_write_4(bst, scu_bsh, SCU_CPU_PWR_STS, pwr_sts);
 	pwr_cntl0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG);
 	pwr_cntl0 &= ~((3 << 18) << ((cpuno - 1) * 2));
 	bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0);
 	meson8b_mpinit_delay(5000);
 	cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG);
 	cpuclk |= (1 << (24 + cpuno));
 	bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk);
 	mempd0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_MEM_PD0_REG);
 	mempd0 &= ~((uint32_t)(0xf << 28) >> ((cpuno - 1) * 4));
 	bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_MEM_PD0_REG, mempd0);
 	pwr_cntl1 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL1_REG);
 	pwr_cntl1 &= ~((3 << 4) << ((cpuno - 1) * 2));
 	bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL1_REG, pwr_cntl1);
 	meson8b_mpinit_delay(10000);
 	for (;;) {
 		pwr_cntl1 = bus_space_read_4(bst, ao_bsh,
 		    MESON_AOBUS_PWR_CTRL1_REG) & ((1 << 17) << (cpuno - 1));
 		if (pwr_cntl1)
 			break;
 		meson8b_mpinit_delay(10000);
+	}
 	pwr_cntl0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG);
 	pwr_cntl0 &= ~(1 << cpuno);
 	bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0);
 	cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG);
 	cpuclk &= ~(1 << (24 + cpuno));
 	bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk);
 	bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno),
 	    KERN_VTOPHYS((vaddr_t)cpu_mpstart));
 	uint32_t ctrl = bus_space_read_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG);
 	ctrl |= __BITS(cpuno,0);
 	bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG, ctrl);
 #endif
 	return 0;
+}
 ARM_CPU_METHOD(meson8b, "amlogic,meson8b-smp", cpu_enable_meson8b);
 static int
 meson8b_mpstart(void)
+{
 	int ret = 0;
 	const bus_addr_t cbar = armreg_cbar_read();
 	bus_space_tag_t bst = &arm_generic_bs_tag;
 	if (cbar == 0)
 		return ret;
 	const bus_space_handle_t scu_bsh =
 	    cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE;
 	const uint32_t scu_cfg = bus_space_read_4(bst, scu_bsh, SCU_CFG);
 	const u_int ncpus = (scu_cfg & SCU_CFG_CPUMAX) + 1;
 	if (ncpus < 2)
 		return ret;
 	/*
 	 * Invalidate all SCU cache tags. That is, for all cores (0-3)
 	 */
 	bus_space_write_4(bst, scu_bsh, SCU_INV_ALL_REG, 0xffff);
 	uint32_t scu_ctl = bus_space_read_4(bst, scu_bsh, SCU_CTL);
 	scu_ctl |= SCU_CTL_SCU_ENA;
 	bus_space_write_4(bst, scu_bsh, SCU_CTL, scu_ctl);
 	armv7_dcache_wbinv_all();
 	ret = arm_fdt_cpu_mpstart();
 	return ret;
+}
 static const struct arm_platform meson8b_platform = {
 	.ap_devmap = meson_platform_devmap,
 	.ap_bootstrap = meson8b_platform_bootstrap,
 	.ap_init_attach_args = meson_platform_init_attach_args,
 	.ap_device_register = meson8b_platform_device_register,
 	.ap_reset = meson8b_platform_reset,
 	.ap_delay = a9ptmr_delay,
 	.ap_uart_freq = meson_platform_uart_freq,
 	.ap_mpstart = meson8b_mpstart,
 };
 ARM_PLATFORM(meson8b, "amlogic,meson8b", &meson8b_platform);
 #endif	/* SOC_MESON8B */
 #if defined(SOC_MESONGX)
 static void
 mesongx_platform_reset(void)
+{
 	bus_space_tag_t bst = &meson_bs_tag;
 	bus_space_handle_t bsh;
 	uint32_t val;
 	bus_space_map(bst, MESONGX_WATCHDOG_BASE, MESONGX_WATCHDOG_SIZE, 0, &bsh);
 	val = MESONGX_WATCHDOG_CNTL_SYS_RESET_N_EN |
 	      MESONGX_WATCHDOG_CNTL_WDOG_EN |
 	      MESONGX_WATCHDOG_CNTL_CLK_EN;
 	bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_CNTL, val);
 	bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_TCNT, 1);
 	bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_RESET, 0);
 	for (;;) {
 		__asm("wfi");
+	}
+}
 static const struct arm_platform mesongx_platform = {
 	.ap_devmap = meson_platform_devmap,
 	.ap_bootstrap = meson_platform_bootstrap,
 	.ap_init_attach_args = meson_platform_init_attach_args,
 	.ap_device_register = meson_platform_device_register,
 	.ap_reset = mesongx_platform_reset,
 	.ap_delay = gtmr_delay,
 	.ap_uart_freq = meson_platform_uart_freq,
 	.ap_mpstart = arm_fdt_cpu_mpstart,
 };
 #if defined(SOC_MESONGXBB)
 ARM_PLATFORM(mesongxbb, "amlogic,meson-gxbb", &mesongx_platform);
 #endif	/* SOC_MESONGXBB */
 #if defined(SOC_MESONGXL)
 ARM_PLATFORM(mesongxl, "amlogic,meson-gxl", &mesongx_platform);
 #endif	/* SOC_MESONGXL */
 #endif	/* SOC_MESONGX */

 @@ -1,236 +1,238 @@
-/*	$NetBSD: imx6_platform.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $	*/
+/*	$NetBSD: imx6_platform.c,v 1.3 2021/01/29 13:10:07 rin Exp $	*/
 /*-
  * Copyright (c) 2019 Genetec Corporation.  All rights reserved.
  * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx6_platform.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx6_platform.c,v 1.3 2021/01/29 13:10:07 rin Exp $");
 #include "arml2cc.h"
 #include "opt_console.h"
 #include "opt_fdt.h"
 #include "opt_multiprocessor.h"
 #include "opt_soc.h"
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/termios.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/fdt/arm_fdtvar.h>
 #include <uvm/uvm_extern.h>
 #include <arm/arm32/machdep.h>
 #include <machine/bootconfig.h>
 #include <arm/cpufunc.h>
 #include <arm/cortex/a9tmr_var.h>
 #include <arm/cortex/scu_reg.h>
 #include <arm/cortex/gic_reg.h>
 #include <arm/cortex/pl310_var.h>
 #include <arm/nxp/imx6_reg.h>
 #include <arm/nxp/imx6_srcreg.h>
 #include <arm/imx/imxuartreg.h>
 #include <arm/imx/imxwdogreg.h>
 #include <arm/nxp/imx6_platform.h>
 #include <libfdt.h>
 #define	IMX_REF_FREQ	80000000
 #ifdef VERBOSE_INIT_ARM
 #define VPRINTF(...)	printf(__VA_ARGS__)
 #else
 #define VPRINTF(...)	__nothing
 #endif
 extern struct bus_space armv7_generic_bs_tag;
 extern struct arm32_bus_dma_tag arm_generic_dma_tag;
 static const struct pmap_devmap *
 imx_platform_devmap(void)
+{
 	static const struct pmap_devmap devmap[] = {
 		DEVMAP_ENTRY(KERNEL_IO_IOREG_VBASE, IMX6_IOREG_PBASE, IMX6_IOREG_SIZE),
 		DEVMAP_ENTRY(KERNEL_IO_ARMCORE_VBASE, IMX6_ARMCORE_PBASE, IMX6_ARMCORE_SIZE),
 		DEVMAP_ENTRY_END
 	};
 	return devmap;
+}
 static void
 imx_platform_init_attach_args(struct fdt_attach_args *faa)
+{
 	faa->faa_bst = &armv7_generic_bs_tag;
 	faa->faa_dmat = &arm_generic_dma_tag;
+}
 void imx_platform_early_putchar(char);
 void __noasan
 imx_platform_early_putchar(char c)
+{
 #ifdef CONSADDR
 #define CONSADDR_VA	((CONSADDR - IMX6_IOREG_PBASE) + KERNEL_IO_IOREG_VBASE)
 	volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
 	    (volatile uint32_t *)CONSADDR_VA :
 	    (volatile uint32_t *)CONSADDR;
 	while ((le32toh(uartaddr[(IMX_USR2/4)]) & IMX_USR2_TXDC) == 0)
+		;
 	uartaddr[(IMX_UTXD/4)] = htole32(c);
 #endif
+}
 static void
 imx_platform_device_register(device_t self, void *aux)
+{
 	prop_dictionary_t prop = device_properties(self);
 	if (device_is_a(self, "atphy")) {
 		static const struct device_compatible_entry compat_data[] = {
 			{ .compat = "fsl,imx6dl-sabresd" },
 			{ .compat = "fsl,imx6q-sabresd" },
 			{ .compat = "fsl,imx6qp-sabresd" },
 			{ .compat = "solidrun,hummingboard2/q" },
 			{ .compat = "solidrun,hummingboard2/dl" },
 			DEVICE_COMPAT_EOL
 		};
 		if (of_compatible_match(OF_finddevice("/"), compat_data))
 			prop_dictionary_set_uint32(prop, "clk_25m", 125000000);
+	}
+}
 static u_int
 imx_platform_uart_freq(void)
+{
 	return IMX_REF_FREQ;
+}
 static void
 imx_platform_bootstrap(void)
+{
 #if NARML2CC > 0
 	bus_space_tag_t bst = &armv7_generic_bs_tag;
 	bus_space_handle_t bsh;
 	if (bus_space_map(bst, IMX6_ARMCORE_PBASE, IMX6_ARMCORE_SIZE, 0, &bsh))
 		panic("couldn't map armcore registers");
 	arml2cc_init(bst, bsh, ARMCORE_L2C_BASE);
 	bus_space_unmap(bst, bsh, IMX6_ARMCORE_SIZE);
 #endif
 	arm_fdt_cpu_bootstrap();
+}
 static int
 imx_platform_mpstart(void)
+{
 #if defined(MULTIPROCESSOR)
 	bus_space_tag_t bst = &armv7_generic_bs_tag;
 	bus_space_handle_t bsh;
 	if (bus_space_map(bst, IMX6_ARMCORE_PBASE, IMX6_ARMCORE_SIZE, 0, &bsh) != 0)
 		panic("couldn't map armcore registers");
 	/* Enable Snoop Control Unit */
 	bus_space_write_4(bst, bsh, SCU_INV_ALL_REG, 0xff);
 	bus_space_write_4(bst, bsh, SCU_CTL,
 	    bus_space_read_4(bst, bsh, SCU_CTL) | SCU_CTL_SCU_ENA);
 	bus_space_unmap(bst, bsh, AIPS1_SRC_SIZE);
 	if (bus_space_map(bst, IMX6_AIPS1_BASE + AIPS1_SRC_BASE, AIPS1_SRC_SIZE, 0, &bsh) != 0)
 		panic("couldn't map SRC");
 	uint32_t srcctl = bus_space_read_4(bst, bsh, SRC_SCR);
 	const paddr_t mpstart = KERN_VTOPHYS((vaddr_t)cpu_mpstart);
 	srcctl &= ~(SRC_SCR_CORE1_ENABLE | SRC_SCR_CORE2_ENABLE	 |
 	    SRC_SCR_CORE3_ENABLE);
 	bus_space_write_4(bst, bsh, SRC_SCR, srcctl);
 	for (int i = 1; i < arm_cpu_max; i++) {
 		bus_space_write_4(bst, bsh, SRC_GPRN_ENTRY(i), mpstart);
 		srcctl |= SRC_SCR_COREN_RST(i);
 		srcctl |= SRC_SCR_COREN_ENABLE(i);
+	}
 	bus_space_write_4(bst, bsh, SRC_SCR, srcctl);
 	bus_space_unmap(bst, bsh, AIPS1_SRC_SIZE);
 	return arm_fdt_cpu_mpstart();
 #else
 	return 0;
 #endif
+}
 static void
 imx6_platform_reset(void)
+{
 	bus_space_tag_t bst = &armv7_generic_bs_tag;
 	bus_space_handle_t bsh;
 	if (bus_space_map(bst, IMX6_AIPS1_BASE + AIPS1_WDOG1_BASE, AIPS1_WDOG_SIZE, 0, &bsh))
 		panic("couldn't map wdog1 registers");
 	delay(1000);	/* wait for flushing FIFO of serial console */
 	cpsid(I32_bit|F32_bit);
 	/* software reset signal on wdog */
 	bus_space_write_2(bst, bsh, IMX_WDOG_WCR, WCR_WDE);
 	/*
 	 * write twice due to errata.
 	 * Reference: ERR004346: IMX6DQCE Chip Errata for the i.MX 6Dual/6Quad
 	 */
 	bus_space_write_2(bst, bsh, IMX_WDOG_WCR, WCR_WDE);
 	for (;;)
 		__asm("wfi");
+}
 const struct arm_platform imx6_platform = {
 	.ap_devmap = imx_platform_devmap,
 	.ap_bootstrap = imx_platform_bootstrap,
 	.ap_init_attach_args = imx_platform_init_attach_args,
 	.ap_device_register = imx_platform_device_register,
 	.ap_reset = imx6_platform_reset,
 	.ap_delay = a9ptmr_delay,
 	.ap_uart_freq = imx_platform_uart_freq,
 	.ap_mpstart = imx_platform_mpstart,
 };
 ARM_PLATFORM(imx6dl, "fsl,imx6dl", &imx6_platform);
 ARM_PLATFORM(imx6q, "fsl,imx6q", &imx6_platform);
 ARM_PLATFORM(imx6qp, "fsl,imx6qp", &imx6_platform);

 @@ -1,540 +1,541 @@
-/* $NetBSD: ti_gpio.c,v 1.11 2021/01/29 13:07:32 rin Exp $ */
+/* $NetBSD: ti_gpio.c,v 1.12 2021/01/29 13:10:07 rin Exp $ */
 /*-
  * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ti_gpio.c,v 1.11 2021/01/29 13:07:32 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ti_gpio.c,v 1.12 2021/01/29 13:10:07 rin Exp $");
 #include <sys/param.h>
 #include <sys/bitops.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/gpio.h>
 #include <sys/intr.h>
 #include <sys/kmem.h>
 #include <sys/lwp.h>
 #include <sys/mutex.h>
 #include <sys/systm.h>
 #include <dev/fdt/fdtvar.h>
 #include <dev/gpio/gpiovar.h>
 #include <arm/ti/ti_prcm.h>
 #define	TI_GPIO_NPINS			32
 enum ti_gpio_type {
 	TI_GPIO_OMAP3,
 	TI_GPIO_OMAP4,
 	TI_NGPIO
 };
 enum {
 	GPIO_IRQSTATUS1,
 	GPIO_IRQENABLE1,	/* OMAP3 */
 	GPIO_IRQENABLE1_SET,	/* OMAP4 */
 	GPIO_IRQENABLE1_CLR,	/* OMAP4 */
 	GPIO_OE,
 	GPIO_DATAIN,
 	GPIO_DATAOUT,
 	GPIO_LEVELDETECT0,
 	GPIO_LEVELDETECT1,
 	GPIO_RISINGDETECT,
 	GPIO_FALLINGDETECT,
 	GPIO_CLEARDATAOUT,
 	GPIO_SETDATAOUT,
 	GPIO_NREG
 };
 static const u_int ti_gpio_regmap[TI_NGPIO][GPIO_NREG] = {
 	[TI_GPIO_OMAP3] = {
 		[GPIO_IRQSTATUS1]	= 0x18,
 		[GPIO_IRQENABLE1]	= 0x1c,
 		[GPIO_OE]		= 0x34,
 		[GPIO_DATAIN]		= 0x38,
 		[GPIO_DATAOUT]		= 0x3c,
 		[GPIO_LEVELDETECT0]	= 0x40,
 		[GPIO_LEVELDETECT1]	= 0x44,
 		[GPIO_RISINGDETECT]	= 0x48,
 		[GPIO_FALLINGDETECT]	= 0x4c,
 		[GPIO_CLEARDATAOUT]	= 0x90,
 		[GPIO_SETDATAOUT]	= 0x94,
 	},
 	[TI_GPIO_OMAP4] = {
 		[GPIO_IRQSTATUS1]	= 0x2c,
 		[GPIO_IRQENABLE1_SET]	= 0x34,
 		[GPIO_IRQENABLE1_CLR]	= 0x38,
 		[GPIO_OE]		= 0x134,
 		[GPIO_DATAIN]		= 0x138,
 		[GPIO_DATAOUT]		= 0x13c,
 		[GPIO_LEVELDETECT0]	= 0x140,
 		[GPIO_LEVELDETECT1]	= 0x144,
 		[GPIO_RISINGDETECT]	= 0x148,
 		[GPIO_FALLINGDETECT]	= 0x14c,
 		[GPIO_CLEARDATAOUT]	= 0x190,
 		[GPIO_SETDATAOUT]	= 0x194,
 	},
 };
 static const struct device_compatible_entry compat_data[] = {
 	{ .compat = "ti,omap3-gpio",	.value = TI_GPIO_OMAP3 },
 	{ .compat = "ti,omap4-gpio",	.value = TI_GPIO_OMAP4 },
 	DEVICE_COMPAT_EOL
 };
 struct ti_gpio_intr {
 	u_int intr_pin;
 	int (*intr_func)(void *);
 	void *intr_arg;
 	bool intr_mpsafe;
 };
 struct ti_gpio_softc {
 	device_t sc_dev;
 	bus_space_tag_t sc_bst;
 	bus_space_handle_t sc_bsh;
 	kmutex_t sc_lock;
 	enum ti_gpio_type sc_type;
 	const char *sc_modname;
 	void *sc_ih;
 	struct gpio_chipset_tag sc_gp;
 	gpio_pin_t sc_pins[TI_GPIO_NPINS];
 	bool sc_pinout[TI_GPIO_NPINS];
 	struct ti_gpio_intr sc_intr[TI_GPIO_NPINS];
 	device_t sc_gpiodev;
 };
 struct ti_gpio_pin {
 	struct ti_gpio_softc *pin_sc;
 	u_int pin_nr;
 	int pin_flags;
 	bool pin_actlo;
 };
 #define RD4(sc, reg) 		\
     bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, ti_gpio_regmap[(sc)->sc_type][(reg)])
 #define WR4(sc, reg, val) 	\
     bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, ti_gpio_regmap[(sc)->sc_type][(reg)], (val))
 static int	ti_gpio_match(device_t, cfdata_t, void *);
 static void	ti_gpio_attach(device_t, device_t, void *);
 CFATTACH_DECL_NEW(ti_gpio, sizeof(struct ti_gpio_softc),
 	ti_gpio_match, ti_gpio_attach, NULL, NULL);
 static int
 ti_gpio_ctl(struct ti_gpio_softc *sc, u_int pin, int flags)
+{
 	uint32_t oe;
 	KASSERT(mutex_owned(&sc->sc_lock));
 	oe = RD4(sc, GPIO_OE);
 	if (flags & GPIO_PIN_INPUT)
 		oe |= __BIT(pin);
 	else if (flags & GPIO_PIN_OUTPUT)
 		oe &= ~__BIT(pin);
 	WR4(sc, GPIO_OE, oe);
 	sc->sc_pinout[pin] = (flags & GPIO_PIN_OUTPUT) != 0;
 	return 0;
+}
 static void *
 ti_gpio_acquire(device_t dev, const void *data, size_t len, int flags)
+{
 	struct ti_gpio_softc * const sc = device_private(dev);
 	struct ti_gpio_pin *gpin;
 	const u_int *gpio = data;
 	int error;
 	if (len != 12)
 		return NULL;
 	const uint8_t pin = be32toh(gpio[1]) & 0xff;
 	const bool actlo = be32toh(gpio[2]) & 1;
 	if (pin >= __arraycount(sc->sc_pins))
 		return NULL;
 	mutex_enter(&sc->sc_lock);
 	error = ti_gpio_ctl(sc, pin, flags);
 	mutex_exit(&sc->sc_lock);
 	if (error != 0)
 		return NULL;
 	gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP);
 	gpin->pin_sc = sc;
 	gpin->pin_nr = pin;
 	gpin->pin_flags = flags;
 	gpin->pin_actlo = actlo;
 	return gpin;
+}
 static void
 ti_gpio_release(device_t dev, void *priv)
+{
 	struct ti_gpio_softc * const sc = device_private(dev);
 	struct ti_gpio_pin *pin = priv;
 	mutex_enter(&sc->sc_lock);
 	ti_gpio_ctl(pin->pin_sc, pin->pin_nr, GPIO_PIN_INPUT);
 	mutex_exit(&sc->sc_lock);
 	kmem_free(pin, sizeof(*pin));
+}
 static int
 ti_gpio_read(device_t dev, void *priv, bool raw)
+{
 	struct ti_gpio_softc * const sc = device_private(dev);
 	struct ti_gpio_pin *pin = priv;
 	uint32_t data;
 	int val;
 	KASSERT(sc == pin->pin_sc);
 	const uint32_t data_mask = __BIT(pin->pin_nr);
 	/* No lock required for reads */
 	if (sc->sc_pinout[pin->pin_nr])
 		data = RD4(sc, GPIO_DATAOUT);
 	else
 		data = RD4(sc, GPIO_DATAIN);
 	val = __SHIFTOUT(data, data_mask);
 	if (!raw && pin->pin_actlo)
 		val = !val;
 	return val;
+}
 static void
 ti_gpio_write(device_t dev, void *priv, int val, bool raw)
+{
 	struct ti_gpio_softc * const sc = device_private(dev);
 	struct ti_gpio_pin *pin = priv;
 	KASSERT(sc == pin->pin_sc);
 	const uint32_t data_mask = __BIT(pin->pin_nr);
 	if (!raw && pin->pin_actlo)
 		val = !val;
 	const u_int data_reg = val ? GPIO_SETDATAOUT : GPIO_CLEARDATAOUT;
 	WR4(sc, data_reg, data_mask);
+}
 static struct fdtbus_gpio_controller_func ti_gpio_funcs = {
 	.acquire = ti_gpio_acquire,
 	.release = ti_gpio_release,
 	.read = ti_gpio_read,
 	.write = ti_gpio_write,
 };
 static void
 ti_gpio_intr_disestablish(device_t dev, void *ih)
+{
 	struct ti_gpio_softc * const sc = device_private(dev);
 	struct ti_gpio_intr *intr = ih;
 	const u_int pin = intr->intr_pin;
 	const uint32_t pin_mask = __BIT(pin);
 	uint32_t val;
 	/* Disable interrupts */
 	if (sc->sc_type == TI_GPIO_OMAP3) {
 		val = RD4(sc, GPIO_IRQENABLE1);
 		WR4(sc, GPIO_IRQENABLE1, val & ~pin_mask);
 	} else {
 		WR4(sc, GPIO_IRQENABLE1_CLR, pin_mask);
+	}
 	intr->intr_func = NULL;
 	intr->intr_arg = NULL;
+}
 static void *
 ti_gpio_intr_establish(device_t dev, u_int *specifier, int ipl, int flags,
     int (*func)(void *), void *arg, const char *xname)
+{
 	struct ti_gpio_softc * const sc = device_private(dev);
 	uint32_t val;
 	/* 1st cell is the pin */
 	/* 2nd cell is flags */
 	const u_int pin = be32toh(specifier[0]);
 	const u_int type = be32toh(specifier[2]) & 0xf;
 	if (ipl != IPL_VM || pin >= __arraycount(sc->sc_pins))
 		return NULL;
 	/*
 	 * Enabling both high and low level triggers will cause the GPIO
 	 * controller to always assert the interrupt.
 	 */
 	if ((type & (FDT_INTR_TYPE_LOW_LEVEL|FDT_INTR_TYPE_HIGH_LEVEL)) ==
 	    (FDT_INTR_TYPE_LOW_LEVEL|FDT_INTR_TYPE_HIGH_LEVEL))
 		return NULL;
 	if (sc->sc_intr[pin].intr_func != NULL)
 		return NULL;
 	/* Set pin as input */
 	if (ti_gpio_ctl(sc, pin, GPIO_PIN_INPUT) != 0)
 		return NULL;
 	sc->sc_intr[pin].intr_pin = pin;
 	sc->sc_intr[pin].intr_func = func;
 	sc->sc_intr[pin].intr_arg = arg;
 	sc->sc_intr[pin].intr_mpsafe = (flags & FDT_INTR_MPSAFE) != 0;
 	const uint32_t pin_mask = __BIT(pin);
 	/* Configure triggers */
 	val = RD4(sc, GPIO_LEVELDETECT0);
 	if ((type & FDT_INTR_TYPE_LOW_LEVEL) != 0)
 		val |= pin_mask;
 	else
 		val &= ~pin_mask;
 	WR4(sc, GPIO_LEVELDETECT0, val);
 	val = RD4(sc, GPIO_LEVELDETECT1);
 	if ((type & FDT_INTR_TYPE_HIGH_LEVEL) != 0)
 		val |= pin_mask;
 	else
 		val &= ~pin_mask;
 	WR4(sc, GPIO_LEVELDETECT1, val);
 	val = RD4(sc, GPIO_RISINGDETECT);
 	if ((type & FDT_INTR_TYPE_POS_EDGE) != 0)
 		val |= pin_mask;
 	else
 		val &= ~pin_mask;
 	WR4(sc, GPIO_RISINGDETECT, val);
 	val = RD4(sc, GPIO_FALLINGDETECT);
 	if ((type & FDT_INTR_TYPE_NEG_EDGE) != 0)
 		val |= pin_mask;
 	else
 		val &= ~pin_mask;
 	WR4(sc, GPIO_FALLINGDETECT, val);
 	/* Enable interrupts */
 	if (sc->sc_type == TI_GPIO_OMAP3) {
 		val = RD4(sc, GPIO_IRQENABLE1);
 		WR4(sc, GPIO_IRQENABLE1, val | pin_mask);
 	} else {
 		WR4(sc, GPIO_IRQENABLE1_SET, pin_mask);
+	}
 	return &sc->sc_intr[pin];
+}
 static bool
 ti_gpio_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen)
+{
 	struct ti_gpio_softc * const sc = device_private(dev);
 	/* 1st cell is the pin */
 	/* 2nd cell is flags */
 	const u_int pin = be32toh(specifier[0]);
 	if (pin >= __arraycount(sc->sc_pins))
 		return false;
 	snprintf(buf, buflen, "%s pin %d", sc->sc_modname, pin);
 	return true;
+}
 static struct fdtbus_interrupt_controller_func ti_gpio_intrfuncs = {
 	.establish = ti_gpio_intr_establish,
 	.disestablish = ti_gpio_intr_disestablish,
 	.intrstr = ti_gpio_intrstr,
 };
 static int
 ti_gpio_pin_read(void *priv, int pin)
+{
 	struct ti_gpio_softc * const sc = priv;
 	uint32_t data;
 	int val;
 	KASSERT(pin < __arraycount(sc->sc_pins));
 	const uint32_t data_mask = __BIT(pin);
 	data = RD4(sc, GPIO_DATAIN);
 	val = __SHIFTOUT(data, data_mask);
 	return val;
+}
 static void
 ti_gpio_pin_write(void *priv, int pin, int val)
+{
 	struct ti_gpio_softc * const sc = priv;
 	KASSERT(pin < __arraycount(sc->sc_pins));
 	const u_int data_reg = val ? GPIO_SETDATAOUT : GPIO_CLEARDATAOUT;
 	const uint32_t data_mask = __BIT(pin);
 	WR4(sc, data_reg, data_mask);
+}
 static void
 ti_gpio_pin_ctl(void *priv, int pin, int flags)
+{
 	struct ti_gpio_softc * const sc = priv;
 	KASSERT(pin < __arraycount(sc->sc_pins));
 	mutex_enter(&sc->sc_lock);
 	ti_gpio_ctl(sc, pin, flags);
 	mutex_exit(&sc->sc_lock);
+}
 static void
 ti_gpio_attach_ports(struct ti_gpio_softc *sc)
+{
 	struct gpio_chipset_tag *gp = &sc->sc_gp;
 	struct gpiobus_attach_args gba;
 	u_int pin;
 	gp->gp_cookie = sc;
 	gp->gp_pin_read = ti_gpio_pin_read;
 	gp->gp_pin_write = ti_gpio_pin_write;
 	gp->gp_pin_ctl = ti_gpio_pin_ctl;
 	for (pin = 0; pin < __arraycount(sc->sc_pins); pin++) {
 		sc->sc_pins[pin].pin_num = pin;
 		sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
 		sc->sc_pins[pin].pin_state = ti_gpio_pin_read(sc, pin);
+	}
 	memset(&gba, 0, sizeof(gba));
 	gba.gba_gc = gp;
 	gba.gba_pins = sc->sc_pins;
 	gba.gba_npins = __arraycount(sc->sc_pins);
 	sc->sc_gpiodev = config_found_ia(sc->sc_dev, "gpiobus", &gba, NULL);
+}
 static int
 ti_gpio_intr(void *priv)
+{
 	struct ti_gpio_softc * const sc = priv;
 	uint32_t status;
 	u_int bit;
 	int rv = 0;
 	status = RD4(sc, GPIO_IRQSTATUS1);
 	WR4(sc, GPIO_IRQSTATUS1, status);
 	while ((bit = ffs32(status)) != 0) {
 		const u_int pin = bit - 1;
 		const uint32_t pin_mask = __BIT(pin);
 		struct ti_gpio_intr *intr = &sc->sc_intr[pin];
 		status &= ~pin_mask;
 		if (intr->intr_func == NULL)
 			continue;
 		if (!intr->intr_mpsafe)
 			KERNEL_LOCK(1, curlwp);
 		rv |= intr->intr_func(intr->intr_arg);
 		if (!intr->intr_mpsafe)
 			KERNEL_UNLOCK_ONE(curlwp);
+	}
 	return rv;
+}
 static int
 ti_gpio_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_compatible_match(faa->faa_phandle, compat_data);
+}
 static void
 ti_gpio_attach(device_t parent, device_t self, void *aux)
+{
 	struct ti_gpio_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	char intrstr[128];
 	bus_addr_t addr;
 	bus_size_t size;
 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
 		aprint_error(": couldn't get registers\n");
 		return;
+	}
 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
 		aprint_error(": couldn't decode interrupt\n");
 		return;
+	}
 	if (ti_prcm_enable_hwmod(phandle, 0) != 0) {
 		aprint_error(": couldn't enable module\n");
 		return;
+	}
 	sc->sc_dev = self;
 	sc->sc_bst = faa->faa_bst;
 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
 		aprint_error(": couldn't map registers\n");
 		return;
+	}
 	sc->sc_type = of_compatible_lookup(phandle, compat_data)->value;
 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
 	sc->sc_modname = fdtbus_get_string(phandle, "ti,hwmods");
 	if (sc->sc_modname == NULL)
 		sc->sc_modname = fdtbus_get_string(OF_parent(phandle), "ti,hwmods");
 	if (sc->sc_modname == NULL)
 		sc->sc_modname = kmem_asprintf("gpio@%" PRIxBUSADDR, addr);
 	aprint_naive("\n");
 	aprint_normal(": GPIO (%s)\n", sc->sc_modname);
 	fdtbus_register_gpio_controller(self, phandle, &ti_gpio_funcs);
 	ti_gpio_attach_ports(sc);
 	sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM,
 	    FDT_INTR_MPSAFE, ti_gpio_intr, sc, device_xname(self));
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(self, "failed to establish interrupt on %s\n",
 		    intrstr);
 		return;
+	}
 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
 	fdtbus_register_interrupt_controller(self, phandle, &ti_gpio_intrfuncs);
+}