Wed Mar 31 13:41:01 2021 UTC ()
Pull up following revision(s) (requested by skrll in ticket #1238):

	sys/arch/arm/cortex/gic.c: revision 1.47

Only target the boot cpu for real with SPI interrupts.  I tried to do
this back in 2014, but somehow I missed a spot.

This is a quick-and-dirty fix for the USB stack which expects transfer
completions to be in-order.  If interrupts happen across the CPUs then
this isn't guaranteed (yet).

kern/55243 panic at usb_transfer_complete() on raspberry pi 4


(martin)
diff -r1.38 -r1.38.4.1 src/sys/arch/arm/cortex/gic.c
cvs diff -r1.38 -r1.38.4.1 src/sys/arch/arm/cortex/gic.c (expand / switch to unified diff)

--- src/sys/arch/arm/cortex/gic.c 2018/11/16 23:25:09 1.38
+++ src/sys/arch/arm/cortex/gic.c 2021/03/31 13:41:01 1.38.4.1
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: gic.c,v 1.38 2018/11/16 23:25:09 jmcneill Exp $ */ 1/* $NetBSD: gic.c,v 1.38.4.1 2021/03/31 13:41:01 martin Exp $ */
2/*- 2/*-
3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * Copyright (c) 2012 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas of 3am Software Foundry. 7 * by Matt Thomas of 3am Software Foundry.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -24,27 +24,27 @@ @@ -24,27 +24,27 @@
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE. 28 * POSSIBILITY OF SUCH DAMAGE.
29 */ 29 */
30 30
31#include "opt_ddb.h" 31#include "opt_ddb.h"
32#include "opt_multiprocessor.h" 32#include "opt_multiprocessor.h"
33 33
34#define _INTR_PRIVATE 34#define _INTR_PRIVATE
35 35
36#include <sys/cdefs.h> 36#include <sys/cdefs.h>
37__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.38 2018/11/16 23:25:09 jmcneill Exp $"); 37__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.38.4.1 2021/03/31 13:41:01 martin Exp $");
38 38
39#include <sys/param.h> 39#include <sys/param.h>
40#include <sys/bus.h> 40#include <sys/bus.h>
41#include <sys/cpu.h> 41#include <sys/cpu.h>
42#include <sys/device.h> 42#include <sys/device.h>
43#include <sys/evcnt.h> 43#include <sys/evcnt.h>
44#include <sys/intr.h> 44#include <sys/intr.h>
45#include <sys/proc.h> 45#include <sys/proc.h>
46#include <sys/atomic.h> 46#include <sys/atomic.h>
47 47
48#include <arm/armreg.h> 48#include <arm/armreg.h>
49#include <arm/atomic.h> 49#include <arm/atomic.h>
50#include <arm/cpufunc.h> 50#include <arm/cpufunc.h>
@@ -494,27 +494,31 @@ armgic_cpu_update_priorities(struct armg @@ -494,27 +494,31 @@ armgic_cpu_update_priorities(struct armg
494 494
495static void 495static void
496armgic_cpu_init_targets(struct armgic_softc *sc) 496armgic_cpu_init_targets(struct armgic_softc *sc)
497{ 497{
498 /* 498 /*
499 * Update the mpsafe targets 499 * Update the mpsafe targets
500 */ 500 */
501 for (size_t irq = 32; irq < sc->sc_pic.pic_maxsources; irq++) { 501 for (size_t irq = 32; irq < sc->sc_pic.pic_maxsources; irq++) {
502 struct intrsource * const is = sc->sc_pic.pic_sources[irq]; 502 struct intrsource * const is = sc->sc_pic.pic_sources[irq];
503 const bus_size_t targets_reg = GICD_ITARGETSRn(irq / 4); 503 const bus_size_t targets_reg = GICD_ITARGETSRn(irq / 4);
504 if (is != NULL && is->is_mpsafe) { 504 if (is != NULL && is->is_mpsafe) {
505 const u_int byte_shift = 8 * (irq & 3); 505 const u_int byte_shift = 8 * (irq & 3);
506 uint32_t targets = gicd_read(sc, targets_reg); 506 uint32_t targets = gicd_read(sc, targets_reg);
 507#if 0
507 targets |= sc->sc_mptargets << byte_shift; 508 targets |= sc->sc_mptargets << byte_shift;
 509#else
 510 targets |= sc->sc_bptargets << byte_shift;
 511#endif
508 gicd_write(sc, targets_reg, targets); 512 gicd_write(sc, targets_reg, targets);
509 } 513 }
510 } 514 }
511} 515}
512 516
513void 517void
514armgic_cpu_init(struct pic_softc *pic, struct cpu_info *ci) 518armgic_cpu_init(struct pic_softc *pic, struct cpu_info *ci)
515{ 519{
516 struct armgic_softc * const sc = PICTOSOFTC(pic); 520 struct armgic_softc * const sc = PICTOSOFTC(pic);
517 sc->sc_target[cpu_index(ci)] = gicd_find_targets(sc); 521 sc->sc_target[cpu_index(ci)] = gicd_find_targets(sc);
518 atomic_or_32(&sc->sc_mptargets, sc->sc_target[cpu_index(ci)]); 522 atomic_or_32(&sc->sc_mptargets, sc->sc_target[cpu_index(ci)]);
519 KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl); 523 KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl);
520 armgic_cpu_init_priorities(sc); 524 armgic_cpu_init_priorities(sc);