Fri Apr 2 03:20:54 2021 UTC ()
Add bit-field definitions for DCR_SDRAM0_B[0-3]CR registers.


(rin)
diff -r1.3 -r1.4 src/sys/arch/powerpc/include/ibm4xx/dcr4xx.h
cvs diff -r1.3 -r1.4 src/sys/arch/powerpc/include/ibm4xx/dcr4xx.h (expand / switch to unified diff)

--- src/sys/arch/powerpc/include/ibm4xx/dcr4xx.h 2013/11/21 13:33:15 1.3
+++ src/sys/arch/powerpc/include/ibm4xx/dcr4xx.h 2021/04/02 03:20:53 1.4
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: dcr4xx.h,v 1.3 2013/11/21 13:33:15 kiyohara Exp $ */ 1/* $NetBSD: dcr4xx.h,v 1.4 2021/04/02 03:20:53 rin Exp $ */
2 2
3/* 3/*
4 * Copyright 2002 Wasabi Systems, Inc. 4 * Copyright 2002 Wasabi Systems, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Written by Eduardo Horvath for Wasabi Systems, Inc. 7 * Written by Eduardo Horvath for Wasabi Systems, Inc.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -293,26 +293,28 @@ @@ -293,26 +293,28 @@
293/* Indirectly accessed SDRAM Controller DCRs */ 293/* Indirectly accessed SDRAM Controller DCRs */
294 294
295#define DCR_SDRAM0_BESR0 0x00 295#define DCR_SDRAM0_BESR0 0x00
296#define DCR_SDRAM0_BESR1 0x08 296#define DCR_SDRAM0_BESR1 0x08
297#define DCR_SDRAM0_BEAR 0x10 297#define DCR_SDRAM0_BEAR 0x10
298#define DCR_SDRAM0_CFG 0x20 298#define DCR_SDRAM0_CFG 0x20
299#define DCR_SDRAM0_STATUS 0x24 299#define DCR_SDRAM0_STATUS 0x24
300#define DCR_SDRAM0_RTR 0x30 300#define DCR_SDRAM0_RTR 0x30
301#define DCR_SDRAM0_PMIT 0x34 301#define DCR_SDRAM0_PMIT 0x34
302#define DCR_SDRAM0_B0CR 0x40 302#define DCR_SDRAM0_B0CR 0x40
303#define DCR_SDRAM0_B1CR 0x44 303#define DCR_SDRAM0_B1CR 0x44
304#define DCR_SDRAM0_B2CR 0x48 304#define DCR_SDRAM0_B2CR 0x48
305#define DCR_SDRAM0_B3CR 0x4c 305#define DCR_SDRAM0_B3CR 0x4c
 306#define SDRAM0_BnCR_EN 0x00000001
 307#define SDRAM0_BnCR_SZ(n) (1 << ((((n) >> 17) & 7) + 22))
306#define DCR_SDRAM0_TR 0x80 308#define DCR_SDRAM0_TR 0x80
307#define DCR_SDRAM0_ECCCFG 0x94 309#define DCR_SDRAM0_ECCCFG 0x94
308#define DCR_SDRAM0_ECCESR 0x98 310#define DCR_SDRAM0_ECCESR 0x98
309#define SDRAM0_ECCESR_BLCE 0xf0000000 311#define SDRAM0_ECCESR_BLCE 0xf0000000
310#define SDRAM0_ECCESR_CBE 0x00c00000 312#define SDRAM0_ECCESR_CBE 0x00c00000
311#define SDRAM0_ECCESR_CE 0x00200000 313#define SDRAM0_ECCESR_CE 0x00200000
312#define SDRAM0_ECCESR_UE 0x00100000 314#define SDRAM0_ECCESR_UE 0x00100000
313#define SDRAM0_ECCESR_BKE 0x0000f000 315#define SDRAM0_ECCESR_BKE 0x0000f000
314 316
315#define SDRAM0_ECCESR_BLCEN(n) (0x80000000 >> (n)) 317#define SDRAM0_ECCESR_BLCEN(n) (0x80000000 >> (n))
316#define SDRAM0_ECCESR_BKEN(n) (0x00008000 >> (n)) 318#define SDRAM0_ECCESR_BKEN(n) (0x00008000 >> (n))
317#define SDRAM0_ECCESR_CBEN(n) (0x00800000 >> (n)) 319#define SDRAM0_ECCESR_CBEN(n) (0x00800000 >> (n))
318 320