 @@ -1,136 +1,136 @@
-/*	$NetBSD: intr.h,v 1.21 2009/07/08 12:23:10 tsutsui Exp $	*/
+/*	$NetBSD: intr.h,v 1.22 2021/04/02 12:11:41 rin Exp $	*/
 /*-
  * Copyright (c) 1996, 1997, 2007 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Leo Weppelman.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #ifndef _ATARI_INTR_H_
 #define _ATARI_INTR_H_
 #define	IPL_NONE	0		    /* disable no interrupts	    */
 #define	IPL_SOFTCLOCK	1
 #define	IPL_SOFTBIO	2
 #define	IPL_SOFTNET	3
 #define	IPL_SOFTSERIAL	4
 #define	IPL_VM		5
 #define	IPL_SCHED	6
 #define	IPL_HIGH	7
 #define	NIPL		8
 #define	IST_UNUSABLE	-1	/* interrupt cannot be used	*/
 #define	IST_NONE	0	/* none (dummy)			*/
 #define	IST_PULSE	1	/* pulsed			*/
 #define	IST_EDGE	2	/* edge-triggered		*/
 #define	IST_LEVEL	3	/* level-triggered		*/
 /*
  * spl functions; all but spl0 are done in-line
  */
 #include <machine/psl.h>
 /* spl0 requires checking for software interrupts */
 #define splsoftclock()		splraise1()
 #define splsoftbio()		splraise1()
 #define splsoftnet()		splraise1()
 #define splsoftserial()		splraise1()
 #define splvm()			splraise4()
 #define splsched()		splraise6()
 #define splhigh()		spl7()
 #define splx(s)			((s) & PSL_IPL ? _spl(s) : spl0())
 #ifdef _KERNEL
 int spl0(void);
 extern const uint16_t ipl2psl_table[NIPL];
 extern int idepth;
 typedef int ipl_t;
 typedef struct {
 	uint16_t _psl;
 } ipl_cookie_t;
 static inline ipl_cookie_t
 makeiplcookie(ipl_t ipl)
+{
 	return (ipl_cookie_t){._psl = ipl2psl_table[ipl]};
+}
 static inline int
 splraiseipl(ipl_cookie_t icookie)
+{
 	return _splraise(icookie._psl);
+}
 #include <sys/queue.h>
 #include <machine/cpu.h>	/* XXX: for clockframe */
 struct clockframe;
 #define	AUTO_VEC	0x0001	/* We're dealing with an auto-vector	*/
 #define	USER_VEC	0x0002	/* We're dealing with an user-vector	*/
 #define	FAST_VEC	0x0010	/* Fast, stash right into vector-table	*/
 #define	ARG_CLOCKFRAME	0x0020	/* Supply clockframe as an argument	*/
 /*
  * Interrupt handler chains.  intr_establish() inserts a handler into
  * the list.  The handler is called with its (single) argument or with a
  * 'standard' clockframe. This depends on 'ih_type'.
  */
 typedef int	(*hw_ifun_t)(void *, int);
 struct intrhand {
 	LIST_ENTRY(intrhand)	ih_link;
 	hw_ifun_t		ih_fun;
 	void			*ih_arg;
 	int			ih_type;
 	int			ih_pri;
 	int			ih_vector;
-	u_long			*ih_intrcnt;
+	u_int			*ih_intrcnt;
 };
 void		intr_init(void);
 struct intrhand *intr_establish(int, int, int, hw_ifun_t, void *);
 int		intr_disestablish(struct intrhand *);
 void		intr_dispatch(struct clockframe);
 void		intr_glue(void);
 /*
  * Exported by intrcnt.h
  */
 extern u_long	autovects[];
-extern u_long	intrcnt_auto[];
+extern u_int	intrcnt_auto[];
 extern u_long	uservects[];
-extern u_long	intrcnt_user[];
+extern u_int	intrcnt_user[];
 #endif /* _KERNEL */
 #endif /* _ATARI_INTR_H_ */

 @@ -1,218 +1,218 @@
-/*	$NetBSD: isr.c,v 1.18 2020/11/18 03:40:50 thorpej Exp $	*/
+/*	$NetBSD: isr.c,v 1.19 2021/04/02 12:11:41 rin Exp $	*/
 /*-
  * Copyright (c) 1996 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Adam Glass, Gordon W. Ross, and Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Link and dispatch interrupts.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: isr.c,v 1.18 2020/11/18 03:40:50 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: isr.c,v 1.19 2021/04/02 12:11:41 rin Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/queue.h>
 #include <sys/kmem.h>
 #include <sys/vmmeter.h>
 #include <sys/cpu.h>
 #include <uvm/uvm_extern.h>
 #include <cesfic/cesfic/isr.h>
 typedef LIST_HEAD(, isr) isr_list_t;
 isr_list_t isr_list[NISR];
-extern	int intrcnt[];		/* from locore.s */
+extern	u_int intrcnt[];	/* from locore.s */
 void
 isrinit(void)
+{
 	int i;
 	/* Initialize the ISR lists. */
 	for (i = 0; i < NISR; ++i) {
 		LIST_INIT(&isr_list[i]);
+	}
+}
 /*
  * Establish an interrupt handler.
  * Called by driver attach functions.
  */
 void *
 isrlink(int (*func)(void *), void *arg, int ipl, int priority)
+{
 	struct isr *newisr, *curisr;
 	isr_list_t *list;
 	if ((ipl < 0) || (ipl >= NISR))
 		panic("isrlink: bad ipl %d", ipl);
 	newisr = kmem_alloc(sizeof(*newisr), KM_SLEEP);
 	newisr->isr_func = func;
 	newisr->isr_arg = arg;
 	newisr->isr_ipl = ipl;
 	newisr->isr_priority = priority;
 	/*
 	 * Some devices are particularly sensitive to interrupt
 	 * handling latency.  The DCA, for example, can lose many
 	 * characters if its interrupt isn't handled with reasonable
 	 * speed.
+	 *
 	 * To work around this problem, each device can give itself a
 	 * "priority".  An unbuffered DCA would give itself a higher
 	 * priority than a SCSI device, for example.
+	 *
 	 * This is necessary because of the flat spl scheme employed by
 	 * the hp300.  Each device can be set from ipl 3 to ipl 5, which
 	 * in turn means that splbio, splnet, and spltty must all be at
 	 * spl5.
+	 *
 	 * Don't blame me...I just work here.
 	 */
 	/*
 	 * Get the appropriate ISR list.  If the list is empty, no
 	 * additional work is necessary; we simply insert ourselves
 	 * at the head of the list.
 	 */
 	list = &isr_list[ipl];
 	if (list->lh_first == NULL) {
 		LIST_INSERT_HEAD(list, newisr, isr_link);
 		goto done;
+	}
 	/*
 	 * A little extra work is required.  We traverse the list
 	 * and place ourselves after any ISRs with our current (or
 	 * higher) priority.
 	 */
 	for (curisr = list->lh_first; curisr->isr_link.le_next != NULL;
 	    curisr = curisr->isr_link.le_next) {
 		if (newisr->isr_priority > curisr->isr_priority) {
 			LIST_INSERT_BEFORE(curisr, newisr, isr_link);
 			goto done;
+		}
+	}
 	/*
 	 * We're the least important entry, it seems.  We just go
 	 * on the end.
 	 */
 	LIST_INSERT_AFTER(curisr, newisr, isr_link);
  done:
 	return (newisr);
+}
 #if 0
 /*
  * Disestablish an interrupt handler.
  */
 void
 isrunlink(void *arg)
+{
 	struct isr *isr = arg;
 	LIST_REMOVE(isr, isr_link);
 	kmem_free(isr, sizeof(*isr));
+}
 #endif
 /*
  * This is the dispatcher called by the low-level
  * assembly language interrupt routine.
  */
 static unsigned int idepth;
 void
 isrdispatch(int evec)
 	/* evec:		 format | vector offset */
+{
 	struct isr *isr;
 	isr_list_t *list;
 	int handled, ipl, vec;
 	static int straycount, unexpected;
 	vec = (evec & 0xfff) >> 2;
 	if ((vec < ISRLOC) || (vec >= (ISRLOC + NISR)))
 		panic("isrdispatch: bad vec 0x%x", vec);
 	ipl = vec - ISRLOC;
 	intrcnt[ipl]++;
 	curcpu()->ci_data.cpu_nintr++;
 	if (ipl >= IPL_VM)
 		idepth++;
 	list = &isr_list[ipl];
 	if (list->lh_first == NULL) {
 		printf("intrhand: ipl %d unexpected\n", ipl);
 		if (++unexpected > 10)
 			panic("isrdispatch: too many unexpected interrupts");
 		goto out;
+	}
 	handled = 0;
 	/* Give all the handlers a chance. */
 	for (isr = list->lh_first ; isr != NULL; isr = isr->isr_link.le_next)
 		handled |= (*isr->isr_func)(isr->isr_arg);
 	if (handled)
 		straycount = 0;
 	else if (++straycount > 50)
 		panic("isrdispatch: too many stray interrupts");
 	else
 		printf("isrdispatch: stray level %d interrupt\n", ipl);
  out:
 	if (ipl >= IPL_VM)
 		idepth--;
+}
 bool
 cpu_intr_p(void)
+{
 	return idepth != 0;
+}
 const uint16_t ipl2psl_table[NIPL] = {
 	[IPL_NONE]       = PSL_S|PSL_IPL0,
 	[IPL_SOFTCLOCK]  = PSL_S|PSL_IPL1,
 	[IPL_SOFTBIO]    = PSL_S|PSL_IPL1,
 	[IPL_SOFTNET]    = PSL_S|PSL_IPL1,
 	[IPL_SOFTSERIAL] = PSL_S|PSL_IPL1,
 	[IPL_VM]         = PSL_S|PSL_IPL4,
 	[IPL_SCHED]      = PSL_S|PSL_IPL6,
 	[IPL_HIGH]       = PSL_S|PSL_IPL7,
 };

 @@ -1,279 +1,279 @@
-/*	$NetBSD: isr.c,v 1.24 2020/12/19 21:38:30 thorpej Exp $	*/
+/*	$NetBSD: isr.c,v 1.25 2021/04/02 12:11:41 rin Exp $	*/
 /*-
  * Copyright (c) 1996 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Adam Glass, Gordon W. Ross, and Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: isr.c,v 1.24 2020/12/19 21:38:30 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: isr.c,v 1.25 2021/04/02 12:11:41 rin Exp $");
 /*
  * Link and dispatch interrupts.
  */
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kmem.h>
 #include <sys/vmmeter.h>
 #include <sys/cpu.h>
 #include <uvm/uvm_extern.h>
 #include <luna68k/luna68k/isr.h>
 isr_autovec_list_t isr_autovec[NISRAUTOVEC];
 struct	isr_vectored isr_vectored[NISRVECTORED];
 int	idepth;
-extern	int intrcnt[];		/* from locore.s */
+extern	u_int intrcnt[];	/* from locore.s */
 extern	void (*vectab[])(void);
 extern	void badtrap(void);
 extern	void intrhand_vectored(void);
 extern	int getsr(void);	/* in locore.s */
 void
 isrinit(void)
+{
 	int i;
 	/* Initialize the autovector lists. */
 	for (i = 0; i < NISRAUTOVEC; ++i) {
 		LIST_INIT(&isr_autovec[i]);
+	}
+}
 /*
  * Establish an autovectored interrupt handler.
  * Called by driver attach functions.
  */
 void
 isrlink_autovec(int (*func)(void *), void *arg, int ipl, int priority)
+{
 	struct isr_autovec *newisr, *curisr;
 	isr_autovec_list_t *list;
 	if ((ipl < 0) || (ipl >= NISRAUTOVEC))
 		panic("isrlink_autovec: bad ipl %d", ipl);
 	newisr = kmem_alloc(sizeof(*newisr), KM_SLEEP);
 	newisr->isr_func = func;
 	newisr->isr_arg = arg;
 	newisr->isr_ipl = ipl;
 	newisr->isr_priority = priority;
 	/*
 	 * Some devices are particularly sensitive to interrupt
 	 * handling latency.  The SCC, for example, can lose many
 	 * characters if its interrupt isn't handled with reasonable
 	 * speed.
+	 *
 	 * To work around this problem, each device can give itself a
 	 * "priority".  An unbuffered SCC would give itself a higher
 	 * priority than a SCSI device, for example.
+	 *
 	 * This solution was originally developed for the hp300, which
 	 * has a flat spl scheme (by necessity).  Thankfully, the
 	 * MVME systems don't have this problem, though this may serve
 	 * a useful purpose in any case.
 	 */
 	/*
 	 * Get the appropriate ISR list.  If the list is empty, no
 	 * additional work is necessary; we simply insert ourselves
 	 * at the head of the list.
 	 */
 	list = &isr_autovec[ipl];
 	if (list->lh_first == NULL) {
 		LIST_INSERT_HEAD(list, newisr, isr_link);
 		return;
+	}
 	/*
 	 * A little extra work is required.  We traverse the list
 	 * and place ourselves after any ISRs with our current (or
 	 * higher) priority.
 	 */
 	for (curisr = list->lh_first; curisr->isr_link.le_next != NULL;
 	    curisr = curisr->isr_link.le_next) {
 		if (newisr->isr_priority > curisr->isr_priority) {
 			LIST_INSERT_BEFORE(curisr, newisr, isr_link);
 			return;
+		}
+	}
 	/*
 	 * We're the least important entry, it seems.  We just go
 	 * on the end.
 	 */
 	LIST_INSERT_AFTER(curisr, newisr, isr_link);
+}
 /*
  * Establish a vectored interrupt handler.
  * Called by bus interrupt establish functions.
  */
 void
 isrlink_vectored(int (*func)(void *), void *arg, int ipl, int vec)
+{
 	struct isr_vectored *isr;
 	if ((ipl < 0) || (ipl >= NISRAUTOVEC))
 		panic("isrlink_vectored: bad ipl %d", ipl);
 	if ((vec < ISRVECTORED) || (vec >= ISRVECTORED + NISRVECTORED))
 		panic("isrlink_vectored: bad vec 0x%x", vec);
 	isr = &isr_vectored[vec - ISRVECTORED];
 	if ((vectab[vec] != badtrap) || (isr->isr_func != NULL))
 		panic("isrlink_vectored: vec 0x%x not available", vec);
 	/* Fill in the new entry. */
 	isr->isr_func = func;
 	isr->isr_arg = arg;
 	isr->isr_ipl = ipl;
 	/* Hook into the vector table. */
 	vectab[vec] = intrhand_vectored;
+}
 /*
  * Unhook a vectored interrupt.
  */
 void
 isrunlink_vectored(int vec)
+{
 	if ((vec < ISRVECTORED) || (vec >= ISRVECTORED + NISRVECTORED))
 		panic("isrunlink_vectored: bad vec 0x%x", vec);
 	if (vectab[vec] != intrhand_vectored)
 		panic("isrunlink_vectored: not vectored interrupt");
 	vectab[vec] = badtrap;
 	memset(&isr_vectored[vec - ISRVECTORED], 0, sizeof(struct isr_vectored));
+}
 /*
  * This is the dispatcher called by the low-level
  * assembly language autovectored interrupt routine.
  */
 void
 isrdispatch_autovec(int evec)
 	/* evec:		 format | vector offset */
+{
 	struct isr_autovec *isr;
 	isr_autovec_list_t *list;
 	int handled = 0, ipl, vec;
 	static int straycount, unexpected;
 	idepth++;
 	vec = (evec & 0xfff) >> 2;
 	if ((vec < ISRAUTOVEC) || (vec >= (ISRAUTOVEC + NISRAUTOVEC)))
 		panic("isrdispatch_autovec: bad vec 0x%x", vec);
 	ipl = vec - ISRAUTOVEC;
 	intrcnt[ipl]++;
 	curcpu()->ci_data.cpu_nintr++;
 	list = &isr_autovec[ipl];
 	if (list->lh_first == NULL) {
 		printf("isrdispatch_autovec: ipl %d unexpected\n", ipl);
 		if (++unexpected > 10)
 			panic("too many unexpected interrupts");
 		idepth--;
 		return;
+	}
 	/* Give all the handlers a chance. */
 	for (isr = list->lh_first ; isr != NULL; isr = isr->isr_link.le_next)
 		handled |= (*isr->isr_func)(isr->isr_arg);
 	if (handled)
 		straycount = 0;
 	else if (++straycount > 50)
 		panic("isr_dispatch_autovec: too many stray interrupts");
 	else
 		printf("isrdispatch_autovec: stray level %d interrupt\n", ipl);
 	idepth--;
+}
 /*
  * This is the dispatcher called by the low-level
  * assembly language vectored interrupt routine.
  */
 void
 isrdispatch_vectored(int pc, int evec, void *frame)
+{
 	struct isr_vectored *isr;
 	int ipl, vec;
 	idepth++;
 	vec = (evec & 0xfff) >> 2;
 	ipl = (getsr() >> 8) & 7;
 	intrcnt[ipl]++;
 	curcpu()->ci_data.cpu_nintr++;
 	if ((vec < ISRVECTORED) || (vec >= (ISRVECTORED + NISRVECTORED)))
 		panic("isrdispatch_vectored: bad vec 0x%x", vec);
 	isr = &isr_vectored[vec - ISRVECTORED];
 	if (isr->isr_func == NULL) {
 		printf("isrdispatch_vectored: no handler for vec 0x%x\n", vec);
 		vectab[vec] = badtrap;
 		idepth--;
 		return;
+	}
 	/*
 	 * Handler gets exception frame if argument is NULL.
 	 */
 	if ((*isr->isr_func)(isr->isr_arg ? isr->isr_arg : frame) == 0)
 		printf("isrdispatch_vectored: vec 0x%x not claimed\n", vec);
 	idepth--;
+}
 bool
 cpu_intr_p(void)
+{
 	return idepth != 0;
+}
 const uint16_t ipl2psl_table[NIPL] = {
 	[IPL_NONE]       = PSL_S|PSL_IPL0,
 	[IPL_SOFTCLOCK]  = PSL_S|PSL_IPL1,
 	[IPL_SOFTBIO]    = PSL_S|PSL_IPL1,
 	[IPL_SOFTNET]    = PSL_S|PSL_IPL1,
 	[IPL_SOFTSERIAL] = PSL_S|PSL_IPL1,
 	[IPL_VM]         = PSL_S|PSL_IPL4,
 	[IPL_SCHED]      = PSL_S|PSL_IPL5,
 	[IPL_HIGH]       = PSL_S|PSL_IPL7,
 };

 @@ -1,259 +1,259 @@
-/*	$NetBSD: intr.c,v 1.31 2020/07/21 06:10:26 rin Exp $	*/
+/*	$NetBSD: intr.c,v 1.32 2021/04/02 12:11:41 rin Exp $	*/
 /*-
  * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Adam Glass, Gordon W. Ross, and Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Link and dispatch interrupts.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.31 2020/07/21 06:10:26 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.32 2021/04/02 12:11:41 rin Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/malloc.h>
 #include <sys/vmmeter.h>
 #include <sys/cpu.h>
 #include <sys/intr.h>
 #include <machine/psc.h>
 #include <machine/viareg.h>
 #define	NISR	8
 #define	ISRLOC	0x18
 static int intr_noint(void *);
 static int ((*intr_func[NISR])(void *)) = {
 	intr_noint,
 	intr_noint,
 	intr_noint,
 	intr_noint,
 	intr_noint,
 	intr_noint,
 	intr_noint,
 	intr_noint
 };
 static void *intr_arg[NISR] = {
 	(void *)0,
 	(void *)1,
 	(void *)2,
 	(void *)3,
 	(void *)4,
 	(void *)5,
 	(void *)6,
 	(void *)7
 };
 #ifdef DEBUG
 int	intr_debug = 0;
 #endif
 /*
  * Some of the below are not used yet, but might be used someday on the
  * IIfx/Q700/900/950/etc. where the interrupt controller may be reprogrammed
  * to interrupt on different levels as listed in locore.s
  */
 uint16_t ipl2psl_table[NIPL];
 int idepth;
 volatile int ssir;
-extern	int intrcnt[];		/* from locore.s */
+extern	u_int intrcnt[];	/* from locore.s */
 void	intr_computeipl(void);
 #define MAX_INAME_LENGTH 53
 #define STD_INAMES \
 	"spur\0via1\0via2\0unused1\0scc\0unused2\0unused3\0nmi\0clock\0"
 #define AUX_INAMES \
 	"spur\0soft\0via2\0ethernet\0scc\0sound\0via1\0nmi\0clock\0    "
 #define AV_INAMES \
 	"spur\0via1\0via2\0ethernet\0scc\0dsp\0unused1\0nmi\0clock\0   "
 void
 intr_init(void)
+{
 	extern char	intrnames[MAX_INAME_LENGTH];
 	extern char	eintrnames[] __diagused;
 	const char	*inames;
 	ipl2psl_table[IPL_NONE]       = 0;
 	ipl2psl_table[IPL_SOFTCLOCK]  = PSL_S|PSL_IPL1;
 	ipl2psl_table[IPL_SOFTNET]    = PSL_S|PSL_IPL1;
 	ipl2psl_table[IPL_SOFTSERIAL] = PSL_S|PSL_IPL1;
 	ipl2psl_table[IPL_SOFTBIO]    = PSL_S|PSL_IPL1;
 	ipl2psl_table[IPL_HIGH]       = PSL_S|PSL_IPL7;
 	if (mac68k_machine.aux_interrupts) {
 		inames = AUX_INAMES;
 		/* Standard spl(9) interrupt priorities */
 		ipl2psl_table[IPL_VM]        = (PSL_S | PSL_IPL6);
 		ipl2psl_table[IPL_SCHED]     = (PSL_S | PSL_IPL6);
 	} else {
 		inames = STD_INAMES;
 		/* Standard spl(9) interrupt priorities */
 		ipl2psl_table[IPL_VM]        = (PSL_S | PSL_IPL2);
 		ipl2psl_table[IPL_SCHED]     = (PSL_S | PSL_IPL3);
 		if (current_mac_model->class == MACH_CLASSAV) {
 			inames = AV_INAMES;
 			ipl2psl_table[IPL_VM]    = (PSL_S | PSL_IPL4);
 			ipl2psl_table[IPL_SCHED] = (PSL_S | PSL_IPL4);
+		}
+	}
 	KASSERT(MAX_INAME_LENGTH <=
 		((uintptr_t)eintrnames - (uintptr_t)intrnames));
 	memcpy(intrnames, inames, MAX_INAME_LENGTH);
 	intr_computeipl();
 	/* Initialize the VIAs */
 	via_init();
 	/* Initialize the PSC (if present) */
 	psc_init();
+}
 /*
  * Compute the interrupt levels for the spl*()
  * calls.  This doesn't have to be fast.
  */
 void
 intr_computeipl(void)
+{
 	/*
 	 * Enforce the following relationship, as defined in spl(9):
 	 * `bio <= net <= tty <= vm <= statclock <= clock <= sched <= serial'
 	 */
 	if (ipl2psl_table[IPL_VM] > ipl2psl_table[IPL_SCHED])
 		ipl2psl_table[IPL_SCHED] = ipl2psl_table[IPL_VM];
 	if (ipl2psl_table[IPL_SCHED] > ipl2psl_table[IPL_HIGH])
 		ipl2psl_table[IPL_HIGH] = ipl2psl_table[IPL_SCHED];
+}
 /*
  * Establish an autovectored interrupt handler.
  * Called by driver attach functions.
+ *
  * XXX Warning!  DO NOT use Macintosh ROM traps from an interrupt handler
  * established by this routine, either directly or indirectly, without
  * properly saving and restoring all registers.  If not, chaos _will_
  * ensue!  (sar 19980806)
  */
 void
 intr_establish(int (*func)(void *), void *arg, int ipl)
+{
 	if ((ipl < 0) || (ipl >= NISR))
 		panic("intr_establish: bad ipl %d", ipl);
 #ifdef DIAGNOSTIC
 	if (intr_func[ipl] != intr_noint)
 		printf("intr_establish: attempt to share ipl %d\n", ipl);
 #endif
 	intr_func[ipl] = func;
 	intr_arg[ipl] = arg;
+}
 /*
  * Disestablish an interrupt handler.
  */
 void
 intr_disestablish(int ipl)
+{
 	if ((ipl < 0) || (ipl >= NISR))
 		panic("intr_disestablish: bad ipl %d", ipl);
 	intr_func[ipl] = intr_noint;
 	intr_arg[ipl] = (void *)ipl;
+}
 /*
  * This is the dispatcher called by the low-level
  * assembly language interrupt routine.
+ *
  * XXX Note: see the warning in intr_establish()
  */
 #if __GNUC_PREREQ__(8, 0)
 /*
  * XXX rtclock_intr() requires this for unwinding stack frame.
  */
 #pragma GCC push_options
 #pragma GCC optimize "-fno-omit-frame-pointer"
 #endif
 void
 intr_dispatch(int evec)		/* format | vector offset */
+{
 	int ipl, vec;
 	idepth++;
 	vec = (evec & 0xfff) >> 2;
 #ifdef DIAGNOSTIC
 	if ((vec < ISRLOC) || (vec >= (ISRLOC + NISR)))
 		panic("intr_dispatch: bad vec 0x%x", vec);
 #endif
 	ipl = vec - ISRLOC;
 	intrcnt[ipl]++;
 	curcpu()->ci_data.cpu_nintr++;
 	(void)(*intr_func[ipl])(intr_arg[ipl]);
 	idepth--;
+}
 #if __GNUC_PREREQ__(8, 0)
 #pragma GCC pop_options
 #endif
 /*
  * Default interrupt handler:  do nothing.
  */
 static int
 intr_noint(void *arg)
+{
 #ifdef DEBUG
 	idepth++;
 	if (intr_debug)
 		printf("intr_noint: ipl %d\n", (int)arg);
 	idepth--;
 #endif
 	return 0;
+}
 bool
 cpu_intr_p(void)
+{
 	return idepth != 0;
+}

 @@ -1,342 +1,342 @@
-/*	$NetBSD: isr.c,v 1.35 2020/11/21 17:59:13 thorpej Exp $	*/
+/*	$NetBSD: isr.c,v 1.36 2021/04/02 12:11:41 rin Exp $	*/
 /*-
  * Copyright (c) 1996 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Adam Glass, Gordon W. Ross, and Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Link and dispatch interrupts.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: isr.c,v 1.35 2020/11/21 17:59:13 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: isr.c,v 1.36 2021/04/02 12:11:41 rin Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kmem.h>
 #include <sys/vmmeter.h>
 #include <sys/device.h>
 #include <sys/cpu.h>
 #include <uvm/uvm_extern.h>
 #include <mvme68k/mvme68k/isr.h>
 volatile unsigned int interrupt_depth;
 isr_autovec_list_t isr_autovec[NISRAUTOVEC];
 struct	isr_vectored isr_vectored[NISRVECTORED];
 static const char irqgroupname[] = "hard irqs";
 struct	evcnt mvme68k_irq_evcnt[] = {
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "spur"),
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "lev1"),
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "lev2"),
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "lev3"),
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "lev4"),
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "lev5"),
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "lev6"),
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "nmi")
 };
 static int idepth;
-extern	int intrcnt[];		/* from locore.s. XXXSCW: will go away soon */
+extern	u_int intrcnt[];	/* from locore.s. XXXSCW: will go away soon */
 extern	void (*vectab[])(void);
 extern	void badtrap(void);
 extern	void intrhand_vectored(void);
 static	int spurintr(void *);
 void
 isrinit(void)
+{
 	int i;
 	/* Initialize the autovector lists. */
 	for (i = 0; i < NISRAUTOVEC; ++i)
 		LIST_INIT(&isr_autovec[i]);
 	/* Initialise the interrupt event counts */
 	for (i = 0; i < (sizeof(mvme68k_irq_evcnt) / sizeof(struct evcnt)); i++)
 		evcnt_attach_static(&mvme68k_irq_evcnt[i]);
 	/* Arrange to trap Spurious and NMI auto-vectored Interrupts */
 	isrlink_autovec(spurintr, NULL, 0, 0, NULL);
 	isrlink_autovec(nmihand, NULL, 7, 0, NULL);
+}
 /*
  * Establish an autovectored interrupt handler.
  * Called by driver attach functions.
  */
 void
 isrlink_autovec(int (*func)(void *), void *arg, int ipl, int priority,
     struct evcnt *evcnt)
+{
 	struct isr_autovec *newisr, *curisr;
 	isr_autovec_list_t *list;
 #ifdef DIAGNOSTIC
 	if ((ipl < 0) || (ipl >= NISRAUTOVEC))
 		panic("%s: bad ipl %d", __func__, ipl);
 #endif
 	newisr = kmem_alloc(sizeof(*newisr), KM_SLEEP);
 	newisr->isr_func = func;
 	newisr->isr_arg = arg;
 	newisr->isr_ipl = ipl;
 	newisr->isr_priority = priority;
 	newisr->isr_evcnt = evcnt;
 	/*
 	 * Some devices are particularly sensitive to interrupt
 	 * handling latency.  The SCC, for example, can lose many
 	 * characters if its interrupt isn't handled with reasonable
 	 * speed.
+	 *
 	 * To work around this problem, each device can give itself a
 	 * "priority".  An unbuffered SCC would give itself a higher
 	 * priority than a SCSI device, for example.
+	 *
 	 * This solution was originally developed for the hp300, which
 	 * has a flat spl scheme (by necessity).  Thankfully, the
 	 * MVME systems don't have this problem, though this may serve
 	 * a useful purpose in any case.
 	 */
 	/*
 	 * Get the appropriate ISR list.  If the list is empty, no
 	 * additional work is necessary; we simply insert ourselves
 	 * at the head of the list.
 	 */
 	list = &isr_autovec[ipl];
 	if (list->lh_first == NULL) {
 		LIST_INSERT_HEAD(list, newisr, isr_link);
 		return;
+	}
 	/*
 	 * A little extra work is required.  We traverse the list
 	 * and place ourselves after any ISRs with our current (or
 	 * higher) priority.
 	 */
 	for (curisr = list->lh_first; curisr->isr_link.le_next != NULL;
 	    curisr = curisr->isr_link.le_next) {
 		if (newisr->isr_priority > curisr->isr_priority) {
 			LIST_INSERT_BEFORE(curisr, newisr, isr_link);
 			return;
+		}
+	}
 	/*
 	 * We're the least important entry, it seems.  We just go
 	 * on the end.
 	 */
 	LIST_INSERT_AFTER(curisr, newisr, isr_link);
+}
 /*
  * Establish a vectored interrupt handler.
  * Called by bus interrupt establish functions.
  */
 void
 isrlink_vectored(int (*func)(void *), void *arg, int ipl, int vec,
     struct evcnt *evcnt)
+{
 	struct isr_vectored *isr;
 #ifdef DIAGNOSTIC
 	if ((ipl < 0) || (ipl >= NISRAUTOVEC))
 		panic("%s: bad ipl %d", __func__, ipl);
 	if ((vec < ISRVECTORED) || (vec >= ISRVECTORED + NISRVECTORED))
 		panic("%s: bad vec 0x%x", __func__, vec);
 #endif
 	isr = &isr_vectored[vec - ISRVECTORED];
 #ifdef DIAGNOSTIC
 	if ((vectab[vec] != badtrap) || (isr->isr_func != NULL))
 		panic("%s: vec 0x%x not available", __func__, vec);
 #endif
 	/* Fill in the new entry. */
 	isr->isr_func = func;
 	isr->isr_arg = arg;
 	isr->isr_ipl = ipl;
 	isr->isr_evcnt = evcnt;
 	/* Hook into the vector table. */
 	vectab[vec] = intrhand_vectored;
+}
 /*
  * Return a pointer to the evcnt structure for
  * the specified ipl.
  */
 struct evcnt *
 isrlink_evcnt(int ipl)
+{
 #ifdef DIAGNOSTIC
 	if (ipl < 0 ||
 	    ipl >= (sizeof(mvme68k_irq_evcnt) / sizeof(struct evcnt)))
 		panic("%s: bad ipl %d", __func__, ipl);
 #endif
 	return &mvme68k_irq_evcnt[ipl];
+}
 /*
  * Unhook a vectored interrupt.
  */
 void
 isrunlink_vectored(int vec)
+{
 #ifdef DIAGNOSTIC
 	if ((vec < ISRVECTORED) || (vec >= ISRVECTORED + NISRVECTORED))
 		panic("%s: bad vec 0x%x", __func__, vec);
 	if (vectab[vec] != intrhand_vectored)
 		panic("%s: not vectored interrupt", __func__);
 #endif
 	vectab[vec] = badtrap;
 	memset(&isr_vectored[vec - ISRVECTORED], 0,
 	    sizeof(struct isr_vectored));
+}
 /*
  * This is the dispatcher called by the low-level
  * assembly language autovectored interrupt routine.
  */
 void
 isrdispatch_autovec(struct clockframe *frame)
+{
 	struct isr_autovec *isr;
 	isr_autovec_list_t *list;
 	int handled, ipl;
 	void *arg;
 	static int straycount, unexpected;
 	idepth++;
 	ipl = (frame->vec >> 2) - ISRAUTOVEC;
 #ifdef DIAGNOSTIC
 	if ((ipl < 0) || (ipl >= NISRAUTOVEC))
 		panic("%s: bad vec 0x%x", __func__, frame->vec);
 #endif
 	intrcnt[ipl]++;	/* XXXSCW: Will go away soon */
 	mvme68k_irq_evcnt[ipl].ev_count++;
 	curcpu()->ci_data.cpu_nintr++;
 	list = &isr_autovec[ipl];
 	if (list->lh_first == NULL) {
 		printf("%s: ipl %d unexpected\n", __func__, ipl);
 		if (++unexpected > 10)
 			panic("too many unexpected interrupts");
 		idepth--;
 		return;
+	}
 	/* Give all the handlers a chance. */
 	handled = 0;
 	for (isr = list->lh_first ; isr != NULL; isr = isr->isr_link.le_next) {
 		arg = isr->isr_arg ? isr->isr_arg : frame;
 		if ((*isr->isr_func)(arg) != 0) {
 			if (isr->isr_evcnt)
 				isr->isr_evcnt->ev_count++;
 			handled++;
+		}
+	}
 	if (handled)
 		straycount = 0;
 	else if (++straycount > 50)
 		panic("%s: too many stray interrupts", __func__);
 	else
 		printf("%s: stray level %d interrupt\n", __func__, ipl);
 	idepth--;
+}
 /*
  * This is the dispatcher called by the low-level
  * assembly language vectored interrupt routine.
  */
 void
 isrdispatch_vectored(int ipl, struct clockframe *frame)
+{
 	struct isr_vectored *isr;
 	int vec;
 	idepth++;
 	vec = (frame->vec >> 2) - ISRVECTORED;
 #ifdef DIAGNOSTIC
 	if ((vec < 0) || (vec >= NISRVECTORED))
 		panic("%s: bad vec 0x%x", __func__, frame->vec);
 #endif
 	isr = &isr_vectored[vec];
 	intrcnt[ipl]++;	/* XXXSCW: Will go away soon */
 	mvme68k_irq_evcnt[ipl].ev_count++;
 	curcpu()->ci_data.cpu_nintr++;
 	if (isr->isr_func == NULL) {
 		printf("%s: no handler for vec 0x%x\n", __func__, frame->vec);
 		vectab[vec + ISRVECTORED] = badtrap;
 		idepth--;
 		return;
+	}
 	/*
 	 * Handler gets exception frame if argument is NULL.
 	 */
 	if ((*isr->isr_func)(isr->isr_arg ? isr->isr_arg : frame) == 0)
 		printf("%s: vec 0x%x not claimed\n", __func__, frame->vec);
 	else if (isr->isr_evcnt)
 		isr->isr_evcnt->ev_count++;
 	idepth--;
+}
 bool
 cpu_intr_p(void)
+{
 	return idepth != 0;
+}
 /* ARGSUSED */
 static int
 spurintr(void *arg)
+{
 	return 1;
+}

 @@ -1,407 +1,407 @@
-/*	$NetBSD: isr.c,v 1.31 2020/11/21 17:49:20 thorpej Exp $ */
+/*	$NetBSD: isr.c,v 1.32 2021/04/02 12:11:41 rin Exp $ */
 /*
  * This file was taken from mvme68k/mvme68k/isr.c
  * should probably be re-synced when needed.
  * Darrin B. Jewell <jewell@mit.edu>  Tue Nov 10 05:07:16 1998
  * original cvs id: NetBSD: isr.c,v 1.12 1998/07/05 06:49:07 jonathan Exp
  */
 /*-
  * Copyright (c) 1996 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Adam Glass, Gordon W. Ross, and Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Link and dispatch interrupts.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: isr.c,v 1.31 2020/11/21 17:49:20 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: isr.c,v 1.32 2021/04/02 12:11:41 rin Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kmem.h>
 #include <sys/vmmeter.h>
 #include <sys/device.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <uvm/uvm_extern.h>
 #include <next68k/next68k/isr.h>
 #include <next68k/dev/intiovar.h>
 volatile unsigned int interrupt_depth;
 isr_autovec_list_t isr_autovec[NISRAUTOVEC];
 struct	isr_vectored isr_vectored[NISRVECTORED];
 static const char irqgroupname[] = "hard irqs";
 struct	evcnt next68k_irq_evcnt[] = {
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "spur"),
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "lev1"),
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "lev2"),
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "lev3"),
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "lev4"),
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "lev5"),
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "lev6"),
 	EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, irqgroupname, "nmi")
 };
 int idepth;
 int ssir;
-extern	int intrcnt[];		/* from locore.s. XXXSCW: will go away soon */
+extern	u_int intrcnt[];	/* from locore.s. XXXSCW: will go away soon */
 extern	void (*vectab[])(void);
 extern	void badtrap(void);
 extern	void intrhand_vectored(void);
 #if 0
 static	int spurintr(void *);
 #endif
 void
 isrinit(void)
+{
 	int i;
 	/* Initialize the autovector lists. */
 	for (i = 0; i < NISRAUTOVEC; ++i)
 		LIST_INIT(&isr_autovec[i]);
 	/* Initialise the interrupt event counts */
 	for (i = 0; i < (sizeof(next68k_irq_evcnt) / sizeof(struct evcnt)); i++)
 		evcnt_attach_static(&next68k_irq_evcnt[i]);
 	/* Arrange to trap Spurious and NMI auto-vectored Interrupts */
 /* 	isrlink_autovec(spurintr, NULL, 0, 0, NULL); */
 /* 	isrlink_autovec(nmihand, NULL, 7, 0, NULL); */
+}
 /*
  * Establish an autovectored interrupt handler.
  * Called by driver attach functions.
  */
 void
 isrlink_autovec(int (*func)(void *), void *arg, int ipl, int priority,
     struct evcnt *evcnt)
+{
 	struct isr_autovec *newisr, *curisr;
 	isr_autovec_list_t *list;
 #ifdef DIAGNOSTIC
 	if ((ipl < 0) || (ipl >= NISRAUTOVEC))
 		panic("isrlink_autovec: bad ipl %d", ipl);
 #endif
 	newisr = kmem_alloc(sizeof(*newisr), KM_SLEEP);
 	newisr->isr_func = func;
 	newisr->isr_arg = arg;
 	newisr->isr_ipl = ipl;
 	newisr->isr_priority = priority;
 	newisr->isr_evcnt = evcnt;
 	/*
 	 * Some devices are particularly sensitive to interrupt
 	 * handling latency.  The SCC, for example, can lose many
 	 * characters if its interrupt isn't handled with reasonable
 	 * speed.
+	 *
 	 * To work around this problem, each device can give itself a
 	 * "priority".  An unbuffered SCC would give itself a higher
 	 * priority than a SCSI device, for example.
+	 *
 	 * This solution was originally developed for the hp300, which
 	 * has a flat spl scheme (by necessity).  Thankfully, the
 	 * MVME systems don't have this problem, though this may serve
 	 * a useful purpose in any case.
 	 */
 	/*
 	 * Get the appropriate ISR list.  If the list is empty, no
 	 * additional work is necessary; we simply insert ourselves
 	 * at the head of the list.
 	 */
 	list = &isr_autovec[ipl];
 	if (list->lh_first == NULL) {
 		LIST_INSERT_HEAD(list, newisr, isr_link);
 		return;
+	}
 	/*
 	 * A little extra work is required.  We traverse the list
 	 * and place ourselves after any ISRs with our current (or
 	 * higher) priority.
 	 */
 	for (curisr = list->lh_first; curisr->isr_link.le_next != NULL;
 	    curisr = curisr->isr_link.le_next) {
 		if (newisr->isr_priority > curisr->isr_priority) {
 			LIST_INSERT_BEFORE(curisr, newisr, isr_link);
 			return;
+		}
+	}
 	/*
 	 * We're the least important entry, it seems.  We just go
 	 * on the end.
 	 */
 	LIST_INSERT_AFTER(curisr, newisr, isr_link);
+}
 /*
  * Establish a vectored interrupt handler.
  * Called by bus interrupt establish functions.
  */
 void
 isrlink_vectored(int (*func)(void *), void *arg, int ipl, int vec,
     struct evcnt *evcnt)
+{
 	struct isr_vectored *isr;
 #ifdef DIAGNOSTIC
 	if ((ipl < 0) || (ipl >= NISRAUTOVEC))
 		panic("isrlink_vectored: bad ipl %d", ipl);
 	if ((vec < ISRVECTORED) || (vec >= ISRVECTORED + NISRVECTORED))
 		panic("isrlink_vectored: bad vec 0x%x", vec);
 #endif
 	isr = &isr_vectored[vec - ISRVECTORED];
 #ifdef DIAGNOSTIC
 	if ((vectab[vec] != badtrap) || (isr->isr_func != NULL))
 		panic("isrlink_vectored: vec 0x%x not available", vec);
 #endif
 	/* Fill in the new entry. */
 	isr->isr_func = func;
 	isr->isr_arg = arg;
 	isr->isr_ipl = ipl;
 	isr->isr_evcnt = evcnt;
 	/* Hook into the vector table. */
 	vectab[vec] = intrhand_vectored;
+}
 /*
  * Return a pointer to the evcnt structure for
  * the specified ipl.
  */
 struct evcnt *
 isrlink_evcnt(int ipl)
+{
 #ifdef DIAGNOSTIC
 	if (ipl < 0 ||
 	    ipl >= (sizeof(next68k_irq_evcnt) / sizeof(struct evcnt)))
 		panic("isrlink_evcnt: bad ipl %d", ipl);
 #endif
 	return (&next68k_irq_evcnt[ipl]);
+}
 /*
  * Unhook a vectored interrupt.
  */
 void
 isrunlink_vectored(int vec)
+{
 #ifdef DIAGNOSTIC
 	if ((vec < ISRVECTORED) || (vec >= ISRVECTORED + NISRVECTORED))
 		panic("isrunlink_vectored: bad vec 0x%x", vec);
 	if (vectab[vec] != intrhand_vectored)
 		panic("isrunlink_vectored: not vectored interrupt");
 #endif
 	vectab[vec] = badtrap;
 	memset(&isr_vectored[vec - ISRVECTORED], 0, sizeof(struct isr_vectored));
+}
 /*
  * This is the dispatcher called by the low-level
  * assembly language autovectored interrupt routine.
  */
 void
 isrdispatch_autovec(struct clockframe *frame)
+{
 	struct isr_autovec *isr;
 	isr_autovec_list_t *list;
 	int handled, ipl;
 	void *arg;
 	static int straycount, unexpected;
 #ifdef INTRLOG
 	static int logptr = 0;
 	static struct {
 		int ipl;
 		u_long intrstat, intrmask;
 		int handled;
 	} log[256];
 #endif
 	idepth++;
 	ipl = (frame->vec >> 2) - ISRAUTOVEC;
 #ifdef DIAGNOSTIC
 	if ((ipl < 0) || (ipl >= NISRAUTOVEC))
 		panic("isrdispatch_autovec: bad vec 0x%x", frame->vec);
 #endif
 	intrcnt[ipl]++; /* XXXSCW: Will go away soon */
 	next68k_irq_evcnt[ipl].ev_count++;
 	curcpu()->ci_data.cpu_nintr++;
 #ifdef INTRLOG
 	log[logptr].ipl = ipl;
 	log[logptr].intrstat = *intrstat;
 	log[logptr].intrmask = *intrmask;
 #endif
 	list = &isr_autovec[ipl];
 	if (list->lh_first == NULL) {
 		printf("isrdispatch_autovec: ipl %d unexpected\n", ipl);
 		if (++unexpected > 10)
 			panic("too many unexpected interrupts");
 		idepth--;
 		return;
+	}
 	/* Give all the handlers a chance. */
 	handled = 0;
 	for (isr = list->lh_first ; isr != NULL; isr = isr->isr_link.le_next) {
 		arg = isr->isr_arg ? isr->isr_arg : frame;
 		if ((*isr->isr_func)(arg) != 0) {
 			if (isr->isr_evcnt)
 				isr->isr_evcnt->ev_count++;
 			handled++;
+		}
+	}
 #ifdef INTRLOG
 	log[logptr].handled = handled;
 	logptr = (logptr + 1) & 255;
 	if (!handled && ++straycount >= 10) {
 		int n, m;
 		printf("%d stray interrupts, level %d\n", straycount, ipl);
 		for (n = 20; n; n--) {
 			m = (logptr - n) & 255;
 			printf("%02d: %d %08lx %08lx %d\n", n, log[m].ipl,
 			    log[m].intrstat, log[m].intrmask, log[m].handled);
+		}
 		Debugger();
 		straycount = 0;
+	}
 #else
 	if (handled)
 		straycount = 0;
 	else if (++straycount > 50)
 		panic("isr_dispatch_autovec: too many stray interrupts");
 	else {
 		char sbuf[256];
 		printf("isrdispatch_autovec: stray level %d interrupt\n", ipl);
 		snprintb(sbuf, sizeof(sbuf), NEXT_INTR_BITS,
 		    (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)));
 		printf("  *intrstat = %s\n", sbuf);
 		snprintb(sbuf, sizeof(sbuf), NEXT_INTR_BITS,
 		    (*(volatile u_long *)IIOV(NEXT_P_INTRMASK)));
 		printf("  *intrmask = %s\n", sbuf);
+	}
 #endif
 	idepth--;
+}
 bool
 cpu_intr_p(void)
+{
 	return idepth != 0;
+}
 /*
  * This is the dispatcher called by the low-level
  * assembly language vectored interrupt routine.
  */
 void
 isrdispatch_vectored(int ipl, struct clockframe *frame)
+{
 	struct isr_vectored *isr;
 	int vec;
 	vec = (frame->vec >> 2) - ISRVECTORED;
 #ifdef DIAGNOSTIC
 	if ((vec < 0) || (vec >= NISRVECTORED))
 		panic("isrdispatch_vectored: bad vec 0x%x", frame->vec);
 #endif
 	isr = &isr_vectored[vec];
 	intrcnt[ipl]++; /* XXXSCW: Will go away soon */
 	next68k_irq_evcnt[ipl].ev_count++;
 	curcpu()->ci_data.cpu_nintr++;
 	if (isr->isr_func == NULL) {
 		printf("isrdispatch_vectored: no handler for vec 0x%x\n",
 		    frame->vec);
 		vectab[vec + ISRVECTORED] = badtrap;
 		return;
+	}
 	/*
 	 * Handler gets exception frame if argument is NULL.
 	 */
 	if ((*isr->isr_func)(isr->isr_arg ? isr->isr_arg : frame) == 0)
 		printf("isrdispatch_vectored: vec 0x%x not claimed\n",
 		    frame->vec);
 	else
 	if (isr->isr_evcnt)
 		isr->isr_evcnt->ev_count++;
+}
 #if 0
 /* ARGSUSED */
 static int
 spurintr(void *arg)
+{
 	return (1);
+}
 #endif
 const uint16_t ipl2psl_table[NIPL] = {
 	[IPL_NONE]       = PSL_S | PSL_IPL0,
 	[IPL_SOFTCLOCK]  = PSL_S | PSL_IPL1,
 	[IPL_SOFTNET]    = PSL_S | PSL_IPL1,
 	[IPL_SOFTSERIAL] = PSL_S | PSL_IPL1,
 	[IPL_SOFTBIO]    = PSL_S | PSL_IPL1,
 	[IPL_VM]         = PSL_S | PSL_IPL6,
 	[IPL_SCHED]      = PSL_S | PSL_IPL7,
 	[IPL_HIGH]       = PSL_S | PSL_IPL7,
 };

 @@ -1,335 +1,335 @@
-/*	$NetBSD: clock.c,v 1.64 2013/09/07 15:56:11 tsutsui Exp $	*/
+/*	$NetBSD: clock.c,v 1.65 2021/04/02 12:11:41 rin Exp $	*/
 /*
  * Copyright (c) 1982, 1990, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This code is derived from software contributed to Berkeley by
  * the Systems Programming Group of the University of Utah Computer
  * Science Department.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	from: Utah Hdr: clock.c 1.18 91/01/21$
  *	from: @(#)clock.c	8.2 (Berkeley) 1/12/94
  */
 /*
  * Copyright (c) 1994 Gordon W. Ross
  * Copyright (c) 1993 Adam Glass
  * Copyright (c) 1988 University of Utah.
+ *
  * This code is derived from software contributed to Berkeley by
  * the Systems Programming Group of the University of Utah Computer
  * Science Department.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by the University of
  *	California, Berkeley and its contributors.
  * 4. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	from: Utah Hdr: clock.c 1.18 91/01/21$
  *	from: @(#)clock.c	8.2 (Berkeley) 1/12/94
  */
 /*
  * Machine-dependent clock routines for the Intersil 7170:
  * Original by Adam Glass;  partially rewritten by Gordon Ross.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.64 2013/09/07 15:56:11 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.65 2021/04/02 12:11:41 rin Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/time.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 #include <uvm/uvm_extern.h>
 #include <m68k/asm_single.h>
 #include <machine/autoconf.h>
 #include <machine/bus.h>
 #include <machine/cpu.h>
 #include <machine/leds.h>
 #include <sun3/sun3/control.h>
 #include <sun3/sun3/interreg.h>
 #include <sun3/sun3/machdep.h>
 #include <dev/clock_subr.h>
 #include <dev/ic/intersil7170reg.h>
 #include <dev/ic/intersil7170var.h>
-extern int intrcnt[];
+extern u_int intrcnt[];
 #define	CLOCK_PRI	5
 #define IREG_CLK_BITS	(IREG_CLOCK_ENAB_7 | IREG_CLOCK_ENAB_5)
 void _isr_clock(void);	/* in locore.s */
 void clock_intr(struct clockframe);
 static volatile void *intersil_va;
 #define intersil_clock ((volatile struct intersil7170 *)intersil_va)
 #define intersil_clear() (void)intersil_clock->clk_intr_reg
 static int  oclock_match(device_t, cfdata_t, void *);
 static void oclock_attach(device_t, device_t, void *);
 CFATTACH_DECL_NEW(oclock, sizeof(struct intersil7170_softc),
     oclock_match, oclock_attach, NULL, NULL);
 static int
 oclock_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct confargs *ca = aux;
 	/* This driver only supports one unit. */
 	if (intersil_va)
 		return 0;
 	/* Make sure there is something there... */
 	if (bus_peek(ca->ca_bustype, ca->ca_paddr, 1) == -1)
 		return 0;
 	/* Default interrupt priority. */
 	if (ca->ca_intpri == -1)
 		ca->ca_intpri = CLOCK_PRI;
 	return 1;
+}
 static void
 oclock_attach(device_t parent, device_t self, void *aux)
+{
 	struct intersil7170_softc *sc = device_private(self);
 	struct confargs *ca = aux;
 	sc->sc_dev = self;
 	/* Get a mapping for it. */
 	sc->sc_bst = ca->ca_bustag;
 	if (bus_space_map(sc->sc_bst, ca->ca_paddr, sizeof(struct intersil7170),
 , &sc->sc_bsh) != 0) {
 		aprint_error(": can't map registers\n");
 		return;
+	}
 	intersil_va = bus_space_vaddr(sc->sc_bst, sc->sc_bsh);
 	/*
 	 * Set the clock to the correct interrupt rate, but
 	 * do not enable the interrupt until cpu_initclocks.
 	 * XXX: Actually, the interrupt_reg should be zero
 	 * at this point, so the clock interrupts should not
 	 * affect us, but we need to set the rate...
 	 */
 	bus_space_write_1(sc->sc_bst, sc->sc_bsh, INTERSIL_ICMD,
 	    INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE));
 	(void)bus_space_read_1(sc->sc_bst, sc->sc_bsh, INTERSIL_IINTR);
 	/* Set the clock to 100 Hz, but do not enable it yet. */
 	bus_space_write_1(sc->sc_bst, sc->sc_bsh,
 	    INTERSIL_IINTR, INTERSIL_INTER_CSECONDS);
 	sc->sc_year0 = 1968;
 	intersil7170_attach(sc);
 	aprint_normal("\n");
 	/*
 	 * Can not hook up the ISR until cpu_initclocks()
 	 * because hardclock is not ready until then.
 	 * For now, the handler is _isr_autovec(), which
 	 * will complain if it gets clock interrupts.
 	 */
+}
 /*
  * Set and/or clear the desired clock bits in the interrupt
  * register.  We have to be extremely careful that we do it
  * in such a manner that we don't get ourselves lost.
  * XXX:  Watch out!  It's really easy to break this!
  */
 void
 set_clk_mode(u_char on, u_char off, int enable_clk)
+{
 	u_char interreg;
 	/*
 	 * If we have not yet mapped the register,
 	 * then we do not want to do any of this...
 	 */
 	if (!interrupt_reg)
 		return;
 #ifdef	DIAGNOSTIC
 	/* Assertion: were are at splhigh! */
 	if ((getsr() & PSL_IPL) < PSL_IPL7)
 		panic("set_clk_mode: bad ipl");
 #endif
 	/*
 	 * make sure that we are only playing w/
 	 * clock interrupt register bits
 	 */
 	on  &= IREG_CLK_BITS;
 	off &= IREG_CLK_BITS;
 	/* First, turn off the "master" enable bit. */
 	single_inst_bclr_b(*interrupt_reg, IREG_ALL_ENAB);
 	/*
 	 * Save the current interrupt register clock bits,
 	 * and turn off/on the requested bits in the copy.
 	 */
 	interreg = *interrupt_reg & IREG_CLK_BITS;
 	interreg &= ~off;
 	interreg |= on;
 	/* Clear the CLK5 and CLK7 bits to clear the flip-flops. */
 	single_inst_bclr_b(*interrupt_reg, IREG_CLK_BITS);
 	if (intersil_va) {
 		/*
 		 * Then disable clock interrupts, and read the clock's
 		 * interrupt register to clear any pending signals there.
 		 */
 		intersil_clock->clk_cmd_reg =
 		    INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE);
 		intersil_clear();
+	}
 	/* Set the requested bits in the interrupt register. */
 	single_inst_bset_b(*interrupt_reg, interreg);
 	/* Turn the clock back on (maybe) */
 	if (intersil_va && enable_clk)
 		intersil_clock->clk_cmd_reg =
 		    INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE);
 	/* Finally, turn the "master" enable back on. */
 	single_inst_bset_b(*interrupt_reg, IREG_ALL_ENAB);
+}
 /*
  * Set up the real-time clock (enable clock interrupts).
  * Leave stathz 0 since there is no secondary clock available.
  * Note that clock interrupts MUST STAY DISABLED until here.
  */
 void
 cpu_initclocks(void)
+{
 	int s;
 	s = splhigh();
 	/* Install isr (in locore.s) that calls clock_intr(). */
 	isr_add_custom(CLOCK_PRI, (void *)_isr_clock);
 	/* Now enable the clock at level 5 in the interrupt reg. */
 	set_clk_mode(IREG_CLOCK_ENAB_5, 0, 1);
 	splx(s);
+}
 /*
  * This doesn't need to do anything, as we have only one timer and
  * profhz==stathz==hz.
  */
 void
 setstatclockrate(int newhz)
+{
 	/* nothing */
+}
 /*
  * This is called by the "custom" interrupt handler.
  * Note that we can get ZS interrupts while this runs,
  * and zshard may touch the interrupt_reg, so we must
  * be careful to use the single_inst_* macros to modify
  * the interrupt register atomically.
  */
 void
 clock_intr(struct clockframe cf)
+{
 	idepth++;
 	/* Read the clock interrupt register. */
 	intersil_clear();
 	/* Pulse the clock intr. enable low. */
 	single_inst_bclr_b(*interrupt_reg, IREG_CLOCK_ENAB_5);
 	single_inst_bset_b(*interrupt_reg, IREG_CLOCK_ENAB_5);
 	/* Read the clock intr. reg. AGAIN! */
 	intersil_clear();
 	intrcnt[CLOCK_PRI]++;
 	curcpu()->ci_data.cpu_nintr++;
 	{ /* Entertainment! */
 #ifdef	LED_IDLE_CHECK
 		/* With this option, LEDs move only when CPU is idle. */
 		extern char _Idle[];	/* locore.s */
 		if (cf.cf_pc == (long)_Idle)
 #endif
 			leds_intr();
+	}
 	/* Call common clock interrupt handler. */
 	hardclock(&cf);
 	idepth--;
+}

 @@ -1,456 +1,456 @@
-/*	$NetBSD: clock.c,v 1.40 2013/09/06 17:43:19 tsutsui Exp $	*/
+/*	$NetBSD: clock.c,v 1.41 2021/04/02 12:11:41 rin Exp $	*/
 /*
  * Copyright (c) 1982, 1990, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This code is derived from software contributed to Berkeley by
  * the Systems Programming Group of the University of Utah Computer
  * Science Department.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	from: Utah Hdr: clock.c 1.18 91/01/21$
  *	from: @(#)clock.c	8.2 (Berkeley) 1/12/94
  */
 /*
  * Copyright (c) 1994 Gordon W. Ross
  * Copyright (c) 1993 Adam Glass
  * Copyright (c) 1988 University of Utah.
+ *
  * This code is derived from software contributed to Berkeley by
  * the Systems Programming Group of the University of Utah Computer
  * Science Department.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by the University of
  *	California, Berkeley and its contributors.
  * 4. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	from: Utah Hdr: clock.c 1.18 91/01/21$
  *	from: @(#)clock.c	8.2 (Berkeley) 1/12/94
  */
 /*
  * Machine-dependent clock routines.  Sun3X machines may have
  * either the Mostek 48T02 or the Intersil 7170 clock.
+ *
  * It is tricky to determine which you have, because there is
  * always something responding at the address where the Mostek
  * clock might be found: either a Mostek or plain-old EEPROM.
  * Therefore, we cheat.  If we find an Intersil clock, assume
  * that what responds at the end of the EEPROM space is just
  * plain-old EEPROM (not a Mostek clock).  Worse, there are
  * H/W problems with probing for an Intersil on the 3/80, so
  * on that machine we "know" there is a Mostek clock.
+ *
  * Note that the probing algorithm described above requires
  * that we probe the intersil before we probe the mostek!
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.40 2013/09/06 17:43:19 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.41 2021/04/02 12:11:41 rin Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/time.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 #include <uvm/uvm_extern.h>
 #include <m68k/asm_single.h>
 #include <machine/autoconf.h>
 #include <machine/bus.h>
 #include <machine/cpu.h>
 #include <machine/idprom.h>
 #include <machine/leds.h>
 #include <dev/clock_subr.h>
 #include <dev/ic/intersil7170reg.h>
 #include <dev/ic/intersil7170var.h>
 #include <dev/ic/mk48txxreg.h>
 #include <dev/ic/mk48txxvar.h>
 #include <sun3/sun3/machdep.h>
 #include <sun3/sun3/interreg.h>
-extern int intrcnt[];
+extern u_int intrcnt[];
 #define SUN3_470	Yes
 #define	CLOCK_PRI	5
 #define IREG_CLK_BITS	(IREG_CLOCK_ENAB_7 | IREG_CLOCK_ENAB_5)
 #define MKCLOCK_REG_OFFSET	(MK48T02_CLKOFF + MK48TXX_ICSR)
 /*
  * Only one of these two variables should be non-zero after
  * autoconfiguration determines which clock we have.
  */
 static volatile void *intersil_va;
 static volatile void *mostek_clk_va;
 void _isr_clock(void);	/* in locore.s */
 void clock_intr(struct clockframe);
 static int  clock_match(device_t, cfdata_t, void *);
 static void clock_attach(device_t, device_t, void *);
 CFATTACH_DECL_NEW(clock, sizeof(struct mk48txx_softc),
     clock_match, clock_attach, NULL, NULL);
 #ifdef	SUN3_470
 #define intersil_clock ((volatile struct intersil7170 *)intersil_va)
 #define intersil_clear() (void)intersil_clock->clk_intr_reg
 static int  oclock_match(device_t, cfdata_t, void *);
 static void oclock_attach(device_t, device_t, void *);
 CFATTACH_DECL_NEW(oclock, sizeof(struct intersil7170_softc),
     oclock_match, oclock_attach, NULL, NULL);
 /*
  * Is there an intersil clock?
  */
 static int
 oclock_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct confargs *ca = aux;
 	/* This driver only supports one unit. */
 	if (intersil_va)
 		return 0;
 	/*
 	 * The 3/80 can not probe the Intersil absent,
 	 * but it never has one, so "just say no."
 	 */
 	if (cpu_machine_id == ID_SUN3X_80)
 		return 0;
 	/* OK, really probe for the Intersil. */
 	if (bus_peek(ca->ca_bustype, ca->ca_paddr, 1) == -1)
 		return 0;
 	/* Default interrupt priority. */
 	if (ca->ca_intpri == -1)
 		ca->ca_intpri = CLOCK_PRI;
 	return 1;
+}
 /*
  * Attach the intersil clock.
  */
 static void
 oclock_attach(device_t parent, device_t self, void *aux)
+{
 	struct intersil7170_softc *sc = device_private(self);
 	struct confargs *ca = aux;
 	sc->sc_dev = self;
 	/* Get a mapping for it. */
 	sc->sc_bst = ca->ca_bustag;
 	if (bus_space_map(sc->sc_bst, ca->ca_paddr, sizeof(struct intersil7170),
 , &sc->sc_bsh) != 0) {
 		aprint_error(": can't map registers\n");
 		return;
+	}
 	intersil_va = bus_space_vaddr(sc->sc_bst, sc->sc_bsh);
 #ifdef	DIAGNOSTIC
 	/* Verify correct probe order... */
 	if (mostek_clk_va) {
 		mostek_clk_va = NULL;
 		aprint_normal("\n");
 		aprint_error_dev(self, "warning - mostek found also!\n");
+	}
 #endif
 	/*
 	 * Set the clock to the correct interrupt rate, but
 	 * do not enable the interrupt until cpu_initclocks.
 	 * XXX: Actually, the interrupt_reg should be zero
 	 * at this point, so the clock interrupts should not
 	 * affect us, but we need to set the rate...
 	 */
 	bus_space_write_1(sc->sc_bst, sc->sc_bsh, INTERSIL_ICMD,
 	    INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE));
 	(void)bus_space_read_1(sc->sc_bst, sc->sc_bsh, INTERSIL_IINTR);
 	/* Set the clock to 100 Hz, but do not enable it yet. */
 	bus_space_write_1(sc->sc_bst, sc->sc_bsh,
 	    INTERSIL_IINTR, INTERSIL_INTER_CSECONDS);
 	sc->sc_year0 = 1968;
 	intersil7170_attach(sc);
 	aprint_normal("\n");
 	/*
 	 * Can not hook up the ISR until cpu_initclocks()
 	 * because hardclock is not ready until then.
 	 * For now, the handler is _isr_autovec(), which
 	 * will complain if it gets clock interrupts.
 	 */
+}
 #endif	/* SUN3_470 */
 /*
  * Is there a Mostek clock?  Hard to tell...
  * (See comment at top of this file.)
  */
 static int
 clock_match(device_t parent, cfdata_t cf, void *args)
+{
 	struct confargs *ca = args;
 	/* This driver only supports one unit. */
 	if (mostek_clk_va)
 		return 0;
 	/* If intersil was found, use that. */
 	if (intersil_va)
 		return 0;
 	/* Else assume a Mostek is there... */
 	/* Default interrupt priority. */
 	if (ca->ca_intpri == -1)
 		ca->ca_intpri = CLOCK_PRI;
 	return 1;
+}
 /*
  * Attach the mostek clock.
  */
 static void
 clock_attach(device_t parent, device_t self, void *aux)
+{
 	struct mk48txx_softc *sc = device_private(self);
 	struct confargs *ca = aux;
 	sc->sc_dev = self;
 	sc->sc_bst = ca->ca_bustag;
 	if (bus_space_map(sc->sc_bst, ca->ca_paddr - MKCLOCK_REG_OFFSET,
 	    MK48T02_CLKSZ, 0, &sc->sc_bsh) != 0) {
 		aprint_error(": can't map device space\n");
 		return;
+	}
 	mostek_clk_va = bus_space_vaddr(sc->sc_bst, sc->sc_bsh);
 	sc->sc_model = "mk48t02";
 	sc->sc_year0 = 1968;
 	mk48txx_attach(sc);
 	aprint_normal("\n");
+}
 /*
  * Set and/or clear the desired clock bits in the interrupt
  * register.  We have to be extremely careful that we do it
  * in such a manner that we don't get ourselves lost.
  * XXX:  Watch out!  It's really easy to break this!
  */
 void
 set_clk_mode(u_char on, u_char off, int enable_clk)
+{
 	u_char interreg;
 	/*
 	 * If we have not yet mapped the register,
 	 * then we do not want to do any of this...
 	 */
 	if (!interrupt_reg)
 		return;
 #ifdef	DIAGNOSTIC
 	/* Assertion: were are at splhigh! */
 	if ((getsr() & PSL_IPL) < PSL_IPL7)
 		panic("set_clk_mode: bad ipl");
 #endif
 	/*
 	 * make sure that we are only playing w/
 	 * clock interrupt register bits
 	 */
 	on  &= IREG_CLK_BITS;
 	off &= IREG_CLK_BITS;
 	/* First, turn off the "master" enable bit. */
 	single_inst_bclr_b(*interrupt_reg, IREG_ALL_ENAB);
 	/*
 	 * Save the current interrupt register clock bits,
 	 * and turn off/on the requested bits in the copy.
 	 */
 	interreg = *interrupt_reg & IREG_CLK_BITS;
 	interreg &= ~off;
 	interreg |= on;
 	/* Clear the CLK5 and CLK7 bits to clear the flip-flops. */
 	single_inst_bclr_b(*interrupt_reg, IREG_CLK_BITS);
 #ifdef	SUN3_470
 	if (intersil_va) {
 		/*
 		 * Then disable clock interrupts, and read the clock's
 		 * interrupt register to clear any pending signals there.
 		 */
 		intersil_clock->clk_cmd_reg =
 		    INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE);
 		intersil_clear();
+	}
 #endif	/* SUN3_470 */
 	/* Set the requested bits in the interrupt register. */
 	single_inst_bset_b(*interrupt_reg, interreg);
 #ifdef	SUN3_470
 	/* Turn the clock back on (maybe) */
 	if (intersil_va && enable_clk)
 		intersil_clock->clk_cmd_reg =
 		    INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE);
 #endif	/* SUN3_470 */
 	/* Finally, turn the "master" enable back on. */
 	single_inst_bset_b(*interrupt_reg, IREG_ALL_ENAB);
+}
 /*
  * Set up the real-time clock (enable clock interrupts).
  * Leave stathz 0 since there is no secondary clock available.
  * Note that clock interrupts MUST STAY DISABLED until here.
  */
 void
 cpu_initclocks(void)
+{
 	int s;
 	s = splhigh();
 	/* Install isr (in locore.s) that calls clock_intr(). */
 	isr_add_custom(CLOCK_PRI, (void *)_isr_clock);
 	/* Now enable the clock at level 5 in the interrupt reg. */
 	set_clk_mode(IREG_CLOCK_ENAB_5, 0, 1);
 	splx(s);
+}
 /*
  * This doesn't need to do anything, as we have only one timer and
  * profhz==stathz==hz.
  */
 void
 setstatclockrate(int newhz)
+{
 	/* nothing */
+}
 /*
  * Clock interrupt handler (for both Intersil and Mostek).
  * XXX - Is it worth the trouble to save a few cycles here
  * by making two separate interrupt handlers?
+ *
  * This is called by the "custom" interrupt handler.
  * Note that we can get ZS interrupts while this runs,
  * and zshard may touch the interrupt_reg, so we must
  * be careful to use the single_inst_* macros to modify
  * the interrupt register atomically.
  */
 void
 clock_intr(struct clockframe cf)
+{
 	extern char _Idle[];	/* locore.s */
 	idepth++;
 #ifdef	SUN3_470
 	if (intersil_va) {
 		/* Read the clock interrupt register. */
 		intersil_clear();
+	}
 #endif	/* SUN3_470 */
 	/* Pulse the clock intr. enable low. */
 	single_inst_bclr_b(*interrupt_reg, IREG_CLOCK_ENAB_5);
 	single_inst_bset_b(*interrupt_reg, IREG_CLOCK_ENAB_5);
 #ifdef	SUN3_470
 	if (intersil_va) {
 		/* Read the clock intr. reg. AGAIN! */
 		intersil_clear();
+	}
 #endif	/* SUN3_470 */
 	intrcnt[CLOCK_PRI]++;
 	curcpu()->ci_data.cpu_nintr++;
 	/* Entertainment! */
 	if (cf.cf_pc == (long)_Idle)
 		leds_intr();
 	/* Call common clock interrupt handler. */
 	hardclock(&cf);
 	idepth--;
+}